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e8a3931d JB |
1 | /* linux/arch/arm/mach-s5p6442/dev-spi.c |
2 | * | |
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
4 | * Jaswinder Singh <jassi.brar@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/dma-mapping.h> | |
1c739c7f | 13 | #include <linux/gpio.h> |
e8a3931d JB |
14 | |
15 | #include <mach/dma.h> | |
16 | #include <mach/map.h> | |
17 | #include <mach/irqs.h> | |
e8a3931d JB |
18 | #include <mach/spi-clocks.h> |
19 | ||
20 | #include <plat/s3c64xx-spi.h> | |
21 | #include <plat/gpio-cfg.h> | |
22 | ||
23 | static char *spi_src_clks[] = { | |
24 | [S5P6442_SPI_SRCCLK_PCLK] = "pclk", | |
25 | [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll", | |
26 | }; | |
27 | ||
28 | /* SPI Controller platform_devices */ | |
29 | ||
30 | /* Since we emulate multi-cs capability, we do not touch the CS. | |
31 | * The emulated CS is toggled by board specific mechanism, as it can | |
32 | * be either some immediate GPIO or some signal out of some other | |
33 | * chip in between ... or some yet another way. | |
34 | * We simply do not assume anything about CS. | |
35 | */ | |
36 | static int s5p6442_spi_cfg_gpio(struct platform_device *pdev) | |
37 | { | |
38 | switch (pdev->id) { | |
39 | case 0: | |
40 | s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2)); | |
e8a3931d | 41 | s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP); |
70081472 KK |
42 | s3c_gpio_cfgall_range(S5P6442_GPB(2), 2, |
43 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | |
e8a3931d JB |
44 | break; |
45 | ||
46 | default: | |
47 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | |
48 | return -EINVAL; | |
49 | } | |
50 | ||
51 | return 0; | |
52 | } | |
53 | ||
54 | static struct resource s5p6442_spi0_resource[] = { | |
55 | [0] = { | |
56 | .start = S5P6442_PA_SPI, | |
57 | .end = S5P6442_PA_SPI + 0x100 - 1, | |
58 | .flags = IORESOURCE_MEM, | |
59 | }, | |
60 | [1] = { | |
61 | .start = DMACH_SPI0_TX, | |
62 | .end = DMACH_SPI0_TX, | |
63 | .flags = IORESOURCE_DMA, | |
64 | }, | |
65 | [2] = { | |
66 | .start = DMACH_SPI0_RX, | |
67 | .end = DMACH_SPI0_RX, | |
68 | .flags = IORESOURCE_DMA, | |
69 | }, | |
70 | [3] = { | |
71 | .start = IRQ_SPI0, | |
72 | .end = IRQ_SPI0, | |
73 | .flags = IORESOURCE_IRQ, | |
74 | }, | |
75 | }; | |
76 | ||
77 | static struct s3c64xx_spi_info s5p6442_spi0_pdata = { | |
78 | .cfg_gpio = s5p6442_spi_cfg_gpio, | |
79 | .fifo_lvl_mask = 0x1ff, | |
80 | .rx_lvl_offset = 15, | |
81 | }; | |
82 | ||
83 | static u64 spi_dmamask = DMA_BIT_MASK(32); | |
84 | ||
85 | struct platform_device s5p6442_device_spi = { | |
86 | .name = "s3c64xx-spi", | |
87 | .id = 0, | |
88 | .num_resources = ARRAY_SIZE(s5p6442_spi0_resource), | |
89 | .resource = s5p6442_spi0_resource, | |
90 | .dev = { | |
91 | .dma_mask = &spi_dmamask, | |
92 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
93 | .platform_data = &s5p6442_spi0_pdata, | |
94 | }, | |
95 | }; | |
96 | ||
97 | void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | |
98 | { | |
99 | struct s3c64xx_spi_info *pd; | |
100 | ||
101 | /* Reject invalid configuration */ | |
102 | if (!num_cs || src_clk_nr < 0 | |
103 | || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) { | |
104 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | |
105 | return; | |
106 | } | |
107 | ||
108 | switch (cntrlr) { | |
109 | case 0: | |
110 | pd = &s5p6442_spi0_pdata; | |
111 | break; | |
112 | default: | |
113 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | |
114 | __func__, cntrlr); | |
115 | return; | |
116 | } | |
117 | ||
118 | pd->num_cs = num_cs; | |
119 | pd->src_clk_nr = src_clk_nr; | |
120 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | |
121 | } |