[net-next-2.6.git] / arch / arm / mach-s3c64xx / mach-smdk6410.c

/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/smsc911x.h>
#include <linux/regulator/fixed.h>

#ifdef CONFIG_SMDK6410_WM1190_EV1
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#ifdef CONFIG_SMDK6410_WM1192_EV1
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#endif

#include <video/platform_lcd.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>

#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <mach/regs-modem.h>
#include <mach/regs-gpio.h>
#include <mach/regs-sys.h>
#include <mach/regs-srom.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>

#include <mach/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/adc.h>
#include <plat/ts.h>

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[3] = {
		.hwport	     = 3,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
};

/* framebuffer and LCD setup. */

/* GPF15 = LCD backlight control
 * GPF13 => Panel power
 * GPN5 = LCD nRESET signal
 * PWM_TOUT1 => backlight brightness
 */

static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power) {
		gpio_direction_output(S3C64XX_GPF(13), 1);
		gpio_direction_output(S3C64XX_GPF(15), 1);

		/* fire nRESET on power up */
		gpio_direction_output(S3C64XX_GPN(5), 0);
		msleep(10);
		gpio_direction_output(S3C64XX_GPN(5), 1);
		msleep(1);
	} else {
		gpio_direction_output(S3C64XX_GPF(15), 0);
		gpio_direction_output(S3C64XX_GPF(13), 0);
	}
}

static struct plat_lcd_data smdk6410_lcd_power_data = {
	.set_power	= smdk6410_lcd_power_set,
};

static struct platform_device smdk6410_lcd_powerdev = {
	.name			= "platform-lcd",
	.dev.parent		= &s3c_device_fb.dev,
	.dev.platform_data	= &smdk6410_lcd_power_data,
};

static struct s3c_fb_pd_win smdk6410_fb_win0 = {
	/* this is to ensure we use win0 */
	.win_mode	= {
		.left_margin	= 8,
		.right_margin	= 13,
		.upper_margin	= 7,
		.lower_margin	= 5,
		.hsync_len	= 3,
		.vsync_len	= 1,
		.xres		= 800,
		.yres		= 480,
	},
	.max_bpp	= 32,
	.default_bpp	= 16,
};

/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.win[0]		= &smdk6410_fb_win0,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

/*
 * Configuring Ethernet on SMDK6410
 *
 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
 * The constant address below corresponds to nCS1
 *
 *  1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
 *  2) CFG6 needs to be switched to "LAN9115" side
 */

static struct resource smdk6410_smsc911x_resources[] = {
	[0] = {
		.start = S3C64XX_PA_XM0CSN1,
		.end   = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C_EINT(10),
		.end   = S3C_EINT(10),
		.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
	},
};

static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
	.irq_polarity  = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type      = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.flags         = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface = PHY_INTERFACE_MODE_MII,
};


static struct platform_device smdk6410_smsc911x = {
	.name          = "smsc911x",
	.id            = -1,
	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
	.resource      = &smdk6410_smsc911x_resources[0],
	.dev = {
		.platform_data = &smdk6410_smsc911x_pdata,
	},
};

#ifdef CONFIG_REGULATOR
static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
	{
		/* WM8580 */
		.supply = "PVDD",
		.dev_name = "0-001b",
	},
	{
		/* WM8580 */
		.supply = "AVDD",
		.dev_name = "0-001b",
	},
};

static struct regulator_init_data smdk6410_b_pwr_5v_data = {
	.constraints = {
		.always_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
};

static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
	.supply_name = "B_PWR_5V",
	.microvolts = 5000000,
	.init_data = &smdk6410_b_pwr_5v_data,
	.gpio = -EINVAL,
};

static struct platform_device smdk6410_b_pwr_5v = {
	.name          = "reg-fixed-voltage",
	.id            = -1,
	.dev = {
		.platform_data = &smdk6410_b_pwr_5v_pdata,
	},
};
#endif

static struct map_desc smdk6410_iodesc[] = {};

static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
	&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
	&s3c_device_hsmmc1,
#endif
	&s3c_device_i2c0,
	&s3c_device_i2c1,
	&s3c_device_fb,
	&s3c_device_ohci,
	&s3c_device_usb_hsotg,
	&s3c64xx_device_iisv4,

#ifdef CONFIG_REGULATOR
	&smdk6410_b_pwr_5v,
#endif
	&smdk6410_lcd_powerdev,

	&smdk6410_smsc911x,
	&s3c_device_adc,
	&s3c_device_ts,
	&s3c_device_wdt,
};

#ifdef CONFIG_REGULATOR
/* ARM core */
static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
	{
		.supply = "vddarm",
	}
};

/* VDDARM, BUCK1 on J5 */
static struct regulator_init_data smdk6410_vddarm = {
	.constraints = {
		.name = "PVDD_ARM",
		.min_uV = 1000000,
		.max_uV = 1300000,
		.always_on = 1,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	},
	.num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
	.consumer_supplies = smdk6410_vddarm_consumers,
};

/* VDD_INT, BUCK2 on J5 */
static struct regulator_init_data smdk6410_vddint = {
	.constraints = {
		.name = "PVDD_INT",
		.min_uV = 1000000,
		.max_uV = 1200000,
		.always_on = 1,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	},
};

/* VDD_HI, LDO3 on J5 */
static struct regulator_init_data smdk6410_vddhi = {
	.constraints = {
		.name = "PVDD_HI",
		.always_on = 1,
	},
};

/* VDD_PLL, LDO2 on J5 */
static struct regulator_init_data smdk6410_vddpll = {
	.constraints = {
		.name = "PVDD_PLL",
		.always_on = 1,
	},
};

/* VDD_UH_MMC, LDO5 on J5 */
static struct regulator_init_data smdk6410_vdduh_mmc = {
	.constraints = {
		.name = "PVDD_UH/PVDD_MMC",
		.always_on = 1,
	},
};

/* VCCM3BT, LDO8 on J5 */
static struct regulator_init_data smdk6410_vccmc3bt = {
	.constraints = {
		.name = "PVCCM3BT",
		.always_on = 1,
	},
};

/* VCCM2MTV, LDO11 on J5 */
static struct regulator_init_data smdk6410_vccm2mtv = {
	.constraints = {
		.name = "PVCCM2MTV",
		.always_on = 1,
	},
};

/* VDD_LCD, LDO12 on J5 */
static struct regulator_init_data smdk6410_vddlcd = {
	.constraints = {
		.name = "PVDD_LCD",
		.always_on = 1,
	},
};

/* VDD_OTGI, LDO9 on J5 */
static struct regulator_init_data smdk6410_vddotgi = {
	.constraints = {
		.name = "PVDD_OTGI",
		.always_on = 1,
	},
};

/* VDD_OTG, LDO14 on J5 */
static struct regulator_init_data smdk6410_vddotg = {
	.constraints = {
		.name = "PVDD_OTG",
		.always_on = 1,
	},
};

/* VDD_ALIVE, LDO15 on J5 */
static struct regulator_init_data smdk6410_vddalive = {
	.constraints = {
		.name = "PVDD_ALIVE",
		.always_on = 1,
	},
};

/* VDD_AUDIO, VLDO_AUDIO on J5 */
static struct regulator_init_data smdk6410_vddaudio = {
	.constraints = {
		.name = "PVDD_AUDIO",
		.always_on = 1,
	},
};
#endif

#ifdef CONFIG_SMDK6410_WM1190_EV1
/* S3C64xx internal logic & PLL */
static struct regulator_init_data wm8350_dcdc1_data = {
	.constraints = {
		.name = "PVDD_INT/PVDD_PLL",
		.min_uV = 1200000,
		.max_uV = 1200000,
		.always_on = 1,
		.apply_uV = 1,
	},
};

/* Memory */
static struct regulator_init_data wm8350_dcdc3_data = {
	.constraints = {
		.name = "PVDD_MEM",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.always_on = 1,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		},
		.initial_state = PM_SUSPEND_MEM,
	},
};

/* USB, EXT, PCM, ADC/DAC, USB, MMC */
static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
	{
		/* WM8580 */
		.supply = "DVDD",
		.dev_name = "0-001b",
	},
};

static struct regulator_init_data wm8350_dcdc4_data = {
	.constraints = {
		.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
		.min_uV = 3000000,
		.max_uV = 3000000,
		.always_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
	.consumer_supplies = wm8350_dcdc4_consumers,
};

/* OTGi/1190-EV1 HPVDD & AVDD */
static struct regulator_init_data wm8350_ldo4_data = {
	.constraints = {
		.name = "PVDD_OTGI/HPVDD/AVDD",
		.min_uV = 1200000,
		.max_uV = 1200000,
		.apply_uV = 1,
		.always_on = 1,
	},
};

static struct {
	int regulator;
	struct regulator_init_data *initdata;
} wm1190_regulators[] = {
	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
	{ WM8350_DCDC_6, &smdk6410_vddarm },
	{ WM8350_LDO_1, &smdk6410_vddalive },
	{ WM8350_LDO_2, &smdk6410_vddotg },
	{ WM8350_LDO_3, &smdk6410_vddlcd },
	{ WM8350_LDO_4, &wm8350_ldo4_data },
};

static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
{
	int i;

	/* Configure the IRQ line */
	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);

	/* Instantiate the regulators */
	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
		wm8350_register_regulator(wm8350,
					  wm1190_regulators[i].regulator,
					  wm1190_regulators[i].initdata);

	return 0;
}

static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
	.init = smdk6410_wm8350_init,
	.irq_high = 1,
	.irq_base = IRQ_BOARD_START,
};
#endif

#ifdef CONFIG_SMDK6410_WM1192_EV1
static struct gpio_led wm1192_pmic_leds[] = {
	{
		.name = "PMIC:red:power",
		.gpio = GPIO_BOARD_START + 3,
		.default_state = LEDS_GPIO_DEFSTATE_ON,
	},
};

static struct gpio_led_platform_data wm1192_pmic_led = {
	.num_leds = ARRAY_SIZE(wm1192_pmic_leds),
	.leds = wm1192_pmic_leds,
};

static struct platform_device wm1192_pmic_led_dev = {
	.name          = "leds-gpio",
	.id            = -1,
	.dev = {
		.platform_data = &wm1192_pmic_led,
	},
};

static int wm1192_pre_init(struct wm831x *wm831x)
{
	int ret;

	/* Configure the IRQ line */
	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);

	ret = platform_device_register(&wm1192_pmic_led_dev);
	if (ret != 0)
		dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);

	return 0;
}

static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
	.isink = 1,
	.max_uA = 27554,
};

static struct regulator_init_data wm1192_dcdc3 = {
	.constraints = {
		.name = "PVDD_MEM/PVDD_GPS",
		.always_on = 1,
	},
};

static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
	{ .supply = "DVDD", .dev_name = "0-001b", },   /* WM8580 */
};

static struct regulator_init_data wm1192_ldo1 = {
	.constraints = {
		.name = "PVDD_LCD/PVDD_EXT",
		.always_on = 1,
	},
	.consumer_supplies = wm1192_ldo1_consumers,
	.num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
};

static struct wm831x_status_pdata wm1192_led7_pdata = {
	.name = "LED7:green:",
};

static struct wm831x_status_pdata wm1192_led8_pdata = {
	.name = "LED8:green:",
};

static struct wm831x_pdata smdk6410_wm1192_pdata = {
	.pre_init = wm1192_pre_init,
	.irq_base = IRQ_BOARD_START,

	.backlight = &wm1192_backlight_pdata,
	.dcdc = {
		&smdk6410_vddarm,  /* DCDC1 */
		&smdk6410_vddint,  /* DCDC2 */
		&wm1192_dcdc3,
	},
	.gpio_base = GPIO_BOARD_START,
	.ldo = {
		 &wm1192_ldo1,        /* LDO1 */
		 &smdk6410_vdduh_mmc, /* LDO2 */
		 NULL,                /* LDO3 NC */
		 &smdk6410_vddotgi,   /* LDO4 */
		 &smdk6410_vddotg,    /* LDO5 */
		 &smdk6410_vddhi,     /* LDO6 */
		 &smdk6410_vddaudio,  /* LDO7 */
		 &smdk6410_vccm2mtv,  /* LDO8 */
		 &smdk6410_vddpll,    /* LDO9 */
		 &smdk6410_vccmc3bt,  /* LDO10 */
		 &smdk6410_vddalive,  /* LDO11 */
	},
	.status = {
		&wm1192_led7_pdata,
		&wm1192_led8_pdata,
	},
};
#endif

static struct i2c_board_info i2c_devs0[] __initdata = {
	{ I2C_BOARD_INFO("24c08", 0x50), },
	{ I2C_BOARD_INFO("wm8580", 0x1b), },

#ifdef CONFIG_SMDK6410_WM1192_EV1
	{ I2C_BOARD_INFO("wm8312", 0x34),
	  .platform_data = &smdk6410_wm1192_pdata,
	  .irq = S3C_EINT(12),
	},
#endif

#ifdef CONFIG_SMDK6410_WM1190_EV1
	{ I2C_BOARD_INFO("wm8350", 0x1a),
	  .platform_data = &smdk6410_wm8350_pdata,
	  .irq = S3C_EINT(12),
	},
#endif
};

static struct i2c_board_info i2c_devs1[] __initdata = {
	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
};

static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
	.delay			= 10000,
	.presc			= 49,
	.oversampling_shift	= 2,
};

static void __init smdk6410_map_io(void)
{
	u32 tmp;

	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));

	/* set the LCD type */

	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the lcd bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

static void __init smdk6410_machine_init(void)
{
	u32 cs1;

	s3c_i2c0_set_platdata(NULL);
	s3c_i2c1_set_platdata(NULL);
	s3c_fb_set_platdata(&smdk6410_lcd_pdata);

	s3c24xx_ts_set_platdata(&s3c_ts_platform);

	/* configure nCS1 width to 16 bits */

	cs1 = __raw_readl(S3C64XX_SROM_BW) &
		    ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
						   S3C64XX_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S3C64XX_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */

	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
		     (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
		     (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
		     (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
		     (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
		     (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
		     (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);

	gpio_request(S3C64XX_GPN(5), "LCD power");
	gpio_request(S3C64XX_GPF(13), "LCD power");
	gpio_request(S3C64XX_GPF(15), "LCD power");

	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}

MACHINE_START(SMDK6410, "SMDK6410")
	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
	.phys_io	= S3C_PA_UART & 0xfff00000,
	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C64XX_PA_SDRAM + 0x100,

	.init_irq	= s3c6410_init_irq,
	.map_io		= smdk6410_map_io,
	.init_machine	= smdk6410_machine_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
431107ea	1	/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
5718df9d BD	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/types.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/list.h>
	18	#include <linux/timer.h>
	19	#include <linux/init.h>
	20	#include <linux/serial_core.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
096941ed	23	#include <linux/i2c.h>
a7a81d0b	24	#include <linux/leds.h>
438a5d42 BD	25	#include <linux/fb.h>
	26	#include <linux/gpio.h>
	27	#include <linux/delay.h>
3056ea0a	28	#include <linux/smsc911x.h>
42015c13	29	#include <linux/regulator/fixed.h>
438a5d42	30
ecc558ac MB	31	#ifdef CONFIG_SMDK6410_WM1190_EV1
	32	#include <linux/mfd/wm8350/core.h>
	33	#include <linux/mfd/wm8350/pmic.h>
	34	#endif
438a5d42	35
60f9101a	36	#ifdef CONFIG_SMDK6410_WM1192_EV1
a7a81d0b	37	#include <linux/mfd/wm831x/core.h>
60f9101a MB	38	#include <linux/mfd/wm831x/pdata.h>
	39	#endif
	40
438a5d42	41	#include <video/platform_lcd.h>
5718df9d BD	42
	43	#include <asm/mach/arch.h>
	44	#include <asm/mach/map.h>
	45	#include <asm/mach/irq.h>
	46
	47	#include <mach/hardware.h>
438a5d42	48	#include <mach/regs-fb.h>
5718df9d BD	49	#include <mach/map.h>
	50
	51	#include <asm/irq.h>
	52	#include <asm/mach-types.h>
	53
	54	#include <plat/regs-serial.h>
3501c9ae BD	55	#include <mach/regs-modem.h>
	56	#include <mach/regs-gpio.h>
	57	#include <mach/regs-sys.h>
	58	#include <mach/regs-srom.h>
d85fa24c	59	#include <plat/iic.h>
438a5d42	60	#include <plat/fb.h>
3056ea0a	61	#include <plat/gpio-cfg.h>
5718df9d	62
f7be9aba	63	#include <mach/s3c6410.h>
5718df9d BD	64	#include <plat/clock.h>
	65	#include <plat/devs.h>
	66	#include <plat/cpu.h>
85b14a3f NKC	67	#include <plat/adc.h>
85b14a3f NKC	68	#include <plat/ts.h>
5718df9d BD	69
	70	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	71	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	72	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	73
	74	static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
	75	[0] = {
	76	.hwport = 0,
	77	.flags = 0,
bd258e52 MH	78	.ucon = UCON,
	79	.ulcon = ULCON,
	80	.ufcon = UFCON,
5718df9d BD	81	},
	82	[1] = {
	83	.hwport = 1,
	84	.flags = 0,
bd258e52 MH	85	.ucon = UCON,
	86	.ulcon = ULCON,
	87	.ufcon = UFCON,
	88	},
	89	[2] = {
	90	.hwport = 2,
	91	.flags = 0,
	92	.ucon = UCON,
	93	.ulcon = ULCON,
	94	.ufcon = UFCON,
	95	},
	96	[3] = {
	97	.hwport = 3,
	98	.flags = 0,
	99	.ucon = UCON,
	100	.ulcon = ULCON,
	101	.ufcon = UFCON,
5718df9d BD	102	},
	103	};
	104
438a5d42 BD	105	/* framebuffer and LCD setup. */
	106
	107	/* GPF15 = LCD backlight control
	108	* GPF13 => Panel power
	109	* GPN5 = LCD nRESET signal
	110	* PWM_TOUT1 => backlight brightness
	111	*/
	112
	113	static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
	114	unsigned int power)
	115	{
	116	if (power) {
	117	gpio_direction_output(S3C64XX_GPF(13), 1);
	118	gpio_direction_output(S3C64XX_GPF(15), 1);
	119
	120	/* fire nRESET on power up */
	121	gpio_direction_output(S3C64XX_GPN(5), 0);
	122	msleep(10);
	123	gpio_direction_output(S3C64XX_GPN(5), 1);
	124	msleep(1);
	125	} else {
	126	gpio_direction_output(S3C64XX_GPF(15), 0);
	127	gpio_direction_output(S3C64XX_GPF(13), 0);
	128	}
	129	}
	130
	131	static struct plat_lcd_data smdk6410_lcd_power_data = {
	132	.set_power = smdk6410_lcd_power_set,
	133	};
	134
	135	static struct platform_device smdk6410_lcd_powerdev = {
	136	.name = "platform-lcd",
	137	.dev.parent = &s3c_device_fb.dev,
	138	.dev.platform_data = &smdk6410_lcd_power_data,
	139	};
	140
	141	static struct s3c_fb_pd_win smdk6410_fb_win0 = {
	142	/* this is to ensure we use win0 */
	143	.win_mode = {
438a5d42 BD	144	.left_margin = 8,
	145	.right_margin = 13,
	146	.upper_margin = 7,
	147	.lower_margin = 5,
	148	.hsync_len = 3,
	149	.vsync_len = 1,
	150	.xres = 800,
	151	.yres = 480,
	152	},
	153	.max_bpp = 32,
	154	.default_bpp = 16,
	155	};
	156
	157	/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
	158	static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
	159	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
	160	.win[0] = &smdk6410_fb_win0,
	161	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	162	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	163	};
	164
a4e94694 AG	165	/*
	166	* Configuring Ethernet on SMDK6410
	167	*
	168	* Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
	169	* The constant address below corresponds to nCS1
	170	*
	171	* 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
	172	* 2) CFG6 needs to be switched to "LAN9115" side
	173	*/
	174
3056ea0a MB	175	static struct resource smdk6410_smsc911x_resources[] = {
3056ea0a MB	176	[0] = {
f01fdac0 AG	177	.start = S3C64XX_PA_XM0CSN1,
f01fdac0 AG	178	.end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
3056ea0a MB	179	.flags = IORESOURCE_MEM,
	180	},
	181	[1] = {
	182	.start = S3C_EINT(10),
	183	.end = S3C_EINT(10),
	184	.flags = IORESOURCE_IRQ \| IRQ_TYPE_LEVEL_LOW,
	185	},
	186	};
	187
	188	static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
	189	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	190	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	191	.flags = SMSC911X_USE_32BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	192	.phy_interface = PHY_INTERFACE_MODE_MII,
	193	};
	194
	195
	196	static struct platform_device smdk6410_smsc911x = {
	197	.name = "smsc911x",
	198	.id = -1,
	199	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
	200	.resource = &smdk6410_smsc911x_resources[0],
	201	.dev = {
	202	.platform_data = &smdk6410_smsc911x_pdata,
	203	},
	204	};
	205
42015c13 MB	206	#ifdef CONFIG_REGULATOR
	207	static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
	208	{
	209	/* WM8580 */
	210	.supply = "PVDD",
	211	.dev_name = "0-001b",
	212	},
	213	{
	214	/* WM8580 */
	215	.supply = "AVDD",
	216	.dev_name = "0-001b",
	217	},
	218	};
	219
	220	static struct regulator_init_data smdk6410_b_pwr_5v_data = {
	221	.constraints = {
	222	.always_on = 1,
	223	},
	224	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
	225	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
	226	};
	227
	228	static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
	229	.supply_name = "B_PWR_5V",
	230	.microvolts = 5000000,
	231	.init_data = &smdk6410_b_pwr_5v_data,
d3cf4489	232	.gpio = -EINVAL,
42015c13 MB	233	};
	234
	235	static struct platform_device smdk6410_b_pwr_5v = {
	236	.name = "reg-fixed-voltage",
	237	.id = -1,
	238	.dev = {
	239	.platform_data = &smdk6410_b_pwr_5v_pdata,
	240	},
	241	};
	242	#endif
	243
027191a8	244	static struct map_desc smdk6410_iodesc[] = {};
5718df9d BD	245
5718df9d BD	246	static struct platform_device *smdk6410_devices[] __initdata = {
b24636cf	247	#ifdef CONFIG_SMDK6410_SD_CH0
39057f23	248	&s3c_device_hsmmc0,
b24636cf BD	249	#endif
	250	#ifdef CONFIG_SMDK6410_SD_CH1
	251	&s3c_device_hsmmc1,
	252	#endif
d85fa24c	253	&s3c_device_i2c0,
d7ea3743	254	&s3c_device_i2c1,
438a5d42	255	&s3c_device_fb,
b813248c	256	&s3c_device_ohci,
06fa1d37	257	&s3c_device_usb_hsotg,
1f100868	258	&s3c64xx_device_iisv4,
42015c13 MB	259
	260	#ifdef CONFIG_REGULATOR
	261	&smdk6410_b_pwr_5v,
	262	#endif
438a5d42	263	&smdk6410_lcd_powerdev,
3056ea0a MB	264
3056ea0a MB	265	&smdk6410_smsc911x,
85b14a3f NKC	266	&s3c_device_adc,
85b14a3f NKC	267	&s3c_device_ts,
b351c4a1	268	&s3c_device_wdt,
5718df9d BD	269	};
5718df9d BD	270
60f9101a MB	271	#ifdef CONFIG_REGULATOR
	272	/* ARM core */
	273	static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
	274	{
	275	.supply = "vddarm",
	276	}
	277	};
	278
	279	/* VDDARM, BUCK1 on J5 */
	280	static struct regulator_init_data smdk6410_vddarm = {
ecc558ac	281	.constraints = {
60f9101a MB	282	.name = "PVDD_ARM",
	283	.min_uV = 1000000,
	284	.max_uV = 1300000,
	285	.always_on = 1,
	286	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	287	},
	288	.num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
	289	.consumer_supplies = smdk6410_vddarm_consumers,
	290	};
	291
	292	/* VDD_INT, BUCK2 on J5 */
	293	static struct regulator_init_data smdk6410_vddint = {
	294	.constraints = {
	295	.name = "PVDD_INT",
	296	.min_uV = 1000000,
ecc558ac MB	297	.max_uV = 1200000,
ecc558ac MB	298	.always_on = 1,
60f9101a	299	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
ecc558ac MB	300	},
	301	};
	302
60f9101a MB	303	/* VDD_HI, LDO3 on J5 */
60f9101a MB	304	static struct regulator_init_data smdk6410_vddhi = {
ecc558ac	305	.constraints = {
60f9101a	306	.name = "PVDD_HI",
ecc558ac	307	.always_on = 1,
ecc558ac MB	308	},
	309	};
	310
60f9101a MB	311	/* VDD_PLL, LDO2 on J5 */
	312	static struct regulator_init_data smdk6410_vddpll = {
	313	.constraints = {
	314	.name = "PVDD_PLL",
	315	.always_on = 1,
42015c13 MB	316	},
	317	};
	318
60f9101a MB	319	/* VDD_UH_MMC, LDO5 on J5 */
60f9101a MB	320	static struct regulator_init_data smdk6410_vdduh_mmc = {
ecc558ac	321	.constraints = {
60f9101a	322	.name = "PVDD_UH/PVDD_MMC",
ecc558ac MB	323	.always_on = 1,
	324	},
	325	};
	326
60f9101a MB	327	/* VCCM3BT, LDO8 on J5 */
	328	static struct regulator_init_data smdk6410_vccmc3bt = {
	329	.constraints = {
	330	.name = "PVCCM3BT",
	331	.always_on = 1,
	332	},
e3980b6a MB	333	};
e3980b6a MB	334
60f9101a MB	335	/* VCCM2MTV, LDO11 on J5 */
60f9101a MB	336	static struct regulator_init_data smdk6410_vccm2mtv = {
ecc558ac	337	.constraints = {
60f9101a MB	338	.name = "PVCCM2MTV",
	339	.always_on = 1,
	340	},
	341	};
	342
	343	/* VDD_LCD, LDO12 on J5 */
	344	static struct regulator_init_data smdk6410_vddlcd = {
	345	.constraints = {
	346	.name = "PVDD_LCD",
	347	.always_on = 1,
	348	},
	349	};
	350
	351	/* VDD_OTGI, LDO9 on J5 */
	352	static struct regulator_init_data smdk6410_vddotgi = {
	353	.constraints = {
	354	.name = "PVDD_OTGI",
	355	.always_on = 1,
	356	},
	357	};
	358
	359	/* VDD_OTG, LDO14 on J5 */
	360	static struct regulator_init_data smdk6410_vddotg = {
	361	.constraints = {
	362	.name = "PVDD_OTG",
ecc558ac MB	363	.always_on = 1,
ecc558ac MB	364	},
5718df9d BD	365	};
5718df9d BD	366
60f9101a MB	367	/* VDD_ALIVE, LDO15 on J5 */
60f9101a MB	368	static struct regulator_init_data smdk6410_vddalive = {
ecc558ac MB	369	.constraints = {
ecc558ac MB	370	.name = "PVDD_ALIVE",
60f9101a MB	371	.always_on = 1,
	372	},
	373	};
	374
	375	/* VDD_AUDIO, VLDO_AUDIO on J5 */
	376	static struct regulator_init_data smdk6410_vddaudio = {
	377	.constraints = {
	378	.name = "PVDD_AUDIO",
	379	.always_on = 1,
	380	},
	381	};
	382	#endif
	383
	384	#ifdef CONFIG_SMDK6410_WM1190_EV1
	385	/* S3C64xx internal logic & PLL */
	386	static struct regulator_init_data wm8350_dcdc1_data = {
	387	.constraints = {
	388	.name = "PVDD_INT/PVDD_PLL",
ecc558ac MB	389	.min_uV = 1200000,
	390	.max_uV = 1200000,
	391	.always_on = 1,
	392	.apply_uV = 1,
	393	},
	394	};
	395
60f9101a MB	396	/* Memory */
60f9101a MB	397	static struct regulator_init_data wm8350_dcdc3_data = {
ecc558ac	398	.constraints = {
60f9101a MB	399	.name = "PVDD_MEM",
	400	.min_uV = 1800000,
	401	.max_uV = 1800000,
f53aee29	402	.always_on = 1,
60f9101a MB	403	.state_mem = {
	404	.uV = 1800000,
	405	.mode = REGULATOR_MODE_NORMAL,
	406	.enabled = 1,
	407	},
	408	.initial_state = PM_SUSPEND_MEM,
ecc558ac MB	409	},
	410	};
	411
60f9101a MB	412	/* USB, EXT, PCM, ADC/DAC, USB, MMC */
	413	static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
	414	{
	415	/* WM8580 */
	416	.supply = "DVDD",
	417	.dev_name = "0-001b",
	418	},
	419	};
	420
	421	static struct regulator_init_data wm8350_dcdc4_data = {
ecc558ac	422	.constraints = {
60f9101a	423	.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
ecc558ac MB	424	.min_uV = 3000000,
ecc558ac MB	425	.max_uV = 3000000,
f53aee29	426	.always_on = 1,
ecc558ac	427	},
60f9101a MB	428	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
60f9101a MB	429	.consumer_supplies = wm8350_dcdc4_consumers,
ecc558ac MB	430	};
	431
	432	/* OTGi/1190-EV1 HPVDD & AVDD */
	433	static struct regulator_init_data wm8350_ldo4_data = {
	434	.constraints = {
	435	.name = "PVDD_OTGI/HPVDD/AVDD",
	436	.min_uV = 1200000,
	437	.max_uV = 1200000,
	438	.apply_uV = 1,
f53aee29	439	.always_on = 1,
ecc558ac MB	440	},
	441	};
	442
	443	static struct {
	444	int regulator;
	445	struct regulator_init_data *initdata;
	446	} wm1190_regulators[] = {
	447	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
	448	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
	449	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
60f9101a MB	450	{ WM8350_DCDC_6, &smdk6410_vddarm },
	451	{ WM8350_LDO_1, &smdk6410_vddalive },
	452	{ WM8350_LDO_2, &smdk6410_vddotg },
	453	{ WM8350_LDO_3, &smdk6410_vddlcd },
ecc558ac MB	454	{ WM8350_LDO_4, &wm8350_ldo4_data },
	455	};
	456
	457	static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
	458	{
	459	int i;
	460
a3323b72 MB	461	/* Configure the IRQ line */
	462	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
	463
ecc558ac MB	464	/* Instantiate the regulators */
	465	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
	466	wm8350_register_regulator(wm8350,
	467	wm1190_regulators[i].regulator,
	468	wm1190_regulators[i].initdata);
	469
	470	return 0;
	471	}
	472
	473	static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
	474	.init = smdk6410_wm8350_init,
db9256f3	475	.irq_high = 1,
9fca8786	476	.irq_base = IRQ_BOARD_START,
ecc558ac MB	477	};
	478	#endif
	479
60f9101a	480	#ifdef CONFIG_SMDK6410_WM1192_EV1
a7a81d0b MB	481	static struct gpio_led wm1192_pmic_leds[] = {
	482	{
	483	.name = "PMIC:red:power",
	484	.gpio = GPIO_BOARD_START + 3,
	485	.default_state = LEDS_GPIO_DEFSTATE_ON,
	486	},
	487	};
	488
	489	static struct gpio_led_platform_data wm1192_pmic_led = {
	490	.num_leds = ARRAY_SIZE(wm1192_pmic_leds),
	491	.leds = wm1192_pmic_leds,
	492	};
	493
	494	static struct platform_device wm1192_pmic_led_dev = {
	495	.name = "leds-gpio",
	496	.id = -1,
	497	.dev = {
	498	.platform_data = &wm1192_pmic_led,
	499	},
	500	};
	501
60f9101a MB	502	static int wm1192_pre_init(struct wm831x *wm831x)
60f9101a MB	503	{
a7a81d0b MB	504	int ret;
a7a81d0b MB	505
60f9101a MB	506	/* Configure the IRQ line */
	507	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
	508
a7a81d0b MB	509	ret = platform_device_register(&wm1192_pmic_led_dev);
	510	if (ret != 0)
	511	dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
	512
60f9101a MB	513	return 0;
	514	}
	515
	516	static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
	517	.isink = 1,
	518	.max_uA = 27554,
	519	};
	520
	521	static struct regulator_init_data wm1192_dcdc3 = {
	522	.constraints = {
	523	.name = "PVDD_MEM/PVDD_GPS",
	524	.always_on = 1,
	525	},
	526	};
	527
	528	static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
	529	{ .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */
	530	};
	531
	532	static struct regulator_init_data wm1192_ldo1 = {
	533	.constraints = {
	534	.name = "PVDD_LCD/PVDD_EXT",
	535	.always_on = 1,
	536	},
	537	.consumer_supplies = wm1192_ldo1_consumers,
	538	.num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
	539	};
	540
	541	static struct wm831x_status_pdata wm1192_led7_pdata = {
	542	.name = "LED7:green:",
	543	};
	544
	545	static struct wm831x_status_pdata wm1192_led8_pdata = {
	546	.name = "LED8:green:",
	547	};
	548
	549	static struct wm831x_pdata smdk6410_wm1192_pdata = {
	550	.pre_init = wm1192_pre_init,
	551	.irq_base = IRQ_BOARD_START,
	552
	553	.backlight = &wm1192_backlight_pdata,
	554	.dcdc = {
	555	&smdk6410_vddarm, /* DCDC1 */
	556	&smdk6410_vddint, /* DCDC2 */
	557	&wm1192_dcdc3,
	558	},
a7a81d0b	559	.gpio_base = GPIO_BOARD_START,
60f9101a MB	560	.ldo = {
	561	&wm1192_ldo1, /* LDO1 */
	562	&smdk6410_vdduh_mmc, /* LDO2 */
	563	NULL, /* LDO3 NC */
	564	&smdk6410_vddotgi, /* LDO4 */
	565	&smdk6410_vddotg, /* LDO5 */
	566	&smdk6410_vddhi, /* LDO6 */
	567	&smdk6410_vddaudio, /* LDO7 */
	568	&smdk6410_vccm2mtv, /* LDO8 */
	569	&smdk6410_vddpll, /* LDO9 */
	570	&smdk6410_vccmc3bt, /* LDO10 */
	571	&smdk6410_vddalive, /* LDO11 */
	572	},
	573	.status = {
	574	&wm1192_led7_pdata,
	575	&wm1192_led8_pdata,
	576	},
	577	};
	578	#endif
	579
096941ed BD	580	static struct i2c_board_info i2c_devs0[] __initdata = {
096941ed BD	581	{ I2C_BOARD_INFO("24c08", 0x50), },
77897479	582	{ I2C_BOARD_INFO("wm8580", 0x1b), },
ecc558ac	583
60f9101a MB	584	#ifdef CONFIG_SMDK6410_WM1192_EV1
	585	{ I2C_BOARD_INFO("wm8312", 0x34),
	586	.platform_data = &smdk6410_wm1192_pdata,
	587	.irq = S3C_EINT(12),
	588	},
	589	#endif
	590
ecc558ac MB	591	#ifdef CONFIG_SMDK6410_WM1190_EV1
	592	{ I2C_BOARD_INFO("wm8350", 0x1a),
	593	.platform_data = &smdk6410_wm8350_pdata,
	594	.irq = S3C_EINT(12),
	595	},
	596	#endif
096941ed BD	597	};
	598
	599	static struct i2c_board_info i2c_devs1[] __initdata = {
	600	{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
5718df9d BD	601	};
5718df9d BD	602
85b14a3f NKC	603	static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
	604	.delay = 10000,
	605	.presc = 49,
	606	.oversampling_shift = 2,
	607	};
	608
5718df9d BD	609	static void __init smdk6410_map_io(void)
5718df9d BD	610	{
d6662c35 BD	611	u32 tmp;
d6662c35 BD	612
5718df9d BD	613	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
	614	s3c24xx_init_clocks(12000000);
	615	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
d6662c35 BD	616
	617	/* set the LCD type */
	618
	619	tmp = __raw_readl(S3C64XX_SPCON);
	620	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	621	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	622	__raw_writel(tmp, S3C64XX_SPCON);
	623
	624	/* remove the lcd bypass */
	625	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	626	tmp &= ~MIFPCON_LCD_BYPASS;
	627	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
5718df9d BD	628	}
	629
	630	static void __init smdk6410_machine_init(void)
	631	{
f01fdac0 AG	632	u32 cs1;
f01fdac0 AG	633
d85fa24c	634	s3c_i2c0_set_platdata(NULL);
d7ea3743	635	s3c_i2c1_set_platdata(NULL);
438a5d42	636	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
096941ed	637
85b14a3f NKC	638	s3c24xx_ts_set_platdata(&s3c_ts_platform);
85b14a3f NKC	639
f01fdac0 AG	640	/* configure nCS1 width to 16 bits */
	641
	642	cs1 = __raw_readl(S3C64XX_SROM_BW) &
	643	~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	644	cs1 \|= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) \|
	645	(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) \|
	646	(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
	647	S3C64XX_SROM_BW__NCS1__SHIFT;
	648	__raw_writel(cs1, S3C64XX_SROM_BW);
	649
	650	/* set timing for nCS1 suitable for ethernet chip */
	651
	652	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) \|
	653	(6 << S3C64XX_SROM_BCX__TACP__SHIFT) \|
	654	(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) \|
	655	(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) \|
	656	(0xe << S3C64XX_SROM_BCX__TACC__SHIFT) \|
	657	(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) \|
	658	(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
	659
b7f9a94b MB	660	gpio_request(S3C64XX_GPN(5), "LCD power");
	661	gpio_request(S3C64XX_GPF(13), "LCD power");
	662	gpio_request(S3C64XX_GPF(15), "LCD power");
	663
096941ed BD	664	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
	665	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
	666
5718df9d BD	667	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
	668	}
	669
	670	MACHINE_START(SMDK6410, "SMDK6410")
afdd225d	671	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
5718df9d BD	672	.phys_io = S3C_PA_UART & 0xfff00000,
	673	.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
	674	.boot_params = S3C64XX_PA_SDRAM + 0x100,
	675
	676	.init_irq = s3c6410_init_irq,
	677	.map_io = smdk6410_map_io,
	678	.init_machine = smdk6410_machine_init,
	679	.timer = &s3c24xx_timer,
	680	MACHINE_END