[net-next-2.6.git] / arch / arm / mach-s3c2410 / include / mach / regs-s3c2443-clock.h

/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
 *
 * Copyright (c) 2007 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * S3C2443 clock register definitions
*/

#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
#define __ASM_ARM_REGS_S3C2443_CLOCK

#define S3C2443_CLKREG(x)		((x) + S3C24XX_VA_CLKPWR)

#define S3C2443_PLLCON_MDIVSHIFT	16
#define S3C2443_PLLCON_PDIVSHIFT	8
#define S3C2443_PLLCON_SDIVSHIFT	0
#define S3C2443_PLLCON_MDIVMASK		((1<<(1+(23-16)))-1)
#define S3C2443_PLLCON_PDIVMASK		((1<<(1+(9-8)))-1)
#define S3C2443_PLLCON_SDIVMASK		(3)

#define S3C2443_MPLLCON			S3C2443_CLKREG(0x10)
#define S3C2443_EPLLCON			S3C2443_CLKREG(0x18)
#define S3C2443_CLKSRC			S3C2443_CLKREG(0x20)
#define S3C2443_CLKDIV0			S3C2443_CLKREG(0x24)
#define S3C2443_CLKDIV1			S3C2443_CLKREG(0x28)
#define S3C2443_HCLKCON			S3C2443_CLKREG(0x30)
#define S3C2443_PCLKCON			S3C2443_CLKREG(0x34)
#define S3C2443_SCLKCON			S3C2443_CLKREG(0x38)
#define S3C2443_PWRMODE			S3C2443_CLKREG(0x40)
#define S3C2443_SWRST			S3C2443_CLKREG(0x44)
#define S3C2443_BUSPRI0			S3C2443_CLKREG(0x50)
#define S3C2443_SYSID			S3C2443_CLKREG(0x5C)
#define S3C2443_PWRCFG			S3C2443_CLKREG(0x60)
#define S3C2443_RSTCON			S3C2443_CLKREG(0x64)

#define S3C2443_SWRST_RESET		(0x533c2443)

#define S3C2443_PLLCON_OFF		(1<<24)

#define S3C2443_CLKSRC_EPLLREF_XTAL	(2<<7)
#define S3C2443_CLKSRC_EPLLREF_EXTCLK	(3<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF	(0<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF2	(1<<7)
#define S3C2443_CLKSRC_EPLLREF_MASK	(3<<7)

#define S3C2443_CLKSRC_EXTCLK_DIV	(1<<3)

#define S3C2443_CLKDIV0_HALF_HCLK	(1<<3)
#define S3C2443_CLKDIV0_HALF_PCLK	(1<<2)

#define S3C2443_CLKDIV0_HCLKDIV_MASK	(3<<0)

#define S3C2443_CLKDIV0_EXTDIV_MASK	(3<<6)
#define S3C2443_CLKDIV0_EXTDIV_SHIFT	(6)

#define S3C2443_CLKDIV0_PREDIV_MASK	(3<<4)
#define S3C2443_CLKDIV0_PREDIV_SHIFT	(4)

#define S3C2443_CLKDIV0_ARMDIV_MASK	(15<<9)
#define S3C2443_CLKDIV0_ARMDIV_SHIFT	(9)
#define S3C2443_CLKDIV0_ARMDIV_1	(0<<9)
#define S3C2443_CLKDIV0_ARMDIV_2	(8<<9)
#define S3C2443_CLKDIV0_ARMDIV_3	(2<<9)
#define S3C2443_CLKDIV0_ARMDIV_4	(9<<9)
#define S3C2443_CLKDIV0_ARMDIV_6	(10<<9)
#define S3C2443_CLKDIV0_ARMDIV_8	(11<<9)
#define S3C2443_CLKDIV0_ARMDIV_12	(13<<9)
#define S3C2443_CLKDIV0_ARMDIV_16	(15<<9)

/* S3C2443_CLKDIV1 removed, only used in clock.c code */

#define S3C2443_CLKCON_NAND

#define S3C2443_HCLKCON_DMA0		(1<<0)
#define S3C2443_HCLKCON_DMA1		(1<<1)
#define S3C2443_HCLKCON_DMA2		(1<<2)
#define S3C2443_HCLKCON_DMA3		(1<<3)
#define S3C2443_HCLKCON_DMA4		(1<<4)
#define S3C2443_HCLKCON_DMA5		(1<<5)
#define S3C2443_HCLKCON_CAMIF		(1<<8)
#define S3C2443_HCLKCON_LCDC		(1<<9)
#define S3C2443_HCLKCON_USBH		(1<<11)
#define S3C2443_HCLKCON_USBD		(1<<12)
#define S3C2443_HCLKCON_HSMMC		(1<<16)
#define S3C2443_HCLKCON_CFC		(1<<17)
#define S3C2443_HCLKCON_SSMC		(1<<18)
#define S3C2443_HCLKCON_DRAMC		(1<<19)

#define S3C2443_PCLKCON_UART0		(1<<0)
#define S3C2443_PCLKCON_UART1		(1<<1)
#define S3C2443_PCLKCON_UART2		(1<<2)
#define S3C2443_PCLKCON_UART3		(1<<3)
#define S3C2443_PCLKCON_IIC		(1<<4)
#define S3C2443_PCLKCON_SDI		(1<<5)
#define S3C2443_PCLKCON_ADC		(1<<7)
#define S3C2443_PCLKCON_AC97		(1<<8)
#define S3C2443_PCLKCON_IIS		(1<<9)
#define S3C2443_PCLKCON_PWMT		(1<<10)
#define S3C2443_PCLKCON_WDT		(1<<11)
#define S3C2443_PCLKCON_RTC		(1<<12)
#define S3C2443_PCLKCON_GPIO		(1<<13)
#define S3C2443_PCLKCON_SPI0		(1<<14)
#define S3C2443_PCLKCON_SPI1		(1<<15)

#define S3C2443_SCLKCON_DDRCLK		(1<<16)
#define S3C2443_SCLKCON_SSMCCLK		(1<<15)
#define S3C2443_SCLKCON_HSSPICLK	(1<<14)
#define S3C2443_SCLKCON_HSMMCCLK_EXT	(1<<13)
#define S3C2443_SCLKCON_HSMMCCLK_EPLL	(1<<12)
#define S3C2443_SCLKCON_CAMCLK		(1<<11)
#define S3C2443_SCLKCON_DISPCLK		(1<<10)
#define S3C2443_SCLKCON_I2SCLK		(1<<9)
#define S3C2443_SCLKCON_UARTCLK		(1<<8)
#define S3C2443_SCLKCON_USBHOST		(1<<1)

#define S3C2443_PWRCFG_SLEEP		(1<<15)

#include <asm/div64.h>

static inline unsigned int
s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
{
	unsigned int mdiv, pdiv, sdiv;
	uint64_t fvco;

	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;

	mdiv &= S3C2443_PLLCON_MDIVMASK;
	pdiv &= S3C2443_PLLCON_PDIVMASK;
	sdiv &= S3C2443_PLLCON_SDIVMASK;

	fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
	do_div(fvco, pdiv << sdiv);

	return (unsigned int)fvco;
}

static inline unsigned int
s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
{
	unsigned int mdiv, pdiv, sdiv;
	uint64_t fvco;

	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;

	mdiv &= S3C2443_PLLCON_MDIVMASK;
	pdiv &= S3C2443_PLLCON_PDIVMASK;
	sdiv &= S3C2443_PLLCON_SDIVMASK;

	fvco = (uint64_t)baseclk * (mdiv + 8);
	do_div(fvco, (pdiv + 2) << sdiv);

	return (unsigned int)fvco;
}

#endif /*  __ASM_ARM_REGS_S3C2443_CLOCK */
Commit	Line	Data
a09e64fb	1	/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
e9390ef8 BD	2	*
	3	* Copyright (c) 2007 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	* http://armlinux.simtec.co.uk/
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* S3C2443 clock register definitions
	12	*/
	13
	14	#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
	15	#define __ASM_ARM_REGS_S3C2443_CLOCK
	16
	17	#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
	18
	19	#define S3C2443_PLLCON_MDIVSHIFT 16
	20	#define S3C2443_PLLCON_PDIVSHIFT 8
	21	#define S3C2443_PLLCON_SDIVSHIFT 0
	22	#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
	23	#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
	24	#define S3C2443_PLLCON_SDIVMASK (3)
	25
	26	#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
	27	#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
	28	#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
	29	#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
	30	#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
	31	#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
	32	#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
	33	#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
	34	#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
	35	#define S3C2443_SWRST S3C2443_CLKREG(0x44)
	36	#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
	37	#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
	38	#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
	39	#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
	40
b4f14eb8 BD	41	#define S3C2443_SWRST_RESET (0x533c2443)
b4f14eb8 BD	42
e9390ef8 BD	43	#define S3C2443_PLLCON_OFF (1<<24)
e9390ef8 BD	44
78af4735 WS	45	#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
	46	#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
	47	#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
	48	#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
	49	#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
e9390ef8	50
e9390ef8 BD	51	#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
e9390ef8 BD	52
e9390ef8 BD	53	#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
	54	#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
	55
	56	#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
	57
	58	#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
	59	#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
	60
	61	#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
	62	#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
	63
	64	#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
	65	#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
	66	#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
	67	#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
	68	#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
	69	#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
	70	#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
	71	#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
	72	#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
	73	#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
	74
9aa753c4	75	/* S3C2443_CLKDIV1 removed, only used in clock.c code */
e9390ef8 BD	76
	77	#define S3C2443_CLKCON_NAND
	78
	79	#define S3C2443_HCLKCON_DMA0 (1<<0)
	80	#define S3C2443_HCLKCON_DMA1 (1<<1)
	81	#define S3C2443_HCLKCON_DMA2 (1<<2)
	82	#define S3C2443_HCLKCON_DMA3 (1<<3)
	83	#define S3C2443_HCLKCON_DMA4 (1<<4)
	84	#define S3C2443_HCLKCON_DMA5 (1<<5)
	85	#define S3C2443_HCLKCON_CAMIF (1<<8)
dc5d2e82	86	#define S3C2443_HCLKCON_LCDC (1<<9)
e9390ef8 BD	87	#define S3C2443_HCLKCON_USBH (1<<11)
	88	#define S3C2443_HCLKCON_USBD (1<<12)
	89	#define S3C2443_HCLKCON_HSMMC (1<<16)
	90	#define S3C2443_HCLKCON_CFC (1<<17)
	91	#define S3C2443_HCLKCON_SSMC (1<<18)
	92	#define S3C2443_HCLKCON_DRAMC (1<<19)
	93
	94	#define S3C2443_PCLKCON_UART0 (1<<0)
	95	#define S3C2443_PCLKCON_UART1 (1<<1)
	96	#define S3C2443_PCLKCON_UART2 (1<<2)
	97	#define S3C2443_PCLKCON_UART3 (1<<3)
	98	#define S3C2443_PCLKCON_IIC (1<<4)
	99	#define S3C2443_PCLKCON_SDI (1<<5)
	100	#define S3C2443_PCLKCON_ADC (1<<7)
b8b6970b	101	#define S3C2443_PCLKCON_AC97 (1<<8)
e9390ef8 BD	102	#define S3C2443_PCLKCON_IIS (1<<9)
	103	#define S3C2443_PCLKCON_PWMT (1<<10)
	104	#define S3C2443_PCLKCON_WDT (1<<11)
	105	#define S3C2443_PCLKCON_RTC (1<<12)
	106	#define S3C2443_PCLKCON_GPIO (1<<13)
	107	#define S3C2443_PCLKCON_SPI0 (1<<14)
	108	#define S3C2443_PCLKCON_SPI1 (1<<15)
	109
	110	#define S3C2443_SCLKCON_DDRCLK (1<<16)
	111	#define S3C2443_SCLKCON_SSMCCLK (1<<15)
	112	#define S3C2443_SCLKCON_HSSPICLK (1<<14)
	113	#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
	114	#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
	115	#define S3C2443_SCLKCON_CAMCLK (1<<11)
	116	#define S3C2443_SCLKCON_DISPCLK (1<<10)
	117	#define S3C2443_SCLKCON_I2SCLK (1<<9)
	118	#define S3C2443_SCLKCON_UARTCLK (1<<8)
	119	#define S3C2443_SCLKCON_USBHOST (1<<1)
	120
6436b6a7 AK	121	#define S3C2443_PWRCFG_SLEEP (1<<15)
6436b6a7 AK	122
e9390ef8 BD	123	#include <asm/div64.h>
	124
	125	static inline unsigned int
	126	s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
	127	{
	128	unsigned int mdiv, pdiv, sdiv;
	129	uint64_t fvco;
	130
	131	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	132	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	133	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
	134
	135	mdiv &= S3C2443_PLLCON_MDIVMASK;
	136	pdiv &= S3C2443_PLLCON_PDIVMASK;
	137	sdiv &= S3C2443_PLLCON_SDIVMASK;
	138
	139	fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
	140	do_div(fvco, pdiv << sdiv);
	141
	142	return (unsigned int)fvco;
	143	}
	144
	145	static inline unsigned int
	146	s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
	147	{
	148	unsigned int mdiv, pdiv, sdiv;
	149	uint64_t fvco;
	150
	151	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	152	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	153	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
	154
	155	mdiv &= S3C2443_PLLCON_MDIVMASK;
	156	pdiv &= S3C2443_PLLCON_PDIVMASK;
	157	sdiv &= S3C2443_PLLCON_SDIVMASK;
	158
	159	fvco = (uint64_t)baseclk * (mdiv + 8);
	160	do_div(fvco, (pdiv + 2) << sdiv);
	161
	162	return (unsigned int)fvco;
	163	}
	164
	165	#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
	166