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Commit | Line | Data |
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505788cc | 1 | /* linux/arch/arm/mach-s3c2410/dma.c |
1da177e4 | 2 | * |
c16f7bd8 | 3 | * Copyright (c) 2003-2005,2006 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 DMA core | |
7 | * | |
505788cc | 8 | * http://armlinux.simtec.co.uk/ |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
505788cc | 13 | */ |
1da177e4 | 14 | |
1da177e4 LT |
15 | |
16 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
17 | #define DEBUG | |
18 | #endif | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/delay.h> | |
29 | ||
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hardware.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/dma.h> | |
35 | ||
36 | #include <asm/mach/dma.h> | |
37 | #include <asm/arch/map.h> | |
38 | ||
505788cc BD |
39 | #include "dma.h" |
40 | ||
1da177e4 LT |
41 | /* io map for dma */ |
42 | static void __iomem *dma_base; | |
e18b890b | 43 | static struct kmem_cache *dma_kmem; |
1da177e4 | 44 | |
505788cc BD |
45 | struct s3c24xx_dma_selection dma_sel; |
46 | ||
1da177e4 | 47 | /* dma channel state information */ |
f105a7df | 48 | struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; |
1da177e4 LT |
49 | |
50 | /* debugging functions */ | |
51 | ||
52 | #define BUF_MAGIC (0xcafebabe) | |
53 | ||
54 | #define dmawarn(fmt...) printk(KERN_DEBUG fmt) | |
55 | ||
56 | #define dma_regaddr(chan, reg) ((chan)->regs + (reg)) | |
57 | ||
58 | #if 1 | |
59 | #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) | |
60 | #else | |
61 | static inline void | |
f105a7df | 62 | dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) |
1da177e4 LT |
63 | { |
64 | pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); | |
65 | writel(val, dma_regaddr(chan, reg)); | |
66 | } | |
1da177e4 LT |
67 | #endif |
68 | ||
69 | #define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) | |
70 | ||
71 | /* captured register state for debug */ | |
72 | ||
73 | struct s3c2410_dma_regstate { | |
74 | unsigned long dcsrc; | |
75 | unsigned long disrc; | |
76 | unsigned long dstat; | |
77 | unsigned long dcon; | |
78 | unsigned long dmsktrig; | |
79 | }; | |
80 | ||
81 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
82 | ||
83 | /* dmadbg_showregs | |
84 | * | |
85 | * simple debug routine to print the current state of the dma registers | |
86 | */ | |
87 | ||
88 | static void | |
f105a7df | 89 | dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) |
1da177e4 LT |
90 | { |
91 | regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); | |
92 | regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); | |
93 | regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); | |
94 | regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); | |
95 | regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
96 | } | |
97 | ||
98 | static void | |
f105a7df | 99 | dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, |
1da177e4 LT |
100 | struct s3c2410_dma_regstate *regs) |
101 | { | |
102 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", | |
103 | chan->number, fname, line, | |
104 | regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig, | |
105 | regs->dcon); | |
106 | } | |
107 | ||
108 | static void | |
f105a7df | 109 | dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) |
1da177e4 LT |
110 | { |
111 | struct s3c2410_dma_regstate state; | |
112 | ||
113 | dmadbg_capture(chan, &state); | |
114 | ||
115 | printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n", | |
116 | chan->number, fname, line, chan->load_state, | |
117 | chan->curr, chan->next, chan->end); | |
118 | ||
f57e1abd BD |
119 | dmadbg_dumpregs(fname, line, chan, &state); |
120 | } | |
121 | ||
122 | static void | |
f105a7df | 123 | dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) |
f57e1abd BD |
124 | { |
125 | struct s3c2410_dma_regstate state; | |
126 | ||
127 | dmadbg_capture(chan, &state); | |
128 | dmadbg_dumpregs(fname, line, chan, &state); | |
1da177e4 LT |
129 | } |
130 | ||
131 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) | |
132 | #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan)) | |
133 | #else | |
134 | #define dbg_showregs(chan) do { } while(0) | |
135 | #define dbg_showchan(chan) do { } while(0) | |
136 | #endif /* CONFIG_S3C2410_DMA_DEBUG */ | |
137 | ||
505788cc | 138 | static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; |
1da177e4 | 139 | |
505788cc BD |
140 | /* lookup_dma_channel |
141 | * | |
142 | * change the dma channel number given into a real dma channel id | |
143 | */ | |
144 | ||
145 | static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) | |
146 | { | |
147 | if (channel & DMACH_LOW_LEVEL) | |
148 | return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; | |
149 | else | |
150 | return dma_chan_map[channel]; | |
151 | } | |
1da177e4 LT |
152 | |
153 | /* s3c2410_dma_stats_timeout | |
154 | * | |
155 | * Update DMA stats from timeout info | |
156 | */ | |
157 | ||
158 | static void | |
f105a7df | 159 | s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) |
1da177e4 LT |
160 | { |
161 | if (stats == NULL) | |
162 | return; | |
163 | ||
164 | if (val > stats->timeout_longest) | |
165 | stats->timeout_longest = val; | |
166 | if (val < stats->timeout_shortest) | |
167 | stats->timeout_shortest = val; | |
168 | ||
169 | stats->timeout_avg += val; | |
170 | } | |
171 | ||
172 | /* s3c2410_dma_waitforload | |
173 | * | |
174 | * wait for the DMA engine to load a buffer, and update the state accordingly | |
175 | */ | |
176 | ||
177 | static int | |
f105a7df | 178 | s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) |
1da177e4 LT |
179 | { |
180 | int timeout = chan->load_timeout; | |
181 | int took; | |
182 | ||
183 | if (chan->load_state != S3C2410_DMALOAD_1LOADED) { | |
184 | printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line); | |
185 | return 0; | |
186 | } | |
187 | ||
188 | if (chan->stats != NULL) | |
189 | chan->stats->loads++; | |
190 | ||
191 | while (--timeout > 0) { | |
192 | if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { | |
193 | took = chan->load_timeout - timeout; | |
194 | ||
195 | s3c2410_dma_stats_timeout(chan->stats, took); | |
196 | ||
197 | switch (chan->load_state) { | |
198 | case S3C2410_DMALOAD_1LOADED: | |
199 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
200 | break; | |
201 | ||
202 | default: | |
203 | printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state); | |
204 | } | |
205 | ||
206 | return 1; | |
207 | } | |
208 | } | |
209 | ||
210 | if (chan->stats != NULL) { | |
211 | chan->stats->timeout_failed++; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | ||
218 | ||
219 | /* s3c2410_dma_loadbuffer | |
220 | * | |
221 | * load a buffer, and update the channel state | |
222 | */ | |
223 | ||
224 | static inline int | |
f105a7df BD |
225 | s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, |
226 | struct s3c2410_dma_buf *buf) | |
1da177e4 LT |
227 | { |
228 | unsigned long reload; | |
229 | ||
230 | pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n", | |
231 | buf, (unsigned long)buf->data, buf->size); | |
232 | ||
233 | if (buf == NULL) { | |
234 | dmawarn("buffer is NULL\n"); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | /* check the state of the channel before we do anything */ | |
239 | ||
240 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
241 | dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); | |
242 | } | |
243 | ||
244 | if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) { | |
245 | dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); | |
246 | } | |
247 | ||
248 | /* it would seem sensible if we are the last buffer to not bother | |
249 | * with the auto-reload bit, so that the DMA engine will not try | |
250 | * and load another transfer after this one has finished... | |
251 | */ | |
252 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
253 | pr_debug("load_state is none, checking for noreload (next=%p)\n", | |
254 | buf->next); | |
255 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; | |
256 | } else { | |
f57e1abd | 257 | //pr_debug("load_state is %d => autoreload\n", chan->load_state); |
1da177e4 LT |
258 | reload = S3C2410_DCON_AUTORELOAD; |
259 | } | |
260 | ||
f57e1abd BD |
261 | if ((buf->data & 0xf0000000) != 0x30000000) { |
262 | dmawarn("dmaload: buffer is %p\n", (void *)buf->data); | |
263 | } | |
264 | ||
1da177e4 LT |
265 | writel(buf->data, chan->addr_reg); |
266 | ||
267 | dma_wrreg(chan, S3C2410_DMA_DCON, | |
268 | chan->dcon | reload | (buf->size/chan->xfer_unit)); | |
269 | ||
270 | chan->next = buf->next; | |
271 | ||
272 | /* update the state of the channel */ | |
273 | ||
274 | switch (chan->load_state) { | |
275 | case S3C2410_DMALOAD_NONE: | |
276 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
277 | break; | |
278 | ||
279 | case S3C2410_DMALOAD_1RUNNING: | |
280 | chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING; | |
281 | break; | |
282 | ||
283 | default: | |
284 | dmawarn("dmaload: unknown state %d in loadbuffer\n", | |
285 | chan->load_state); | |
286 | break; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /* s3c2410_dma_call_op | |
293 | * | |
294 | * small routine to call the op routine with the given op if it has been | |
295 | * registered | |
296 | */ | |
297 | ||
298 | static void | |
f105a7df | 299 | s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) |
1da177e4 LT |
300 | { |
301 | if (chan->op_fn != NULL) { | |
302 | (chan->op_fn)(chan, op); | |
303 | } | |
304 | } | |
305 | ||
306 | /* s3c2410_dma_buffdone | |
307 | * | |
308 | * small wrapper to check if callback routine needs to be called, and | |
309 | * if so, call it | |
310 | */ | |
311 | ||
312 | static inline void | |
f105a7df BD |
313 | s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, |
314 | enum s3c2410_dma_buffresult result) | |
1da177e4 | 315 | { |
505788cc | 316 | #if 0 |
1da177e4 LT |
317 | pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", |
318 | chan->callback_fn, buf, buf->id, buf->size, result); | |
505788cc | 319 | #endif |
1da177e4 LT |
320 | |
321 | if (chan->callback_fn != NULL) { | |
322 | (chan->callback_fn)(chan, buf->id, buf->size, result); | |
323 | } | |
324 | } | |
325 | ||
326 | /* s3c2410_dma_start | |
327 | * | |
328 | * start a dma channel going | |
329 | */ | |
330 | ||
f105a7df | 331 | static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) |
1da177e4 LT |
332 | { |
333 | unsigned long tmp; | |
334 | unsigned long flags; | |
335 | ||
336 | pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); | |
337 | ||
338 | local_irq_save(flags); | |
339 | ||
340 | if (chan->state == S3C2410_DMA_RUNNING) { | |
341 | pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); | |
342 | local_irq_restore(flags); | |
343 | return 0; | |
344 | } | |
345 | ||
346 | chan->state = S3C2410_DMA_RUNNING; | |
347 | ||
348 | /* check wether there is anything to load, and if not, see | |
349 | * if we can find anything to load | |
350 | */ | |
351 | ||
352 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
353 | if (chan->next == NULL) { | |
354 | printk(KERN_ERR "dma%d: channel has nothing loaded\n", | |
355 | chan->number); | |
356 | chan->state = S3C2410_DMA_IDLE; | |
357 | local_irq_restore(flags); | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | s3c2410_dma_loadbuffer(chan, chan->next); | |
362 | } | |
363 | ||
364 | dbg_showchan(chan); | |
365 | ||
366 | /* enable the channel */ | |
367 | ||
368 | if (!chan->irq_enabled) { | |
369 | enable_irq(chan->irq); | |
370 | chan->irq_enabled = 1; | |
371 | } | |
372 | ||
373 | /* start the channel going */ | |
374 | ||
375 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
376 | tmp &= ~S3C2410_DMASKTRIG_STOP; | |
377 | tmp |= S3C2410_DMASKTRIG_ON; | |
378 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | |
379 | ||
f57e1abd | 380 | pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); |
1da177e4 LT |
381 | |
382 | #if 0 | |
383 | /* the dma buffer loads should take care of clearing the AUTO | |
384 | * reloading feature */ | |
385 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
386 | tmp &= ~S3C2410_DCON_NORELOAD; | |
387 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
388 | #endif | |
389 | ||
390 | s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); | |
391 | ||
392 | dbg_showchan(chan); | |
393 | ||
f57e1abd BD |
394 | /* if we've only loaded one buffer onto the channel, then chec |
395 | * to see if we have another, and if so, try and load it so when | |
396 | * the first buffer is finished, the new one will be loaded onto | |
397 | * the channel */ | |
398 | ||
399 | if (chan->next != NULL) { | |
400 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
401 | ||
402 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
403 | pr_debug("%s: buff not yet loaded, no more todo\n", | |
404 | __FUNCTION__); | |
405 | } else { | |
406 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
407 | s3c2410_dma_loadbuffer(chan, chan->next); | |
408 | } | |
409 | ||
410 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | |
411 | s3c2410_dma_loadbuffer(chan, chan->next); | |
412 | } | |
413 | } | |
414 | ||
415 | ||
1da177e4 | 416 | local_irq_restore(flags); |
f57e1abd | 417 | |
1da177e4 LT |
418 | return 0; |
419 | } | |
420 | ||
421 | /* s3c2410_dma_canload | |
422 | * | |
423 | * work out if we can queue another buffer into the DMA engine | |
424 | */ | |
425 | ||
426 | static int | |
f105a7df | 427 | s3c2410_dma_canload(struct s3c2410_dma_chan *chan) |
1da177e4 LT |
428 | { |
429 | if (chan->load_state == S3C2410_DMALOAD_NONE || | |
430 | chan->load_state == S3C2410_DMALOAD_1RUNNING) | |
431 | return 1; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
1da177e4 LT |
436 | /* s3c2410_dma_enqueue |
437 | * | |
438 | * queue an given buffer for dma transfer. | |
439 | * | |
440 | * id the device driver's id information for this buffer | |
441 | * data the physical address of the buffer data | |
442 | * size the size of the buffer in bytes | |
443 | * | |
444 | * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART | |
445 | * is checked, and if set, the channel is started. If this flag isn't set, | |
446 | * then an error will be returned. | |
447 | * | |
448 | * It is possible to queue more than one DMA buffer onto a channel at | |
449 | * once, and the code will deal with the re-loading of the next buffer | |
450 | * when necessary. | |
451 | */ | |
452 | ||
453 | int s3c2410_dma_enqueue(unsigned int channel, void *id, | |
454 | dma_addr_t data, int size) | |
455 | { | |
505788cc | 456 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); |
f105a7df | 457 | struct s3c2410_dma_buf *buf; |
1da177e4 LT |
458 | unsigned long flags; |
459 | ||
505788cc BD |
460 | if (chan == NULL) |
461 | return -EINVAL; | |
1da177e4 LT |
462 | |
463 | pr_debug("%s: id=%p, data=%08x, size=%d\n", | |
464 | __FUNCTION__, id, (unsigned int)data, size); | |
465 | ||
466 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); | |
467 | if (buf == NULL) { | |
53776eb4 | 468 | pr_debug("%s: out of memory (%ld alloc)\n", |
f57e1abd | 469 | __FUNCTION__, (long)sizeof(*buf)); |
1da177e4 LT |
470 | return -ENOMEM; |
471 | } | |
472 | ||
f57e1abd | 473 | //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); |
1da177e4 LT |
474 | //dbg_showchan(chan); |
475 | ||
476 | buf->next = NULL; | |
477 | buf->data = buf->ptr = data; | |
478 | buf->size = size; | |
479 | buf->id = id; | |
480 | buf->magic = BUF_MAGIC; | |
481 | ||
482 | local_irq_save(flags); | |
483 | ||
484 | if (chan->curr == NULL) { | |
485 | /* we've got nothing loaded... */ | |
486 | pr_debug("%s: buffer %p queued onto empty channel\n", | |
487 | __FUNCTION__, buf); | |
488 | ||
489 | chan->curr = buf; | |
490 | chan->end = buf; | |
491 | chan->next = NULL; | |
492 | } else { | |
493 | pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", | |
494 | chan->number, __FUNCTION__, buf); | |
495 | ||
496 | if (chan->end == NULL) | |
497 | pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", | |
498 | chan->number, __FUNCTION__, chan); | |
499 | ||
500 | chan->end->next = buf; | |
501 | chan->end = buf; | |
502 | } | |
503 | ||
504 | /* if necessary, update the next buffer field */ | |
505 | if (chan->next == NULL) | |
506 | chan->next = buf; | |
507 | ||
508 | /* check to see if we can load a buffer */ | |
509 | if (chan->state == S3C2410_DMA_RUNNING) { | |
510 | if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { | |
511 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
512 | printk(KERN_ERR "dma%d: loadbuffer:" | |
513 | "timeout loading buffer\n", | |
514 | chan->number); | |
515 | dbg_showchan(chan); | |
516 | local_irq_restore(flags); | |
517 | return -EINVAL; | |
518 | } | |
519 | } | |
520 | ||
521 | while (s3c2410_dma_canload(chan) && chan->next != NULL) { | |
522 | s3c2410_dma_loadbuffer(chan, chan->next); | |
523 | } | |
524 | } else if (chan->state == S3C2410_DMA_IDLE) { | |
525 | if (chan->flags & S3C2410_DMAF_AUTOSTART) { | |
526 | s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START); | |
527 | } | |
528 | } | |
529 | ||
530 | local_irq_restore(flags); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | |
535 | ||
536 | static inline void | |
f105a7df | 537 | s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) |
1da177e4 LT |
538 | { |
539 | int magicok = (buf->magic == BUF_MAGIC); | |
540 | ||
541 | buf->magic = -1; | |
542 | ||
543 | if (magicok) { | |
544 | kmem_cache_free(dma_kmem, buf); | |
545 | } else { | |
546 | printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf); | |
547 | } | |
548 | } | |
549 | ||
550 | /* s3c2410_dma_lastxfer | |
551 | * | |
552 | * called when the system is out of buffers, to ensure that the channel | |
553 | * is prepared for shutdown. | |
554 | */ | |
555 | ||
556 | static inline void | |
f105a7df | 557 | s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) |
1da177e4 | 558 | { |
505788cc | 559 | #if 0 |
1da177e4 LT |
560 | pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", |
561 | chan->number, chan->load_state); | |
505788cc | 562 | #endif |
1da177e4 LT |
563 | |
564 | switch (chan->load_state) { | |
565 | case S3C2410_DMALOAD_NONE: | |
566 | break; | |
567 | ||
568 | case S3C2410_DMALOAD_1LOADED: | |
569 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
570 | /* flag error? */ | |
f57e1abd BD |
571 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
572 | chan->number, __FUNCTION__); | |
1da177e4 LT |
573 | return; |
574 | } | |
575 | break; | |
576 | ||
f57e1abd BD |
577 | case S3C2410_DMALOAD_1LOADED_1RUNNING: |
578 | /* I belive in this case we do not have anything to do | |
579 | * until the next buffer comes along, and we turn off the | |
580 | * reload */ | |
581 | return; | |
582 | ||
1da177e4 | 583 | default: |
f57e1abd | 584 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", |
1da177e4 LT |
585 | chan->number, chan->load_state); |
586 | return; | |
587 | ||
588 | } | |
589 | ||
590 | /* hopefully this'll shut the damned thing up after the transfer... */ | |
591 | dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); | |
592 | } | |
593 | ||
594 | ||
595 | #define dmadbg2(x...) | |
596 | ||
597 | static irqreturn_t | |
0cd61b68 | 598 | s3c2410_dma_irq(int irq, void *devpw) |
1da177e4 | 599 | { |
f105a7df BD |
600 | struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; |
601 | struct s3c2410_dma_buf *buf; | |
1da177e4 LT |
602 | |
603 | buf = chan->curr; | |
604 | ||
605 | dbg_showchan(chan); | |
606 | ||
607 | /* modify the channel state */ | |
608 | ||
609 | switch (chan->load_state) { | |
610 | case S3C2410_DMALOAD_1RUNNING: | |
611 | /* TODO - if we are running only one buffer, we probably | |
612 | * want to reload here, and then worry about the buffer | |
613 | * callback */ | |
614 | ||
615 | chan->load_state = S3C2410_DMALOAD_NONE; | |
616 | break; | |
617 | ||
618 | case S3C2410_DMALOAD_1LOADED: | |
619 | /* iirc, we should go back to NONE loaded here, we | |
620 | * had a buffer, and it was never verified as being | |
621 | * loaded. | |
622 | */ | |
623 | ||
624 | chan->load_state = S3C2410_DMALOAD_NONE; | |
625 | break; | |
626 | ||
627 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
628 | /* we'll worry about checking to see if another buffer is | |
629 | * ready after we've called back the owner. This should | |
630 | * ensure we do not wait around too long for the DMA | |
631 | * engine to start the next transfer | |
632 | */ | |
633 | ||
634 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
635 | break; | |
636 | ||
637 | case S3C2410_DMALOAD_NONE: | |
638 | printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", | |
639 | chan->number); | |
640 | break; | |
641 | ||
642 | default: | |
643 | printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", | |
644 | chan->number, chan->load_state); | |
645 | break; | |
646 | } | |
647 | ||
648 | if (buf != NULL) { | |
649 | /* update the chain to make sure that if we load any more | |
650 | * buffers when we call the callback function, things should | |
651 | * work properly */ | |
652 | ||
653 | chan->curr = buf->next; | |
654 | buf->next = NULL; | |
655 | ||
656 | if (buf->magic != BUF_MAGIC) { | |
657 | printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", | |
658 | chan->number, __FUNCTION__, buf); | |
659 | return IRQ_HANDLED; | |
660 | } | |
661 | ||
662 | s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); | |
663 | ||
664 | /* free resouces */ | |
665 | s3c2410_dma_freebuf(buf); | |
666 | } else { | |
667 | } | |
668 | ||
f57e1abd BD |
669 | /* only reload if the channel is still running... our buffer done |
670 | * routine may have altered the state by requesting the dma channel | |
671 | * to stop or shutdown... */ | |
672 | ||
673 | /* todo: check that when the channel is shut-down from inside this | |
674 | * function, we cope with unsetting reload, etc */ | |
675 | ||
676 | if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { | |
1da177e4 LT |
677 | unsigned long flags; |
678 | ||
679 | switch (chan->load_state) { | |
680 | case S3C2410_DMALOAD_1RUNNING: | |
681 | /* don't need to do anything for this state */ | |
682 | break; | |
683 | ||
684 | case S3C2410_DMALOAD_NONE: | |
685 | /* can load buffer immediately */ | |
686 | break; | |
687 | ||
688 | case S3C2410_DMALOAD_1LOADED: | |
689 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
690 | /* flag error? */ | |
f57e1abd BD |
691 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
692 | chan->number, __FUNCTION__); | |
1da177e4 LT |
693 | return IRQ_HANDLED; |
694 | } | |
695 | ||
696 | break; | |
697 | ||
698 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
699 | goto no_load; | |
700 | ||
701 | default: | |
702 | printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", | |
703 | chan->number, chan->load_state); | |
704 | return IRQ_HANDLED; | |
705 | } | |
706 | ||
707 | local_irq_save(flags); | |
708 | s3c2410_dma_loadbuffer(chan, chan->next); | |
709 | local_irq_restore(flags); | |
710 | } else { | |
711 | s3c2410_dma_lastxfer(chan); | |
712 | ||
713 | /* see if we can stop this channel.. */ | |
714 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
715 | pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", | |
716 | chan->number, jiffies); | |
505788cc BD |
717 | s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, |
718 | S3C2410_DMAOP_STOP); | |
1da177e4 LT |
719 | } |
720 | } | |
721 | ||
722 | no_load: | |
723 | return IRQ_HANDLED; | |
724 | } | |
725 | ||
505788cc BD |
726 | static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); |
727 | ||
1da177e4 LT |
728 | /* s3c2410_request_dma |
729 | * | |
730 | * get control of an dma channel | |
731 | */ | |
732 | ||
505788cc BD |
733 | int s3c2410_dma_request(unsigned int channel, |
734 | struct s3c2410_dma_client *client, | |
1da177e4 LT |
735 | void *dev) |
736 | { | |
505788cc | 737 | struct s3c2410_dma_chan *chan; |
1da177e4 LT |
738 | unsigned long flags; |
739 | int err; | |
740 | ||
741 | pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", | |
742 | channel, client->name, dev); | |
743 | ||
1da177e4 LT |
744 | local_irq_save(flags); |
745 | ||
505788cc BD |
746 | chan = s3c2410_dma_map_channel(channel); |
747 | if (chan == NULL) { | |
748 | local_irq_restore(flags); | |
749 | return -EBUSY; | |
1da177e4 LT |
750 | } |
751 | ||
505788cc BD |
752 | dbg_showchan(chan); |
753 | ||
1da177e4 LT |
754 | chan->client = client; |
755 | chan->in_use = 1; | |
756 | ||
757 | if (!chan->irq_claimed) { | |
758 | pr_debug("dma%d: %s : requesting irq %d\n", | |
759 | channel, __FUNCTION__, chan->irq); | |
760 | ||
f57e1abd BD |
761 | chan->irq_claimed = 1; |
762 | local_irq_restore(flags); | |
763 | ||
52e405ea | 764 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, |
1da177e4 LT |
765 | client->name, (void *)chan); |
766 | ||
f57e1abd BD |
767 | local_irq_save(flags); |
768 | ||
1da177e4 LT |
769 | if (err) { |
770 | chan->in_use = 0; | |
f57e1abd | 771 | chan->irq_claimed = 0; |
1da177e4 LT |
772 | local_irq_restore(flags); |
773 | ||
774 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", | |
775 | client->name, chan->irq, chan->number); | |
776 | return err; | |
777 | } | |
778 | ||
1da177e4 LT |
779 | chan->irq_enabled = 1; |
780 | } | |
781 | ||
782 | local_irq_restore(flags); | |
783 | ||
784 | /* need to setup */ | |
785 | ||
786 | pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | EXPORT_SYMBOL(s3c2410_dma_request); | |
792 | ||
793 | /* s3c2410_dma_free | |
794 | * | |
795 | * release the given channel back to the system, will stop and flush | |
796 | * any outstanding transfers, and ensure the channel is ready for the | |
797 | * next claimant. | |
798 | * | |
799 | * Note, although a warning is currently printed if the freeing client | |
800 | * info is not the same as the registrant's client info, the free is still | |
801 | * allowed to go through. | |
802 | */ | |
803 | ||
f105a7df | 804 | int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) |
1da177e4 | 805 | { |
505788cc | 806 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); |
1da177e4 LT |
807 | unsigned long flags; |
808 | ||
505788cc BD |
809 | if (chan == NULL) |
810 | return -EINVAL; | |
1da177e4 LT |
811 | |
812 | local_irq_save(flags); | |
813 | ||
1da177e4 LT |
814 | if (chan->client != client) { |
815 | printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", | |
816 | channel, chan->client, client); | |
817 | } | |
818 | ||
819 | /* sort out stopping and freeing the channel */ | |
820 | ||
821 | if (chan->state != S3C2410_DMA_IDLE) { | |
822 | pr_debug("%s: need to stop dma channel %p\n", | |
823 | __FUNCTION__, chan); | |
824 | ||
825 | /* possibly flush the channel */ | |
826 | s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); | |
827 | } | |
828 | ||
829 | chan->client = NULL; | |
830 | chan->in_use = 0; | |
831 | ||