git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| ee8c9571 CM |
1 | /* |
| 2 | * arch/arm/mach-realview/include/mach/irqs-pba8.h | |
| 3 | * | |
| 4 | * Copyright (C) 2008 ARM Limited | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 18 | * MA 02110-1301, USA. | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef __MACH_IRQS_PBA8_H | |
| 22 | #define __MACH_IRQS_PBA8_H | |
| 23 | ||
| 24 | #define IRQ_PBA8_GIC_START 32 | |
| 25 | ||
| ee8c9571 CM |
26 | /* |
| 27 | * PB-A8 on-board gic irq sources | |
| 28 | */ | |
| 29 | #define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ | |
| 30 | #define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ | |
| 31 | #define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */ | |
| 32 | #define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */ | |
| 33 | #define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */ | |
| 34 | #define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */ | |
| 35 | #define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */ | |
| 36 | #define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */ | |
| 37 | #define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */ | |
| 38 | /* 9 reserved */ | |
| 39 | #define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */ | |
| 40 | #define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ | |
| 41 | #define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */ | |
| 42 | #define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */ | |
| 43 | #define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */ | |
| 44 | #define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */ | |
| 45 | #define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ | |
| 46 | #define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ | |
| 47 | #define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ | |
| 48 | #define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ | |
| 49 | #define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ | |
| 50 | #define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ | |
| 51 | #define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ | |
| 52 | #define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ | |
| 53 | #define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ | |
| 54 | #define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ | |
| 55 | #define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ | |
| 56 | #define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ | |
| 57 | #define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ | |
| 58 | #define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ | |
| 59 | #define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ | |
| 60 | #define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ | |
| 61 | ||
| 3081e43b WD |
62 | #define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ |
| 63 | ||
| ee8c9571 CM |
64 | /* ... */ |
| 65 | #define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) | |
| 66 | #define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) | |
| 67 | #define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) | |
| 68 | #define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) | |
| 69 | ||
| 70 | #define IRQ_PBA8_SMC -1 | |
| 71 | #define IRQ_PBA8_SCTL -1 | |
| 72 | ||
| 73 | #define NR_GIC_PBA8 1 | |
| 74 | ||
| 75 | /* | |
| 76 | * Only define NR_IRQS if less than NR_IRQS_PBA8 | |
| 77 | */ | |
| 78 | #define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) | |
| 79 | ||
| 80 | #if defined(CONFIG_MACH_REALVIEW_PBA8) | |
| 81 | ||
| 82 | #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8) | |
| 83 | #undef NR_IRQS | |
| 84 | #define NR_IRQS NR_IRQS_PBA8 | |
| 85 | #endif | |
| 86 | ||
| 87 | #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8) | |
| 88 | #undef MAX_GIC_NR | |
| 89 | #define MAX_GIC_NR NR_GIC_PBA8 | |
| 90 | #endif | |
| 91 | ||
| 92 | #endif /* CONFIG_MACH_REALVIEW_PBA8 */ | |
| 93 | ||
| 94 | #endif /* __MACH_IRQS_PBA8_H */ |