[net-next-2.6.git] / arch / arm / mach-omap2 / opp2xxx.h

/*
 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
 *
 * Copyright (C) 2005-2009 Texas Instruments, Inc.
 * Copyright (C) 2004-2009 Nokia Corporation
 *
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
 * These configurations are characterized by voltage and speed for clocks.
 * The device is only validated for certain combinations. One way to express
 * these combinations is via the 'ratio's' which the clocks operate with
 * respect to each other. These ratio sets are for a given voltage/DPLL
 * setting. All configurations can be described by a DPLL setting and a ratio
 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
 *
 * 2430 differs from 2420 in that there are no more phase synchronizers used.
 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
 * 2430 (iva2.1, NOdsp, mdm)
 *
 * XXX Missing voltage data.
 *
 * THe format described in this file is deprecated.  Once a reasonable
 * OPP API exists, the data in this file should be converted to use it.
 *
 * This is technically part of the OMAP2xxx clock code.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H

/**
 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
 *
 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 *
 * This is deprecated.  As soon as we have a decent OPP API, we should
 * move all this stuff to it.
 */
struct prcm_config {
	unsigned long xtal_speed;	/* crystal rate */
	unsigned long dpll_speed;	/* dpll: out*xtal*M/(N-1)table_recalc */
	unsigned long mpu_speed;	/* speed of MPU */
	unsigned long cm_clksel_mpu;	/* mpu divider */
	unsigned long cm_clksel_dsp;	/* dsp+iva1 div(2420), iva2.1(2430) */
	unsigned long cm_clksel_gfx;	/* gfx dividers */
	unsigned long cm_clksel1_core;	/* major subsystem dividers */
	unsigned long cm_clksel1_pll;	/* m,n */
	unsigned long cm_clksel2_pll;	/* dpllx1 or x2 out */
	unsigned long cm_clksel_mdm;	/* modem dividers 2430 only */
	unsigned long base_sdrc_rfr;	/* base refresh timing for a set */
	unsigned char flags;
};


/* Core fields for cm_clksel, not ratio governed */
#define RX_CLKSEL_DSS1			(0x10 << 8)
#define RX_CLKSEL_DSS2			(0x0 << 13)
#define RX_CLKSEL_SSI			(0x5 << 20)

/*-------------------------------------------------------------------------
 * Voltage/DPLL ratios
 *-------------------------------------------------------------------------*/

/* 2430 Ratio's, 2430-Ratio Config 1 */
#define R1_CLKSEL_L3			(4 << 0)
#define R1_CLKSEL_L4			(2 << 5)
#define R1_CLKSEL_USB			(4 << 25)
#define R1_CM_CLKSEL1_CORE_VAL		(R1_CLKSEL_USB | RX_CLKSEL_SSI | \
					 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
					 R1_CLKSEL_L4 | R1_CLKSEL_L3)
#define R1_CLKSEL_MPU			(2 << 0)
#define R1_CM_CLKSEL_MPU_VAL		R1_CLKSEL_MPU
#define R1_CLKSEL_DSP			(2 << 0)
#define R1_CLKSEL_DSP_IF		(2 << 5)
#define R1_CM_CLKSEL_DSP_VAL		(R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
#define R1_CLKSEL_GFX			(2 << 0)
#define R1_CM_CLKSEL_GFX_VAL		R1_CLKSEL_GFX
#define R1_CLKSEL_MDM			(4 << 0)
#define R1_CM_CLKSEL_MDM_VAL		R1_CLKSEL_MDM

/* 2430-Ratio Config 2 */
#define R2_CLKSEL_L3			(6 << 0)
#define R2_CLKSEL_L4			(2 << 5)
#define R2_CLKSEL_USB			(2 << 25)
#define R2_CM_CLKSEL1_CORE_VAL		(R2_CLKSEL_USB | RX_CLKSEL_SSI | \
					 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
					 R2_CLKSEL_L4 | R2_CLKSEL_L3)
#define R2_CLKSEL_MPU			(2 << 0)
#define R2_CM_CLKSEL_MPU_VAL		R2_CLKSEL_MPU
#define R2_CLKSEL_DSP			(2 << 0)
#define R2_CLKSEL_DSP_IF		(3 << 5)
#define R2_CM_CLKSEL_DSP_VAL		(R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
#define R2_CLKSEL_GFX			(2 << 0)
#define R2_CM_CLKSEL_GFX_VAL		R2_CLKSEL_GFX
#define R2_CLKSEL_MDM			(6 << 0)
#define R2_CM_CLKSEL_MDM_VAL		R2_CLKSEL_MDM

/* 2430-Ratio Bootm (BYPASS) */
#define RB_CLKSEL_L3			(1 << 0)
#define RB_CLKSEL_L4			(1 << 5)
#define RB_CLKSEL_USB			(1 << 25)
#define RB_CM_CLKSEL1_CORE_VAL		(RB_CLKSEL_USB | RX_CLKSEL_SSI | \
					 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
					 RB_CLKSEL_L4 | RB_CLKSEL_L3)
#define RB_CLKSEL_MPU			(1 << 0)
#define RB_CM_CLKSEL_MPU_VAL		RB_CLKSEL_MPU
#define RB_CLKSEL_DSP			(1 << 0)
#define RB_CLKSEL_DSP_IF		(1 << 5)
#define RB_CM_CLKSEL_DSP_VAL		(RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
#define RB_CLKSEL_GFX			(1 << 0)
#define RB_CM_CLKSEL_GFX_VAL		RB_CLKSEL_GFX
#define RB_CLKSEL_MDM			(1 << 0)
#define RB_CM_CLKSEL_MDM_VAL		RB_CLKSEL_MDM

/* 2420 Ratio Equivalents */
#define RXX_CLKSEL_VLYNQ		(0x12 << 15)
#define RXX_CLKSEL_SSI			(0x8 << 20)

/* 2420-PRCM III 532MHz core */
#define RIII_CLKSEL_L3			(4 << 0)	/* 133MHz */
#define RIII_CLKSEL_L4			(2 << 5)	/* 66.5MHz */
#define RIII_CLKSEL_USB			(4 << 25)	/* 33.25MHz */
#define RIII_CM_CLKSEL1_CORE_VAL	(RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
					 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
					 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
					 RIII_CLKSEL_L3)
#define RIII_CLKSEL_MPU			(2 << 0)	/* 266MHz */
#define RIII_CM_CLKSEL_MPU_VAL		RIII_CLKSEL_MPU
#define RIII_CLKSEL_DSP			(3 << 0)	/* c5x - 177.3MHz */
#define RIII_CLKSEL_DSP_IF		(2 << 5)	/* c5x - 88.67MHz */
#define RIII_SYNC_DSP			(1 << 7)	/* Enable sync */
#define RIII_CLKSEL_IVA			(6 << 8)	/* iva1 - 88.67MHz */
#define RIII_SYNC_IVA			(1 << 13)	/* Enable sync */
#define RIII_CM_CLKSEL_DSP_VAL		(RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
					 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
					 RIII_CLKSEL_DSP)
#define RIII_CLKSEL_GFX			(2 << 0)	/* 66.5MHz */
#define RIII_CM_CLKSEL_GFX_VAL		RIII_CLKSEL_GFX

/* 2420-PRCM II 600MHz core */
#define RII_CLKSEL_L3			(6 << 0)	/* 100MHz */
#define RII_CLKSEL_L4			(2 << 5)	/* 50MHz */
#define RII_CLKSEL_USB			(2 << 25)	/* 50MHz */
#define RII_CM_CLKSEL1_CORE_VAL		(RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
					 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
					 RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
					 RII_CLKSEL_L3)
#define RII_CLKSEL_MPU			(2 << 0)	/* 300MHz */
#define RII_CM_CLKSEL_MPU_VAL		RII_CLKSEL_MPU
#define RII_CLKSEL_DSP			(3 << 0)	/* c5x - 200MHz */
#define RII_CLKSEL_DSP_IF		(2 << 5)	/* c5x - 100MHz */
#define RII_SYNC_DSP			(0 << 7)	/* Bypass sync */
#define RII_CLKSEL_IVA			(3 << 8)	/* iva1 - 200MHz */
#define RII_SYNC_IVA			(0 << 13)	/* Bypass sync */
#define RII_CM_CLKSEL_DSP_VAL		(RII_SYNC_IVA | RII_CLKSEL_IVA | \
					 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
					 RII_CLKSEL_DSP)
#define RII_CLKSEL_GFX			(2 << 0)	/* 50MHz */
#define RII_CM_CLKSEL_GFX_VAL		RII_CLKSEL_GFX

/* 2420-PRCM I 660MHz core */
#define RI_CLKSEL_L3			(4 << 0)	/* 165MHz */
#define RI_CLKSEL_L4			(2 << 5)	/* 82.5MHz */
#define RI_CLKSEL_USB			(4 << 25)	/* 41.25MHz */
#define RI_CM_CLKSEL1_CORE_VAL		(RI_CLKSEL_USB |		\
					 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
					 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
					 RI_CLKSEL_L4 | RI_CLKSEL_L3)
#define RI_CLKSEL_MPU			(2 << 0)	/* 330MHz */
#define RI_CM_CLKSEL_MPU_VAL		RI_CLKSEL_MPU
#define RI_CLKSEL_DSP			(3 << 0)	/* c5x - 220MHz */
#define RI_CLKSEL_DSP_IF		(2 << 5)	/* c5x - 110MHz */
#define RI_SYNC_DSP			(1 << 7)	/* Activate sync */
#define RI_CLKSEL_IVA			(4 << 8)	/* iva1 - 165MHz */
#define RI_SYNC_IVA			(0 << 13)	/* Bypass sync */
#define RI_CM_CLKSEL_DSP_VAL		(RI_SYNC_IVA | RI_CLKSEL_IVA |	\
					 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
					 RI_CLKSEL_DSP)
#define RI_CLKSEL_GFX			(1 << 0)	/* 165MHz */
#define RI_CM_CLKSEL_GFX_VAL		RI_CLKSEL_GFX

/* 2420-PRCM VII (boot) */
#define RVII_CLKSEL_L3			(1 << 0)
#define RVII_CLKSEL_L4			(1 << 5)
#define RVII_CLKSEL_DSS1		(1 << 8)
#define RVII_CLKSEL_DSS2		(0 << 13)
#define RVII_CLKSEL_VLYNQ		(1 << 15)
#define RVII_CLKSEL_SSI			(1 << 20)
#define RVII_CLKSEL_USB			(1 << 25)

#define RVII_CM_CLKSEL1_CORE_VAL	(RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
					 RVII_CLKSEL_VLYNQ | \
					 RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
					 RVII_CLKSEL_L4 | RVII_CLKSEL_L3)

#define RVII_CLKSEL_MPU			(1 << 0) /* all divide by 1 */
#define RVII_CM_CLKSEL_MPU_VAL		RVII_CLKSEL_MPU

#define RVII_CLKSEL_DSP			(1 << 0)
#define RVII_CLKSEL_DSP_IF		(1 << 5)
#define RVII_SYNC_DSP			(0 << 7)
#define RVII_CLKSEL_IVA			(1 << 8)
#define RVII_SYNC_IVA			(0 << 13)
#define RVII_CM_CLKSEL_DSP_VAL		(RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
					 RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
					 RVII_CLKSEL_DSP)

#define RVII_CLKSEL_GFX			(1 << 0)
#define RVII_CM_CLKSEL_GFX_VAL		RVII_CLKSEL_GFX

/*-------------------------------------------------------------------------
 * 2430 Target modes: Along with each configuration the CPU has several
 * modes which goes along with them. Modes mainly are the addition of
 * describe DPLL combinations to go along with a ratio.
 *-------------------------------------------------------------------------*/

/* Hardware governed */
#define MX_48M_SRC			(0 << 3)
#define MX_54M_SRC			(0 << 5)
#define MX_APLLS_CLIKIN_12		(3 << 23)
#define MX_APLLS_CLIKIN_13		(2 << 23)
#define MX_APLLS_CLIKIN_19_2		(0 << 23)

/*
 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 * #5a	(ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 */
#define M5A_DPLL_MULT_12		(133 << 12)
#define M5A_DPLL_DIV_12			(5 << 8)
#define M5A_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)
#define M5A_DPLL_MULT_13		(61 << 12)
#define M5A_DPLL_DIV_13			(2 << 8)
#define M5A_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)
#define M5A_DPLL_MULT_19		(55 << 12)
#define M5A_DPLL_DIV_19			(3 << 8)
#define M5A_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
					 MX_APLLS_CLIKIN_19_2)
/* #5b	(ratio1) target DPLL = 200*2 = 400MHz */
#define M5B_DPLL_MULT_12		(50 << 12)
#define M5B_DPLL_DIV_12			(2 << 8)
#define M5B_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)
#define M5B_DPLL_MULT_13		(200 << 12)
#define M5B_DPLL_DIV_13			(12 << 8)

#define M5B_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)
#define M5B_DPLL_MULT_19		(125 << 12)
#define M5B_DPLL_DIV_19			(31 << 8)
#define M5B_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
					 MX_APLLS_CLIKIN_19_2)
/*
 * #4	(ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 */
#define M4_DPLL_MULT_12			(133 << 12)
#define M4_DPLL_DIV_12			(3 << 8)
#define M4_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)

#define M4_DPLL_MULT_13			(399 << 12)
#define M4_DPLL_DIV_13			(12 << 8)
#define M4_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)

#define M4_DPLL_MULT_19			(145 << 12)
#define M4_DPLL_DIV_19			(6 << 8)
#define M4_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
					 MX_APLLS_CLIKIN_19_2)

/*
 * #3	(ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 */
#define M3_DPLL_MULT_12			(55 << 12)
#define M3_DPLL_DIV_12			(1 << 8)
#define M3_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)
#define M3_DPLL_MULT_13			(76 << 12)
#define M3_DPLL_DIV_13			(2 << 8)
#define M3_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)
#define M3_DPLL_MULT_19			(17 << 12)
#define M3_DPLL_DIV_19			(0 << 8)
#define M3_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
					 MX_APLLS_CLIKIN_19_2)

/*
 * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 */
#define M2_DPLL_MULT_12		        (55 << 12)
#define M2_DPLL_DIV_12		        (1 << 8)
#define M2_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)

/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 * relock time issue */
/* Core frequency changed from 330/165 to 329/164 MHz*/
#define M2_DPLL_MULT_13		        (76 << 12)
#define M2_DPLL_DIV_13		        (2 << 8)
#define M2_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)

#define M2_DPLL_MULT_19		        (17 << 12)
#define M2_DPLL_DIV_19		        (0 << 8)
#define M2_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
					 MX_APLLS_CLIKIN_19_2)

/* boot (boot) */
#define MB_DPLL_MULT			(1 << 12)
#define MB_DPLL_DIV			(0 << 8)
#define MB_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 MB_DPLL_DIV | MB_DPLL_MULT | \
					 MX_APLLS_CLIKIN_12)

#define MB_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 MB_DPLL_DIV | MB_DPLL_MULT | \
					 MX_APLLS_CLIKIN_13)

#define MB_CM_CLKSEL1_PLL_19_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 MB_DPLL_DIV | MB_DPLL_MULT | \
					 MX_APLLS_CLIKIN_19)

/*
 * 2430 - chassis (sedna)
 * 165 (ratio1) same as above #2
 * 150 (ratio1)
 * 133 (ratio2) same as above #4
 * 110 (ratio2) same as above #3
 * 104 (ratio2)
 * boot (boot)
 */

/* PRCM I target DPLL = 2*330MHz = 660MHz */
#define MI_DPLL_MULT_12			(55 << 12)
#define MI_DPLL_DIV_12			(1 << 8)
#define MI_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC | \
					 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)

/*
 * 2420 Equivalent - mode registers
 * PRCM II , target DPLL = 2*300MHz = 600MHz
 */
#define MII_DPLL_MULT_12		(50 << 12)
#define MII_DPLL_DIV_12			(1 << 8)
#define MII_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC |	\
					 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
					 MX_APLLS_CLIKIN_12)
#define MII_DPLL_MULT_13		(300 << 12)
#define MII_DPLL_DIV_13			(12 << 8)
#define MII_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC |	\
					 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
					 MX_APLLS_CLIKIN_13)

/* PRCM III target DPLL = 2*266 = 532MHz*/
#define MIII_DPLL_MULT_12		(133 << 12)
#define MIII_DPLL_DIV_12		(5 << 8)
#define MIII_CM_CLKSEL1_PLL_12_VAL	(MX_48M_SRC | MX_54M_SRC |	\
					 MIII_DPLL_DIV_12 | \
					 MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
#define MIII_DPLL_MULT_13		(266 << 12)
#define MIII_DPLL_DIV_13		(12 << 8)
#define MIII_CM_CLKSEL1_PLL_13_VAL	(MX_48M_SRC | MX_54M_SRC |	\
					 MIII_DPLL_DIV_13 | \
					 MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)

/* PRCM VII (boot bypass) */
#define MVII_CM_CLKSEL1_PLL_12_VAL	MB_CM_CLKSEL1_PLL_12_VAL
#define MVII_CM_CLKSEL1_PLL_13_VAL	MB_CM_CLKSEL1_PLL_13_VAL

/* High and low operation value */
#define MX_CLKSEL2_PLL_2x_VAL		(2 << 0)
#define MX_CLKSEL2_PLL_1x_VAL		(1 << 0)

/* MPU speed defines */
#define S12M	12000000
#define S13M	13000000
#define S19M	19200000
#define S26M	26000000
#define S100M	100000000
#define S133M	133000000
#define S150M	150000000
#define S164M	164000000
#define S165M	165000000
#define S199M	199000000
#define S200M	200000000
#define S266M	266000000
#define S300M	300000000
#define S329M	329000000
#define S330M	330000000
#define S399M	399000000
#define S400M	400000000
#define S532M	532000000
#define S600M	600000000
#define S658M	658000000
#define S660M	660000000
#define S798M	798000000


extern const struct prcm_config omap2420_rate_table[];

#ifdef CONFIG_ARCH_OMAP2430
extern const struct prcm_config omap2430_rate_table[];
#else
#define omap2430_rate_table	NULL
#endif
extern const struct prcm_config *rate_table;
extern const struct prcm_config *curr_prcm_set;

#endif
Commit	Line	Data
d8a94458 PW	1	/*
	2	* opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
	3	*
	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2009 Nokia Corporation
	6	*
	7	* Richard Woodruff <r-woodruff2@ti.com>
	8	*
	9	* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
	10	* These configurations are characterized by voltage and speed for clocks.
	11	* The device is only validated for certain combinations. One way to express
	12	* these combinations is via the 'ratio's' which the clocks operate with
	13	* respect to each other. These ratio sets are for a given voltage/DPLL
	14	* setting. All configurations can be described by a DPLL setting and a ratio
	15	* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
	16	*
	17	* 2430 differs from 2420 in that there are no more phase synchronizers used.
	18	* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
	19	* 2430 (iva2.1, NOdsp, mdm)
	20	*
	21	* XXX Missing voltage data.
	22	*
	23	* THe format described in this file is deprecated. Once a reasonable
	24	* OPP API exists, the data in this file should be converted to use it.
	25	*
	26	* This is technically part of the OMAP2xxx clock code.
	27	*/
	28
	29	#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
	30	#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
	31
	32	/**
	33	* struct prcm_config - define clock rates on a per-OPP basis (24xx)
	34	*
	35	* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
	36	* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
	37	* CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
	38	*
	39	* This is deprecated. As soon as we have a decent OPP API, we should
	40	* move all this stuff to it.
	41	*/
	42	struct prcm_config {
	43	unsigned long xtal_speed; /* crystal rate */
	44	unsigned long dpll_speed; /* dpll: outxtalM/(N-1)table_recalc */
	45	unsigned long mpu_speed; /* speed of MPU */
	46	unsigned long cm_clksel_mpu; /* mpu divider */
	47	unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
	48	unsigned long cm_clksel_gfx; /* gfx dividers */
	49	unsigned long cm_clksel1_core; /* major subsystem dividers */
	50	unsigned long cm_clksel1_pll; /* m,n */
	51	unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
	52	unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
	53	unsigned long base_sdrc_rfr; /* base refresh timing for a set */
	54	unsigned char flags;
	55	};
	56
	57
	58	/* Core fields for cm_clksel, not ratio governed */
	59	#define RX_CLKSEL_DSS1 (0x10 << 8)
	60	#define RX_CLKSEL_DSS2 (0x0 << 13)
	61	#define RX_CLKSEL_SSI (0x5 << 20)
	62
	63	/*-------------------------------------------------------------------------
	64	* Voltage/DPLL ratios
65	-------------------------------------------------------------------------/
66
67	/* 2430 Ratio's, 2430-Ratio Config 1 */
68	#define R1_CLKSEL_L3 (4 << 0)
69	#define R1_CLKSEL_L4 (2 << 5)
70	#define R1_CLKSEL_USB (4 << 25)
71	#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB \| RX_CLKSEL_SSI \| \
72	RX_CLKSEL_DSS2 \| RX_CLKSEL_DSS1 \| \
73	R1_CLKSEL_L4 \| R1_CLKSEL_L3)
74	#define R1_CLKSEL_MPU (2 << 0)
75	#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
76	#define R1_CLKSEL_DSP (2 << 0)
77	#define R1_CLKSEL_DSP_IF (2 << 5)
78	#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP \| R1_CLKSEL_DSP_IF)
79	#define R1_CLKSEL_GFX (2 << 0)
80	#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
81	#define R1_CLKSEL_MDM (4 << 0)
82	#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
83
84	/* 2430-Ratio Config 2 */
85	#define R2_CLKSEL_L3 (6 << 0)
86	#define R2_CLKSEL_L4 (2 << 5)
87	#define R2_CLKSEL_USB (2 << 25)
88	#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB \| RX_CLKSEL_SSI \| \
89	RX_CLKSEL_DSS2 \| RX_CLKSEL_DSS1 \| \
90	R2_CLKSEL_L4 \| R2_CLKSEL_L3)
91	#define R2_CLKSEL_MPU (2 << 0)
92	#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
93	#define R2_CLKSEL_DSP (2 << 0)
94	#define R2_CLKSEL_DSP_IF (3 << 5)
95	#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP \| R2_CLKSEL_DSP_IF)
96	#define R2_CLKSEL_GFX (2 << 0)
97	#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
98	#define R2_CLKSEL_MDM (6 << 0)
99	#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
100
101	/* 2430-Ratio Bootm (BYPASS) */
102	#define RB_CLKSEL_L3 (1 << 0)
103	#define RB_CLKSEL_L4 (1 << 5)
104	#define RB_CLKSEL_USB (1 << 25)
105	#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB \| RX_CLKSEL_SSI \| \
106	RX_CLKSEL_DSS2 \| RX_CLKSEL_DSS1 \| \
107	RB_CLKSEL_L4 \| RB_CLKSEL_L3)
108	#define RB_CLKSEL_MPU (1 << 0)
109	#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
110	#define RB_CLKSEL_DSP (1 << 0)
111	#define RB_CLKSEL_DSP_IF (1 << 5)
112	#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP \| RB_CLKSEL_DSP_IF)
113	#define RB_CLKSEL_GFX (1 << 0)
114	#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
115	#define RB_CLKSEL_MDM (1 << 0)
116	#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
117
118	/* 2420 Ratio Equivalents */
119	#define RXX_CLKSEL_VLYNQ (0x12 << 15)
120	#define RXX_CLKSEL_SSI (0x8 << 20)
121
122	/* 2420-PRCM III 532MHz core */
123	#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
124	#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
125	#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
126	#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB \| RXX_CLKSEL_SSI \| \
127	RXX_CLKSEL_VLYNQ \| RX_CLKSEL_DSS2 \| \
128	RX_CLKSEL_DSS1 \| RIII_CLKSEL_L4 \| \
129	RIII_CLKSEL_L3)
130	#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
131	#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
132	#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
133	#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
134	#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
135	#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
136	#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
137	#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA \| RIII_CLKSEL_IVA \| \
138	RIII_SYNC_DSP \| RIII_CLKSEL_DSP_IF \| \
139	RIII_CLKSEL_DSP)
140	#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
141	#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
142
143	/* 2420-PRCM II 600MHz core */
144	#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
145	#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
146	#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
147	#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB \| RXX_CLKSEL_SSI \| \
148	RXX_CLKSEL_VLYNQ \| RX_CLKSEL_DSS2 \| \
149	RX_CLKSEL_DSS1 \| RII_CLKSEL_L4 \| \
150	RII_CLKSEL_L3)
151	#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
152	#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
153	#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
154	#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
155	#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
156	#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
157	#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
158	#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA \| RII_CLKSEL_IVA \| \
159	RII_SYNC_DSP \| RII_CLKSEL_DSP_IF \| \
160	RII_CLKSEL_DSP)
161	#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
162	#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
163
164	/* 2420-PRCM I 660MHz core */
165	#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
166	#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
167	#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
168	#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB \| \
169	RXX_CLKSEL_SSI \| RXX_CLKSEL_VLYNQ \| \
170	RX_CLKSEL_DSS2 \| RX_CLKSEL_DSS1 \| \
171	RI_CLKSEL_L4 \| RI_CLKSEL_L3)
172	#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
173	#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
174	#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
175	#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
176	#define RI_SYNC_DSP (1 << 7) /* Activate sync */
177	#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
178	#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
179	#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA \| RI_CLKSEL_IVA \| \
180	RI_SYNC_DSP \| RI_CLKSEL_DSP_IF \| \
181	RI_CLKSEL_DSP)
182	#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
183	#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
184
185	/* 2420-PRCM VII (boot) */
186	#define RVII_CLKSEL_L3 (1 << 0)
187	#define RVII_CLKSEL_L4 (1 << 5)
188	#define RVII_CLKSEL_DSS1 (1 << 8)
189	#define RVII_CLKSEL_DSS2 (0 << 13)
190	#define RVII_CLKSEL_VLYNQ (1 << 15)
191	#define RVII_CLKSEL_SSI (1 << 20)
192	#define RVII_CLKSEL_USB (1 << 25)
193
194	#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB \| RVII_CLKSEL_SSI \| \
195	RVII_CLKSEL_VLYNQ \| \
196	RVII_CLKSEL_DSS2 \| RVII_CLKSEL_DSS1 \| \
197	RVII_CLKSEL_L4 \| RVII_CLKSEL_L3)
198
199	#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
200	#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
201
202	#define RVII_CLKSEL_DSP (1 << 0)
203	#define RVII_CLKSEL_DSP_IF (1 << 5)
204	#define RVII_SYNC_DSP (0 << 7)
205	#define RVII_CLKSEL_IVA (1 << 8)
206	#define RVII_SYNC_IVA (0 << 13)
207	#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA \| RVII_CLKSEL_IVA \| \
208	RVII_SYNC_DSP \| RVII_CLKSEL_DSP_IF \| \
209	RVII_CLKSEL_DSP)
210
211	#define RVII_CLKSEL_GFX (1 << 0)
212	#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
213
214	/*-------------------------------------------------------------------------
215	* 2430 Target modes: Along with each configuration the CPU has several
216	* modes which goes along with them. Modes mainly are the addition of
217	* describe DPLL combinations to go along with a ratio.
218	-------------------------------------------------------------------------/
219
220	/* Hardware governed */
221	#define MX_48M_SRC (0 << 3)
222	#define MX_54M_SRC (0 << 5)
223	#define MX_APLLS_CLIKIN_12 (3 << 23)
224	#define MX_APLLS_CLIKIN_13 (2 << 23)
225	#define MX_APLLS_CLIKIN_19_2 (0 << 23)
226
227	/*
228	* 2430 - standalone, 2refM/(n+1), M/N is for exactness not relock speed
229	* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
230	*/
231	#define M5A_DPLL_MULT_12 (133 << 12)
232	#define M5A_DPLL_DIV_12 (5 << 8)
233	#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
234	M5A_DPLL_DIV_12 \| M5A_DPLL_MULT_12 \| \
235	MX_APLLS_CLIKIN_12)
236	#define M5A_DPLL_MULT_13 (61 << 12)
237	#define M5A_DPLL_DIV_13 (2 << 8)
238	#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
239	M5A_DPLL_DIV_13 \| M5A_DPLL_MULT_13 \| \
240	MX_APLLS_CLIKIN_13)
241	#define M5A_DPLL_MULT_19 (55 << 12)
242	#define M5A_DPLL_DIV_19 (3 << 8)
243	#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
244	M5A_DPLL_DIV_19 \| M5A_DPLL_MULT_19 \| \
245	MX_APLLS_CLIKIN_19_2)
246	/* #5b (ratio1) target DPLL = 2002 = 400MHz /
247	#define M5B_DPLL_MULT_12 (50 << 12)
248	#define M5B_DPLL_DIV_12 (2 << 8)
249	#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
250	M5B_DPLL_DIV_12 \| M5B_DPLL_MULT_12 \| \
251	MX_APLLS_CLIKIN_12)
252	#define M5B_DPLL_MULT_13 (200 << 12)
253	#define M5B_DPLL_DIV_13 (12 << 8)
254
255	#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
256	M5B_DPLL_DIV_13 \| M5B_DPLL_MULT_13 \| \
257	MX_APLLS_CLIKIN_13)
258	#define M5B_DPLL_MULT_19 (125 << 12)
259	#define M5B_DPLL_DIV_19 (31 << 8)
260	#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
261	M5B_DPLL_DIV_19 \| M5B_DPLL_MULT_19 \| \
262	MX_APLLS_CLIKIN_19_2)
263	/*
264	* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
265	*/
266	#define M4_DPLL_MULT_12 (133 << 12)
267	#define M4_DPLL_DIV_12 (3 << 8)
268	#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
269	M4_DPLL_DIV_12 \| M4_DPLL_MULT_12 \| \
270	MX_APLLS_CLIKIN_12)
271
272	#define M4_DPLL_MULT_13 (399 << 12)
273	#define M4_DPLL_DIV_13 (12 << 8)
274	#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
275	M4_DPLL_DIV_13 \| M4_DPLL_MULT_13 \| \
276	MX_APLLS_CLIKIN_13)
277
278	#define M4_DPLL_MULT_19 (145 << 12)
279	#define M4_DPLL_DIV_19 (6 << 8)
280	#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
281	M4_DPLL_DIV_19 \| M4_DPLL_MULT_19 \| \
282	MX_APLLS_CLIKIN_19_2)
283
284	/*
285	* #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
286	*/
287	#define M3_DPLL_MULT_12 (55 << 12)
288	#define M3_DPLL_DIV_12 (1 << 8)
289	#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
290	M3_DPLL_DIV_12 \| M3_DPLL_MULT_12 \| \
291	MX_APLLS_CLIKIN_12)
292	#define M3_DPLL_MULT_13 (76 << 12)
293	#define M3_DPLL_DIV_13 (2 << 8)
294	#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
295	M3_DPLL_DIV_13 \| M3_DPLL_MULT_13 \| \
296	MX_APLLS_CLIKIN_13)
297	#define M3_DPLL_MULT_19 (17 << 12)
298	#define M3_DPLL_DIV_19 (0 << 8)
299	#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
300	M3_DPLL_DIV_19 \| M3_DPLL_MULT_19 \| \
301	MX_APLLS_CLIKIN_19_2)
302
303	/*
304	* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
305	*/
306	#define M2_DPLL_MULT_12 (55 << 12)
307	#define M2_DPLL_DIV_12 (1 << 8)
308	#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
309	M2_DPLL_DIV_12 \| M2_DPLL_MULT_12 \| \
310	MX_APLLS_CLIKIN_12)
311
312	/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
313	* relock time issue */
314	/* Core frequency changed from 330/165 to 329/164 MHz*/
315	#define M2_DPLL_MULT_13 (76 << 12)
316	#define M2_DPLL_DIV_13 (2 << 8)
317	#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
318	M2_DPLL_DIV_13 \| M2_DPLL_MULT_13 \| \
319	MX_APLLS_CLIKIN_13)
320
321	#define M2_DPLL_MULT_19 (17 << 12)
322	#define M2_DPLL_DIV_19 (0 << 8)
323	#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
324	M2_DPLL_DIV_19 \| M2_DPLL_MULT_19 \| \
325	MX_APLLS_CLIKIN_19_2)
326
327	/* boot (boot) */
328	#define MB_DPLL_MULT (1 << 12)
329	#define MB_DPLL_DIV (0 << 8)
330	#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
331	MB_DPLL_DIV \| MB_DPLL_MULT \| \
332	MX_APLLS_CLIKIN_12)
333
334	#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
335	MB_DPLL_DIV \| MB_DPLL_MULT \| \
336	MX_APLLS_CLIKIN_13)
337
338	#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC \| MX_54M_SRC \| \
339	MB_DPLL_DIV \| MB_DPLL_MULT \| \
340	MX_APLLS_CLIKIN_19)
341
342	/*
343	* 2430 - chassis (sedna)
344	* 165 (ratio1) same as above #2
345	* 150 (ratio1)
346	* 133 (ratio2) same as above #4
347	* 110 (ratio2) same as above #3
348	* 104 (ratio2)
349	* boot (boot)
350	*/
351
352	/* PRCM I target DPLL = 2330MHz = 660MHz /
353	#define MI_DPLL_MULT_12 (55 << 12)
354	#define MI_DPLL_DIV_12 (1 << 8)
355	#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
356	MI_DPLL_DIV_12 \| MI_DPLL_MULT_12 \| \
357	MX_APLLS_CLIKIN_12)
358
359	/*
360	* 2420 Equivalent - mode registers
361	* PRCM II , target DPLL = 2*300MHz = 600MHz
362	*/
363	#define MII_DPLL_MULT_12 (50 << 12)
364	#define MII_DPLL_DIV_12 (1 << 8)
365	#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
366	MII_DPLL_DIV_12 \| MII_DPLL_MULT_12 \| \
367	MX_APLLS_CLIKIN_12)
368	#define MII_DPLL_MULT_13 (300 << 12)
369	#define MII_DPLL_DIV_13 (12 << 8)
370	#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
371	MII_DPLL_DIV_13 \| MII_DPLL_MULT_13 \| \
372	MX_APLLS_CLIKIN_13)
373
374	/* PRCM III target DPLL = 2266 = 532MHz/
375	#define MIII_DPLL_MULT_12 (133 << 12)
376	#define MIII_DPLL_DIV_12 (5 << 8)
377	#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC \| MX_54M_SRC \| \
378	MIII_DPLL_DIV_12 \| \
379	MIII_DPLL_MULT_12 \| MX_APLLS_CLIKIN_12)
380	#define MIII_DPLL_MULT_13 (266 << 12)
381	#define MIII_DPLL_DIV_13 (12 << 8)
382	#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC \| MX_54M_SRC \| \
383	MIII_DPLL_DIV_13 \| \
384	MIII_DPLL_MULT_13 \| MX_APLLS_CLIKIN_13)
385
386	/* PRCM VII (boot bypass) */
387	#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
388	#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
389
390	/* High and low operation value */
391	#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
392	#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
393
394	/* MPU speed defines */
395	#define S12M 12000000
396	#define S13M 13000000
397	#define S19M 19200000
398	#define S26M 26000000
399	#define S100M 100000000
400	#define S133M 133000000
401	#define S150M 150000000
402	#define S164M 164000000
403	#define S165M 165000000
404	#define S199M 199000000
405	#define S200M 200000000
406	#define S266M 266000000
407	#define S300M 300000000
408	#define S329M 329000000
409	#define S330M 330000000
410	#define S399M 399000000
411	#define S400M 400000000
412	#define S532M 532000000
413	#define S600M 600000000
414	#define S658M 658000000
415	#define S660M 660000000
416	#define S798M 798000000
417
418
419	extern const struct prcm_config omap2420_rate_table[];
56213ca4 TL	420
56213ca4 TL	421	#ifdef CONFIG_ARCH_OMAP2430
d8a94458	422	extern const struct prcm_config omap2430_rate_table[];
56213ca4 TL	423	#else
	424	#define omap2430_rate_table NULL
	425	#endif
d8a94458 PW	426	extern const struct prcm_config *rate_table;
	427	extern const struct prcm_config *curr_prcm_set;
	428
	429	#endif