[net-next-2.6.git] / arch / arm / mach-omap2 / mmc-twl4030.c

/*
 * linux/arch/arm/mach-omap2/mmc-twl4030.c
 *
 * Copyright (C) 2007-2008 Texas Instruments
 * Copyright (C) 2008 Nokia Corporation
 * Author: Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <plat/control.h>
#include <plat/mmc.h>

#include "mmc-twl4030.h"

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static u16 control_pbias_offset;
static u16 control_devconf1_offset;

#define HSMMC_NAME_LEN	9

static struct twl_mmc_controller {
	char				name[HSMMC_NAME_LEN + 1];
} hsmmc[OMAP34XX_NR_MMC];

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

static int twl4030_mmc_get_context_loss(struct device *dev)
{
	/* FIXME: PM DPS not implemented yet */
	return 0;
}

#else
#define twl4030_mmc_get_context_loss NULL
#endif

static void hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 *
	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	 * is most naturally TWL VSIM; those pins also use PBIAS.
	 *
	 * FIXME handle VMMC1A as needed ...
	 */
	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;

	/* 100ms delay required for PBIAS configuration */
	msleep(100);

	if (power_on) {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP2_PBIASLITEVMODE0;
		else
			reg |= OMAP2_PBIASLITEVMODE0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
			OMAP2_PBIASLITEVMODE0);
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void hsmmc23_before_set_reg(struct device *dev, int slot,
				   int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (power_on) {
		/* Only MMC2 supports a CLKIN */
		if (mmc->slots[0].internal_clock) {
			u32 reg;

			reg = omap_ctrl_readl(control_devconf1_offset);
			reg |= OMAP2_MMCSDIO2ADPCLKISEL;
			omap_ctrl_writel(reg, control_devconf1_offset);
		}
	}
}

static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;

void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
{
	struct twl4030_hsmmc_info *c;
	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
	int i;

	if (cpu_is_omap2430()) {
		control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
	} else {
		control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	}

	for (c = controllers; c->mmc; c++) {
		struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
		struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];

		if (!c->mmc || c->mmc > nr_hsmmc) {
			pr_debug("MMC%d: no such controller\n", c->mmc);
			continue;
		}
		if (mmc) {
			pr_debug("MMC%d: already configured\n", c->mmc);
			continue;
		}

		mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
		if (!mmc) {
			pr_err("Cannot allocate memory for mmc device!\n");
			goto done;
		}

		if (c->name)
			strncpy(twl->name, c->name, HSMMC_NAME_LEN);
		else
			snprintf(twl->name, ARRAY_SIZE(twl->name),
				"mmc%islot%i", c->mmc, 1);
		mmc->slots[0].name = twl->name;
		mmc->nr_slots = 1;
		mmc->slots[0].wires = c->wires;
		mmc->slots[0].internal_clock = !c->ext_clock;
		mmc->dma_mask = 0xffffffff;

		mmc->get_context_loss_count =
				twl4030_mmc_get_context_loss;

		mmc->slots[0].switch_pin = c->gpio_cd;
		mmc->slots[0].gpio_wp = c->gpio_wp;

		if (c->cover_only)
			mmc->slots[0].cover = 1;

		if (c->nonremovable)
			mmc->slots[0].nonremovable = 1;

		if (c->power_saving)
			mmc->slots[0].power_saving = 1;

		/* NOTE:  MMC slots should have a Vcc regulator set up.
		 * This may be from a TWL4030-family chip, another
		 * controllable regulator, or a fixed supply.
		 *
		 * temporary HACK: ocr_mask instead of fixed supply
		 */
		mmc->slots[0].ocr_mask = c->ocr_mask;

		switch (c->mmc) {
		case 1:
			/* on-chip level shifting via PBIAS0/PBIAS1 */
			mmc->slots[0].before_set_reg = hsmmc1_before_set_reg;
			mmc->slots[0].after_set_reg = hsmmc1_after_set_reg;

			/* Omap3630 HSMMC1 supports only 4-bit */
			if (cpu_is_omap3630() && c->wires > 4) {
				c->wires = 4;
				mmc->slots[0].wires = c->wires;
			}
			break;
		case 2:
			if (c->ext_clock)
				c->transceiver = 1;
			if (c->transceiver && c->wires > 4)
				c->wires = 4;
			/* FALLTHROUGH */
		case 3:
			/* off-chip level shifting, or none */
			mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
			mmc->slots[0].after_set_reg = NULL;
			break;
		default:
			pr_err("MMC%d configuration not supported!\n", c->mmc);
			kfree(mmc);
			continue;
		}
		hsmmc_data[c->mmc - 1] = mmc;
	}

	omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);

	/* pass the device nodes back to board setup code */
	for (c = controllers; c->mmc; c++) {
		struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];

		if (!c->mmc || c->mmc > nr_hsmmc)
			continue;
		c->dev = mmc->dev;
	}

done:
	for (i = 0; i < nr_hsmmc; i++)
		kfree(hsmmc_data[i]);
}

#endif
Commit	Line	Data
90c62bf0 TL	1	/*
	2	* linux/arch/arm/mach-omap2/mmc-twl4030.c
	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments
	5	* Copyright (C) 2008 Nokia Corporation
	6	* Author: Texas Instruments
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
db0fefc5 AH	12	#include <linux/kernel.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
90c62bf0	15	#include <linux/delay.h>
90c62bf0	16	#include <mach/hardware.h>
ce491cf8 TL	17	#include <plat/control.h>
ce491cf8 TL	18	#include <plat/mmc.h>
90c62bf0 TL	19
	20	#include "mmc-twl4030.h"
	21
db0fefc5	22	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
90c62bf0 TL	23
	24	static u16 control_pbias_offset;
	25	static u16 control_devconf1_offset;
	26
	27	#define HSMMC_NAME_LEN 9
	28
	29	static struct twl_mmc_controller {
b583f26d DB	30	char name[HSMMC_NAME_LEN + 1];
b583f26d DB	31	} hsmmc[OMAP34XX_NR_MMC];
90c62bf0	32
1887bde3 DK	33	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	34
	35	static int twl4030_mmc_get_context_loss(struct device *dev)
	36	{
	37	/* FIXME: PM DPS not implemented yet */
	38	return 0;
	39	}
	40
	41	#else
	42	#define twl4030_mmc_get_context_loss NULL
	43	#endif
	44
db0fefc5 AH	45	static void hsmmc1_before_set_reg(struct device *dev, int slot,
db0fefc5 AH	46	int power_on, int vdd)
90c62bf0	47	{
555d503f	48	u32 reg, prog_io;
90c62bf0 TL	49	struct omap_mmc_platform_data *mmc = dev->platform_data;
90c62bf0 TL	50
0329c377 DB	51	/*
0329c377 DB	52	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
b583f26d	53	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
0329c377 DB	54	* 1.8V and 3.0V modes, controlled by the PBIAS register.
	55	*
	56	* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	57	* is most naturally TWL VSIM; those pins also use PBIAS.
b583f26d DB	58	*
b583f26d DB	59	* FIXME handle VMMC1A as needed ...
0329c377	60	*/
90c62bf0 TL	61	if (power_on) {
	62	if (cpu_is_omap2430()) {
	63	reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
	64	if ((1 << vdd) >= MMC_VDD_30_31)
	65	reg \|= OMAP243X_MMC1_ACTIVE_OVERWRITE;
	66	else
	67	reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
	68	omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
	69	}
	70
	71	if (mmc->slots[0].internal_clock) {
	72	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	73	reg \|= OMAP2_MMCSDIO1ADPCLKISEL;
	74	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
	75	}
	76
	77	reg = omap_ctrl_readl(control_pbias_offset);
555d503f M	78	if (cpu_is_omap3630()) {
	79	/* Set MMC I/O to 52Mhz */
	80	prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	81	prog_io \|= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
	82	omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
	83	} else {
	84	reg \|= OMAP2_PBIASSPEEDCTRL0;
	85	}
90c62bf0 TL	86	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
90c62bf0 TL	87	omap_ctrl_writel(reg, control_pbias_offset);
db0fefc5 AH	88	} else {
	89	reg = omap_ctrl_readl(control_pbias_offset);
	90	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
	91	omap_ctrl_writel(reg, control_pbias_offset);
	92	}
	93	}
	94
	95	static void hsmmc1_after_set_reg(struct device *dev, int slot,
	96	int power_on, int vdd)
	97	{
	98	u32 reg;
90c62bf0	99
db0fefc5 AH	100	/* 100ms delay required for PBIAS configuration */
db0fefc5 AH	101	msleep(100);
90c62bf0	102
db0fefc5	103	if (power_on) {
90c62bf0 TL	104	reg = omap_ctrl_readl(control_pbias_offset);
	105	reg \|= (OMAP2_PBIASLITEPWRDNZ0 \| OMAP2_PBIASSPEEDCTRL0);
	106	if ((1 << vdd) <= MMC_VDD_165_195)
	107	reg &= ~OMAP2_PBIASLITEVMODE0;
	108	else
	109	reg \|= OMAP2_PBIASLITEVMODE0;
	110	omap_ctrl_writel(reg, control_pbias_offset);
	111	} else {
90c62bf0 TL	112	reg = omap_ctrl_readl(control_pbias_offset);
	113	reg \|= (OMAP2_PBIASSPEEDCTRL0 \| OMAP2_PBIASLITEPWRDNZ0 \|
	114	OMAP2_PBIASLITEVMODE0);
	115	omap_ctrl_writel(reg, control_pbias_offset);
	116	}
90c62bf0 TL	117	}
90c62bf0 TL	118
db0fefc5 AH	119	static void hsmmc23_before_set_reg(struct device *dev, int slot,
db0fefc5 AH	120	int power_on, int vdd)
90c62bf0	121	{
90c62bf0	122	struct omap_mmc_platform_data *mmc = dev->platform_data;
b583f26d	123
90c62bf0	124	if (power_on) {
db0fefc5	125	/* Only MMC2 supports a CLKIN */
90c62bf0 TL	126	if (mmc->slots[0].internal_clock) {
	127	u32 reg;
	128
	129	reg = omap_ctrl_readl(control_devconf1_offset);
	130	reg \|= OMAP2_MMCSDIO2ADPCLKISEL;
	131	omap_ctrl_writel(reg, control_devconf1_offset);
	132	}
9b7c18e0	133	}
9b7c18e0 AH	134	}
9b7c18e0 AH	135
90c62bf0 TL	136	static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
	137
	138	void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
	139	{
	140	struct twl4030_hsmmc_info *c;
	141	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
a6c7fdd2	142	int i;
90c62bf0 TL	143
	144	if (cpu_is_omap2430()) {
	145	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
	146	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
90c62bf0 TL	147	} else {
	148	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
	149	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	150	}
	151
	152	for (c = controllers; c->mmc; c++) {
	153	struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
	154	struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
	155
	156	if (!c->mmc \|\| c->mmc > nr_hsmmc) {
	157	pr_debug("MMC%d: no such controller\n", c->mmc);
	158	continue;
	159	}
	160	if (mmc) {
	161	pr_debug("MMC%d: already configured\n", c->mmc);
	162	continue;
	163	}
	164
	165	mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	166	if (!mmc) {
	167	pr_err("Cannot allocate memory for mmc device!\n");
a6c7fdd2	168	goto done;
90c62bf0 TL	169	}
90c62bf0 TL	170
e51151a5 AH	171	if (c->name)
	172	strncpy(twl->name, c->name, HSMMC_NAME_LEN);
	173	else
	174	snprintf(twl->name, ARRAY_SIZE(twl->name),
	175	"mmc%islot%i", c->mmc, 1);
90c62bf0 TL	176	mmc->slots[0].name = twl->name;
90c62bf0 TL	177	mmc->nr_slots = 1;
90c62bf0 TL	178	mmc->slots[0].wires = c->wires;
	179	mmc->slots[0].internal_clock = !c->ext_clock;
	180	mmc->dma_mask = 0xffffffff;
90c62bf0	181
1887bde3 DK	182	mmc->get_context_loss_count =
	183	twl4030_mmc_get_context_loss;
	184
db0fefc5 AH	185	mmc->slots[0].switch_pin = c->gpio_cd;
db0fefc5 AH	186	mmc->slots[0].gpio_wp = c->gpio_wp;
90c62bf0	187
db0fefc5 AH	188	if (c->cover_only)
db0fefc5 AH	189	mmc->slots[0].cover = 1;
90c62bf0	190
23d99bb9 AH	191	if (c->nonremovable)
	192	mmc->slots[0].nonremovable = 1;
	193
dd498eff DK	194	if (c->power_saving)
	195	mmc->slots[0].power_saving = 1;
	196
b583f26d DB	197	/* NOTE: MMC slots should have a Vcc regulator set up.
	198	* This may be from a TWL4030-family chip, another
	199	* controllable regulator, or a fixed supply.
	200	*
	201	* temporary HACK: ocr_mask instead of fixed supply
90c62bf0	202	*/
b583f26d	203	mmc->slots[0].ocr_mask = c->ocr_mask;
90c62bf0 TL	204
	205	switch (c->mmc) {
	206	case 1:
b583f26d	207	/* on-chip level shifting via PBIAS0/PBIAS1 */
db0fefc5 AH	208	mmc->slots[0].before_set_reg = hsmmc1_before_set_reg;
db0fefc5 AH	209	mmc->slots[0].after_set_reg = hsmmc1_after_set_reg;
41fd03d6 M	210
	211	/* Omap3630 HSMMC1 supports only 4-bit */
	212	if (cpu_is_omap3630() && c->wires > 4) {
	213	c->wires = 4;
	214	mmc->slots[0].wires = c->wires;
	215	}
90c62bf0 TL	216	break;
90c62bf0 TL	217	case 2:
b583f26d DB	218	if (c->ext_clock)
	219	c->transceiver = 1;
	220	if (c->transceiver && c->wires > 4)
	221	c->wires = 4;
	222	/* FALLTHROUGH */
07d83cc9	223	case 3:
b583f26d	224	/* off-chip level shifting, or none */
db0fefc5 AH	225	mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
db0fefc5 AH	226	mmc->slots[0].after_set_reg = NULL;
07d83cc9	227	break;
90c62bf0 TL	228	default:
90c62bf0 TL	229	pr_err("MMC%d configuration not supported!\n", c->mmc);
07d83cc9	230	kfree(mmc);
90c62bf0 TL	231	continue;
	232	}
	233	hsmmc_data[c->mmc - 1] = mmc;
	234	}
	235
	236	omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
01971f65 DB	237
	238	/* pass the device nodes back to board setup code */
	239	for (c = controllers; c->mmc; c++) {
	240	struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
	241
	242	if (!c->mmc \|\| c->mmc > nr_hsmmc)
	243	continue;
	244	c->dev = mmc->dev;
	245	}
a6c7fdd2 AK	246
	247	done:
	248	for (i = 0; i < nr_hsmmc; i++)
	249	kfree(hsmmc_data[i]);
90c62bf0 TL	250	}
	251
	252	#endif