[net-next-2.6.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach/irq.h>


/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

static int previous_irq;

/*
 * On 34xx we can get occasional spurious interrupts if the ack from
 * an interrupt handler does not get posted before we unmask. Warn about
 * the interrupt handlers that need to flush posted writes.
 */
static int omap_check_spurious(unsigned int irq)
{
	u32 sir, spurious;

	sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
	spurious = sir >> 7;

	if (spurious) {
		printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
					"posted write for irq %i\n",
					irq, sir, previous_irq);
		return spurious;
	}

	return 0;
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(unsigned int irq)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_irq(unsigned int irq)
{
	int offset = irq & (~(IRQ_BITS_PER_REG - 1));

	if (cpu_is_omap34xx()) {
		int spurious = 0;

		/*
		 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
		 * it is the highest irq number?
		 */
		if (irq == INT_34XX_GPT12_IRQ)
			spurious = omap_check_spurious(irq);

		if (!spurious)
			previous_irq = irq;
	}

	irq &= (IRQ_BITS_PER_REG - 1);

	intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
}

static void omap_unmask_irq(unsigned int irq)
{
	int offset = irq & (~(IRQ_BITS_PER_REG - 1));

	irq &= (IRQ_BITS_PER_REG - 1);

	intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
}

static void omap_mask_ack_irq(unsigned int irq)
{
	omap_mask_irq(irq);
	omap_ack_irq(irq);
}

static struct irq_chip omap_irq_chip = {
	.name	= "INTC",
	.ack	= omap_mask_ack_irq,
	.mask	= omap_mask_irq,
	.unmask	= omap_unmask_irq,
};

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

void __init omap_init_irq(void)
{
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		unsigned long base = 0;
		struct omap_irq_bank *bank = irq_banks + i;

		if (cpu_is_omap24xx())
			base = OMAP24XX_IC_BASE;
		else if (cpu_is_omap34xx())
			base = OMAP34XX_IC_BASE;

		BUG_ON(!base);

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");

	for (i = 0; i < nr_of_irqs; i++) {
		set_irq_chip(i, &omap_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
}

#ifdef CONFIG_ARCH_OMAP3
void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
	/* Disable autoidle as it can stall interrupt controller */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
#endif /* CONFIG_ARCH_OMAP3 */
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
1dbae815	15	#include <linux/interrupt.h>
2e7509e5	16	#include <linux/io.h>
a09e64fb	17	#include <mach/hardware.h>
1dbae815	18	#include <asm/mach/irq.h>
1dbae815	19
2e7509e5 PW	20
	21	/* selected INTC register offsets */
	22
	23	#define INTC_REVISION 0x0000
	24	#define INTC_SYSCONFIG 0x0010
	25	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	26	#define INTC_SIR 0x0040
2e7509e5	27	#define INTC_CONTROL 0x0048
0addd61b RN	28	#define INTC_PROTECTION 0x004C
	29	#define INTC_IDLE 0x0050
	30	#define INTC_THRESHOLD 0x0068
	31	#define INTC_MIR0 0x0084
2e7509e5 PW	32	#define INTC_MIR_CLEAR0 0x0088
	33	#define INTC_MIR_SET0 0x008c
	34	#define INTC_PENDING_IRQ0 0x0098
2e7509e5 PW	35	/* Number of IRQ state bits in each MIR register */
2e7509e5 PW	36	#define IRQ_BITS_PER_REG 32
1dbae815 TL	37
	38	/*
	39	* OMAP2 has a number of different interrupt controllers, each interrupt
	40	* controller is identified as its own "bank". Register definitions are
	41	* fairly consistent for each bank, but not all registers are implemented
	42	* for each bank.. when in doubt, consult the TRM.
	43	*/
	44	static struct omap_irq_bank {
e8a91c95	45	void __iomem *base_reg;
1dbae815 TL	46	unsigned int nr_irqs;
	47	} __attribute__ ((aligned(4))) irq_banks[] = {
	48	{
	49	/* MPU INTC */
1dbae815	50	.nr_irqs = 96,
646e3ed1	51	},
1dbae815 TL	52	};
1dbae815 TL	53
0addd61b RN	54	/* Structure to save interrupt controller context */
	55	struct omap3_intc_regs {
	56	u32 sysconfig;
	57	u32 protection;
	58	u32 idle;
	59	u32 threshold;
	60	u32 ilr[INTCPS_NR_IRQS];
	61	u32 mir[INTCPS_NR_MIR_REGS];
	62	};
	63
	64	static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
	65
2e7509e5 PW	66	/* INTC bank register get/set */
	67
	68	static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
	69	{
	70	__raw_writel(val, bank->base_reg + reg);
	71	}
	72
	73	static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
	74	{
	75	return __raw_readl(bank->base_reg + reg);
	76	}
	77
6ccc4c0d TL	78	static int previous_irq;
	79
	80	/*
	81	* On 34xx we can get occasional spurious interrupts if the ack from
	82	* an interrupt handler does not get posted before we unmask. Warn about
	83	* the interrupt handlers that need to flush posted writes.
	84	*/
	85	static int omap_check_spurious(unsigned int irq)
	86	{
	87	u32 sir, spurious;
	88
	89	sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
846c29f1	90	spurious = sir >> 7;
6ccc4c0d	91
846c29f1	92	if (spurious) {
6ccc4c0d TL	93	printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
	94	"posted write for irq %i\n",
	95	irq, sir, previous_irq);
	96	return spurious;
	97	}
	98
	99	return 0;
	100	}
	101
1dbae815 TL	102	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
	103	static void omap_ack_irq(unsigned int irq)
	104	{
2e7509e5	105	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
1dbae815 TL	106	}
	107
	108	static void omap_mask_irq(unsigned int irq)
	109	{
2e7509e5	110	int offset = irq & (~(IRQ_BITS_PER_REG - 1));
1dbae815	111
6ccc4c0d TL	112	if (cpu_is_omap34xx()) {
	113	int spurious = 0;
	114
	115	/*
	116	* INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
	117	* it is the highest irq number?
	118	*/
	119	if (irq == INT_34XX_GPT12_IRQ)
	120	spurious = omap_check_spurious(irq);
	121
	122	if (!spurious)
	123	previous_irq = irq;
	124	}
	125
2e7509e5	126	irq &= (IRQ_BITS_PER_REG - 1);
1dbae815	127
2e7509e5	128	intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
1dbae815 TL	129	}
	130
	131	static void omap_unmask_irq(unsigned int irq)
	132	{
2e7509e5	133	int offset = irq & (~(IRQ_BITS_PER_REG - 1));
1dbae815	134
2e7509e5	135	irq &= (IRQ_BITS_PER_REG - 1);
1dbae815	136
2e7509e5	137	intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
1dbae815 TL	138	}
	139
	140	static void omap_mask_ack_irq(unsigned int irq)
	141	{
	142	omap_mask_irq(irq);
	143	omap_ack_irq(irq);
	144	}
	145
38c677cb DB	146	static struct irq_chip omap_irq_chip = {
38c677cb DB	147	.name = "INTC",
1dbae815 TL	148	.ack = omap_mask_ack_irq,
	149	.mask = omap_mask_irq,
	150	.unmask = omap_unmask_irq,
	151	};
	152
	153	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	154	{
	155	unsigned long tmp;
	156
2e7509e5	157	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
e8a91c95	158	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
1dbae815 TL	159	"(revision %ld.%ld) with %d interrupts\n",
	160	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
	161
2e7509e5	162	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
1dbae815	163	tmp \|= 1 << 1; /* soft reset */
2e7509e5	164	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
1dbae815	165
2e7509e5	166	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
1dbae815	167	/* Wait for reset to complete */;
375e12ab JY	168
375e12ab JY	169	/* Enable autoidle */
2e7509e5	170	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
1dbae815 TL	171	}
1dbae815 TL	172
94434535 JH	173	int omap_irq_pending(void)
	174	{
	175	int i;
	176
	177	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	178	struct omap_irq_bank *bank = irq_banks + i;
	179	int irq;
	180
	181	for (irq = 0; irq < bank->nr_irqs; irq += 32)
	182	if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
	183	((irq >> 5) << 5)))
	184	return 1;
	185	}
	186	return 0;
	187	}
	188
1dbae815 TL	189	void __init omap_init_irq(void)
1dbae815 TL	190	{
4b1135a2	191	unsigned long nr_of_irqs = 0;
1dbae815 TL	192	unsigned int nr_banks = 0;
	193	int i;
	194
	195	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
74005a2b	196	unsigned long base = 0;
1dbae815 TL	197	struct omap_irq_bank *bank = irq_banks + i;
1dbae815 TL	198
646e3ed1	199	if (cpu_is_omap24xx())
1b26fe86	200	base = OMAP24XX_IC_BASE;
cc26b3b0	201	else if (cpu_is_omap34xx())
1b26fe86 TL	202	base = OMAP34XX_IC_BASE;
1b26fe86 TL	203
74005a2b KH	204	BUG_ON(!base);
74005a2b KH	205
1b26fe86 TL	206	/* Static mapping, never released */
	207	bank->base_reg = ioremap(base, SZ_4K);
	208	if (!bank->base_reg) {
	209	printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
	210	continue;
	211	}
2e7509e5	212
1dbae815 TL	213	omap_irq_bank_init_one(bank);
1dbae815 TL	214
4b1135a2	215	nr_of_irqs += bank->nr_irqs;
1dbae815 TL	216	nr_banks++;
	217	}
	218
	219	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
4b1135a2	220	nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
1dbae815	221
4b1135a2	222	for (i = 0; i < nr_of_irqs; i++) {
1dbae815	223	set_irq_chip(i, &omap_irq_chip);
10dd5ce2	224	set_irq_handler(i, handle_level_irq);
1dbae815 TL	225	set_irq_flags(i, IRQF_VALID);
	226	}
	227	}
	228
0addd61b RN	229	#ifdef CONFIG_ARCH_OMAP3
	230	void omap_intc_save_context(void)
	231	{
	232	int ind = 0, i = 0;
	233	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	234	struct omap_irq_bank *bank = irq_banks + ind;
	235	intc_context[ind].sysconfig =
	236	intc_bank_read_reg(bank, INTC_SYSCONFIG);
	237	intc_context[ind].protection =
	238	intc_bank_read_reg(bank, INTC_PROTECTION);
	239	intc_context[ind].idle =
	240	intc_bank_read_reg(bank, INTC_IDLE);
	241	intc_context[ind].threshold =
	242	intc_bank_read_reg(bank, INTC_THRESHOLD);
	243	for (i = 0; i < INTCPS_NR_IRQS; i++)
	244	intc_context[ind].ilr[i] =
2329e7cc	245	intc_bank_read_reg(bank, (0x100 + 0x4*i));
0addd61b RN	246	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	247	intc_context[ind].mir[i] =
	248	intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
	249	(0x20 * i));
	250	}
	251	}
	252
	253	void omap_intc_restore_context(void)
	254	{
	255	int ind = 0, i = 0;
	256
	257	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	258	struct omap_irq_bank *bank = irq_banks + ind;
	259	intc_bank_write_reg(intc_context[ind].sysconfig,
	260	bank, INTC_SYSCONFIG);
	261	intc_bank_write_reg(intc_context[ind].sysconfig,
	262	bank, INTC_SYSCONFIG);
	263	intc_bank_write_reg(intc_context[ind].protection,
	264	bank, INTC_PROTECTION);
	265	intc_bank_write_reg(intc_context[ind].idle,
	266	bank, INTC_IDLE);
	267	intc_bank_write_reg(intc_context[ind].threshold,
	268	bank, INTC_THRESHOLD);
	269	for (i = 0; i < INTCPS_NR_IRQS; i++)
	270	intc_bank_write_reg(intc_context[ind].ilr[i],
2329e7cc	271	bank, (0x100 + 0x4*i));
0addd61b RN	272	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	273	intc_bank_write_reg(intc_context[ind].mir[i],
	274	&irq_banks[0], INTC_MIR0 + (0x20 * i));
	275	}
	276	/* MIRs are saved and restore with other PRCM registers */
	277	}
2bbe3af3 TK	278
	279	void omap3_intc_suspend(void)
	280	{
	281	/* A pending interrupt would prevent OMAP from entering suspend */
	282	omap_ack_irq(0);
	283	}
f18cc2ff TK	284
	285	void omap3_intc_prepare_idle(void)
	286	{
	287	/* Disable autoidle as it can stall interrupt controller */
	288	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
	289	}
	290
	291	void omap3_intc_resume_idle(void)
	292	{
	293	/* Re-enable autoidle */
	294	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
	295	}
0addd61b	296	#endif /* CONFIG_ARCH_OMAP3 */