[net-next-2.6.git] / arch / arm / mach-omap2 / hsmmc.c

/*
 * linux/arch/arm/mach-omap2/hsmmc.c
 *
 * Copyright (C) 2007-2008 Texas Instruments
 * Copyright (C) 2008 Nokia Corporation
 * Author: Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <plat/control.h>
#include <plat/mmc.h>
#include <plat/omap-pm.h>

#include "hsmmc.h"

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static u16 control_pbias_offset;
static u16 control_devconf1_offset;

#define HSMMC_NAME_LEN	9

static struct hsmmc_controller {
	char				name[HSMMC_NAME_LEN + 1];
} hsmmc[OMAP34XX_NR_MMC];

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

static int hsmmc_get_context_loss(struct device *dev)
{
	return omap_pm_get_dev_context_loss_count(dev);
}

#else
#define hsmmc_get_context_loss NULL
#endif

static void hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 *
	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	 * is most naturally TWL VSIM; those pins also use PBIAS.
	 *
	 * FIXME handle VMMC1A as needed ...
	 */
	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;

	/* 100ms delay required for PBIAS configuration */
	msleep(100);

	if (power_on) {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP2_PBIASLITEVMODE0;
		else
			reg |= OMAP2_PBIASLITEVMODE0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
			OMAP2_PBIASLITEVMODE0);
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void hsmmc23_before_set_reg(struct device *dev, int slot,
				   int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	if (power_on) {
		/* Only MMC2 supports a CLKIN */
		if (mmc->slots[0].internal_clock) {
			u32 reg;

			reg = omap_ctrl_readl(control_devconf1_offset);
			reg |= OMAP2_MMCSDIO2ADPCLKISEL;
			omap_ctrl_writel(reg, control_devconf1_offset);
		}
	}
}

static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;
	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
	int i;

	if (cpu_is_omap2430()) {
		control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
	} else {
		control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	}

	for (c = controllers; c->mmc; c++) {
		struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
		struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];

		if (!c->mmc || c->mmc > nr_hsmmc) {
			pr_debug("MMC%d: no such controller\n", c->mmc);
			continue;
		}
		if (mmc) {
			pr_debug("MMC%d: already configured\n", c->mmc);
			continue;
		}

		mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
			      GFP_KERNEL);
		if (!mmc) {
			pr_err("Cannot allocate memory for mmc device!\n");
			goto done;
		}

		if (c->name)
			strncpy(hc->name, c->name, HSMMC_NAME_LEN);
		else
			snprintf(hc->name, ARRAY_SIZE(hc->name),
				"mmc%islot%i", c->mmc, 1);
		mmc->slots[0].name = hc->name;
		mmc->nr_slots = 1;
		mmc->slots[0].wires = c->wires;
		mmc->slots[0].internal_clock = !c->ext_clock;
		mmc->dma_mask = 0xffffffff;

		mmc->get_context_loss_count = hsmmc_get_context_loss;

		mmc->slots[0].switch_pin = c->gpio_cd;
		mmc->slots[0].gpio_wp = c->gpio_wp;

		mmc->slots[0].remux = c->remux;

		if (c->cover_only)
			mmc->slots[0].cover = 1;

		if (c->nonremovable)
			mmc->slots[0].nonremovable = 1;

		if (c->power_saving)
			mmc->slots[0].power_saving = 1;

		if (c->no_off)
			mmc->slots[0].no_off = 1;

		/* NOTE:  MMC slots should have a Vcc regulator set up.
		 * This may be from a TWL4030-family chip, another
		 * controllable regulator, or a fixed supply.
		 *
		 * temporary HACK: ocr_mask instead of fixed supply
		 */
		mmc->slots[0].ocr_mask = c->ocr_mask;

		switch (c->mmc) {
		case 1:
			/* on-chip level shifting via PBIAS0/PBIAS1 */
			mmc->slots[0].before_set_reg = hsmmc1_before_set_reg;
			mmc->slots[0].after_set_reg = hsmmc1_after_set_reg;

			/* Omap3630 HSMMC1 supports only 4-bit */
			if (cpu_is_omap3630() && c->wires > 4) {
				c->wires = 4;
				mmc->slots[0].wires = c->wires;
			}
			break;
		case 2:
			if (c->ext_clock)
				c->transceiver = 1;
			if (c->transceiver && c->wires > 4)
				c->wires = 4;
			/* FALLTHROUGH */
		case 3:
			/* off-chip level shifting, or none */
			mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
			mmc->slots[0].after_set_reg = NULL;
			break;
		default:
			pr_err("MMC%d configuration not supported!\n", c->mmc);
			kfree(mmc);
			continue;
		}
		hsmmc_data[c->mmc - 1] = mmc;
	}

	omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);

	/* pass the device nodes back to board setup code */
	for (c = controllers; c->mmc; c++) {
		struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];

		if (!c->mmc || c->mmc > nr_hsmmc)
			continue;
		c->dev = mmc->dev;
	}

done:
	for (i = 0; i < nr_hsmmc; i++)
		kfree(hsmmc_data[i]);
}

#endif
Commit	Line	Data
90c62bf0	1	/*
d02a900b	2	* linux/arch/arm/mach-omap2/hsmmc.c
90c62bf0 TL	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments
	5	* Copyright (C) 2008 Nokia Corporation
	6	* Author: Texas Instruments
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
db0fefc5 AH	12	#include <linux/kernel.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
90c62bf0	15	#include <linux/delay.h>
90c62bf0	16	#include <mach/hardware.h>
ce491cf8 TL	17	#include <plat/control.h>
ce491cf8 TL	18	#include <plat/mmc.h>
e3df0fb4	19	#include <plat/omap-pm.h>
90c62bf0	20
d02a900b	21	#include "hsmmc.h"
90c62bf0	22
db0fefc5	23	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
90c62bf0 TL	24
	25	static u16 control_pbias_offset;
	26	static u16 control_devconf1_offset;
	27
	28	#define HSMMC_NAME_LEN 9
	29
68ff0423	30	static struct hsmmc_controller {
b583f26d DB	31	char name[HSMMC_NAME_LEN + 1];
b583f26d DB	32	} hsmmc[OMAP34XX_NR_MMC];
90c62bf0	33
1887bde3 DK	34	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
1887bde3 DK	35
68ff0423	36	static int hsmmc_get_context_loss(struct device *dev)
1887bde3	37	{
e3df0fb4	38	return omap_pm_get_dev_context_loss_count(dev);
1887bde3 DK	39	}
	40
	41	#else
68ff0423	42	#define hsmmc_get_context_loss NULL
1887bde3 DK	43	#endif
1887bde3 DK	44
db0fefc5 AH	45	static void hsmmc1_before_set_reg(struct device *dev, int slot,
db0fefc5 AH	46	int power_on, int vdd)
90c62bf0	47	{
555d503f	48	u32 reg, prog_io;
90c62bf0 TL	49	struct omap_mmc_platform_data *mmc = dev->platform_data;
90c62bf0 TL	50
ce6f0016 AH	51	if (mmc->slots[0].remux)
	52	mmc->slots[0].remux(dev, slot, power_on);
	53
0329c377 DB	54	/*
0329c377 DB	55	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
b583f26d	56	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
0329c377 DB	57	* 1.8V and 3.0V modes, controlled by the PBIAS register.
	58	*
	59	* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	60	* is most naturally TWL VSIM; those pins also use PBIAS.
b583f26d DB	61	*
b583f26d DB	62	* FIXME handle VMMC1A as needed ...
0329c377	63	*/
90c62bf0 TL	64	if (power_on) {
	65	if (cpu_is_omap2430()) {
	66	reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
	67	if ((1 << vdd) >= MMC_VDD_30_31)
	68	reg \|= OMAP243X_MMC1_ACTIVE_OVERWRITE;
	69	else
	70	reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
	71	omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
	72	}
	73
	74	if (mmc->slots[0].internal_clock) {
	75	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	76	reg \|= OMAP2_MMCSDIO1ADPCLKISEL;
	77	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
	78	}
	79
	80	reg = omap_ctrl_readl(control_pbias_offset);
555d503f M	81	if (cpu_is_omap3630()) {
	82	/* Set MMC I/O to 52Mhz */
	83	prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	84	prog_io \|= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
	85	omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
	86	} else {
	87	reg \|= OMAP2_PBIASSPEEDCTRL0;
	88	}
90c62bf0 TL	89	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
90c62bf0 TL	90	omap_ctrl_writel(reg, control_pbias_offset);
db0fefc5 AH	91	} else {
	92	reg = omap_ctrl_readl(control_pbias_offset);
	93	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
	94	omap_ctrl_writel(reg, control_pbias_offset);
	95	}
	96	}
	97
	98	static void hsmmc1_after_set_reg(struct device *dev, int slot,
	99	int power_on, int vdd)
	100	{
	101	u32 reg;
90c62bf0	102
db0fefc5 AH	103	/* 100ms delay required for PBIAS configuration */
db0fefc5 AH	104	msleep(100);
90c62bf0	105
db0fefc5	106	if (power_on) {
90c62bf0 TL	107	reg = omap_ctrl_readl(control_pbias_offset);
	108	reg \|= (OMAP2_PBIASLITEPWRDNZ0 \| OMAP2_PBIASSPEEDCTRL0);
	109	if ((1 << vdd) <= MMC_VDD_165_195)
	110	reg &= ~OMAP2_PBIASLITEVMODE0;
	111	else
	112	reg \|= OMAP2_PBIASLITEVMODE0;
	113	omap_ctrl_writel(reg, control_pbias_offset);
	114	} else {
90c62bf0 TL	115	reg = omap_ctrl_readl(control_pbias_offset);
	116	reg \|= (OMAP2_PBIASSPEEDCTRL0 \| OMAP2_PBIASLITEPWRDNZ0 \|
	117	OMAP2_PBIASLITEVMODE0);
	118	omap_ctrl_writel(reg, control_pbias_offset);
	119	}
90c62bf0 TL	120	}
90c62bf0 TL	121
db0fefc5 AH	122	static void hsmmc23_before_set_reg(struct device *dev, int slot,
db0fefc5 AH	123	int power_on, int vdd)
90c62bf0	124	{
90c62bf0	125	struct omap_mmc_platform_data *mmc = dev->platform_data;
b583f26d	126
ce6f0016 AH	127	if (mmc->slots[0].remux)
	128	mmc->slots[0].remux(dev, slot, power_on);
	129
90c62bf0	130	if (power_on) {
db0fefc5	131	/* Only MMC2 supports a CLKIN */
90c62bf0 TL	132	if (mmc->slots[0].internal_clock) {
	133	u32 reg;
	134
	135	reg = omap_ctrl_readl(control_devconf1_offset);
	136	reg \|= OMAP2_MMCSDIO2ADPCLKISEL;
	137	omap_ctrl_writel(reg, control_devconf1_offset);
	138	}
9b7c18e0	139	}
9b7c18e0 AH	140	}
9b7c18e0 AH	141
90c62bf0 TL	142	static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
90c62bf0 TL	143
68ff0423	144	void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
90c62bf0	145	{
68ff0423	146	struct omap2_hsmmc_info *c;
90c62bf0	147	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
a6c7fdd2	148	int i;
90c62bf0 TL	149
	150	if (cpu_is_omap2430()) {
	151	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
	152	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
90c62bf0 TL	153	} else {
	154	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
	155	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	156	}
	157
	158	for (c = controllers; c->mmc; c++) {
68ff0423	159	struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
90c62bf0 TL	160	struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
	161
	162	if (!c->mmc \|\| c->mmc > nr_hsmmc) {
	163	pr_debug("MMC%d: no such controller\n", c->mmc);
	164	continue;
	165	}
	166	if (mmc) {
	167	pr_debug("MMC%d: already configured\n", c->mmc);
	168	continue;
	169	}
	170
68ff0423 AH	171	mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
68ff0423 AH	172	GFP_KERNEL);
90c62bf0 TL	173	if (!mmc) {
90c62bf0 TL	174	pr_err("Cannot allocate memory for mmc device!\n");
a6c7fdd2	175	goto done;
90c62bf0 TL	176	}
90c62bf0 TL	177
e51151a5	178	if (c->name)
68ff0423	179	strncpy(hc->name, c->name, HSMMC_NAME_LEN);
e51151a5	180	else
68ff0423	181	snprintf(hc->name, ARRAY_SIZE(hc->name),
e51151a5	182	"mmc%islot%i", c->mmc, 1);
68ff0423	183	mmc->slots[0].name = hc->name;
90c62bf0	184	mmc->nr_slots = 1;
90c62bf0 TL	185	mmc->slots[0].wires = c->wires;
	186	mmc->slots[0].internal_clock = !c->ext_clock;
	187	mmc->dma_mask = 0xffffffff;
90c62bf0	188
68ff0423	189	mmc->get_context_loss_count = hsmmc_get_context_loss;
1887bde3	190
db0fefc5 AH	191	mmc->slots[0].switch_pin = c->gpio_cd;
db0fefc5 AH	192	mmc->slots[0].gpio_wp = c->gpio_wp;
90c62bf0	193
ce6f0016 AH	194	mmc->slots[0].remux = c->remux;
ce6f0016 AH	195
db0fefc5 AH	196	if (c->cover_only)
db0fefc5 AH	197	mmc->slots[0].cover = 1;
90c62bf0	198
23d99bb9 AH	199	if (c->nonremovable)
	200	mmc->slots[0].nonremovable = 1;
	201
dd498eff DK	202	if (c->power_saving)
	203	mmc->slots[0].power_saving = 1;
	204
1df58db8 AH	205	if (c->no_off)
	206	mmc->slots[0].no_off = 1;
	207
b583f26d DB	208	/* NOTE: MMC slots should have a Vcc regulator set up.
	209	* This may be from a TWL4030-family chip, another
	210	* controllable regulator, or a fixed supply.
	211	*
	212	* temporary HACK: ocr_mask instead of fixed supply
90c62bf0	213	*/
b583f26d	214	mmc->slots[0].ocr_mask = c->ocr_mask;
90c62bf0 TL	215
	216	switch (c->mmc) {
	217	case 1:
b583f26d	218	/* on-chip level shifting via PBIAS0/PBIAS1 */
db0fefc5 AH	219	mmc->slots[0].before_set_reg = hsmmc1_before_set_reg;
db0fefc5 AH	220	mmc->slots[0].after_set_reg = hsmmc1_after_set_reg;
41fd03d6 M	221
	222	/* Omap3630 HSMMC1 supports only 4-bit */
	223	if (cpu_is_omap3630() && c->wires > 4) {
	224	c->wires = 4;
	225	mmc->slots[0].wires = c->wires;
	226	}
90c62bf0 TL	227	break;
90c62bf0 TL	228	case 2:
b583f26d DB	229	if (c->ext_clock)
	230	c->transceiver = 1;
	231	if (c->transceiver && c->wires > 4)
	232	c->wires = 4;
	233	/* FALLTHROUGH */
07d83cc9	234	case 3:
b583f26d	235	/* off-chip level shifting, or none */
db0fefc5 AH	236	mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
db0fefc5 AH	237	mmc->slots[0].after_set_reg = NULL;
07d83cc9	238	break;
90c62bf0 TL	239	default:
90c62bf0 TL	240	pr_err("MMC%d configuration not supported!\n", c->mmc);
07d83cc9	241	kfree(mmc);
90c62bf0 TL	242	continue;
	243	}
	244	hsmmc_data[c->mmc - 1] = mmc;
	245	}
	246
	247	omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
01971f65 DB	248
	249	/* pass the device nodes back to board setup code */
	250	for (c = controllers; c->mmc; c++) {
	251	struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
	252
	253	if (!c->mmc \|\| c->mmc > nr_hsmmc)
	254	continue;
	255	c->dev = mmc->dev;
	256	}
a6c7fdd2 AK	257
	258	done:
	259	for (i = 0; i < nr_hsmmc; i++)
	260	kfree(hsmmc_data[i]);
90c62bf0 TL	261	}
	262
	263	#endif