[net-next-2.6.git] / arch / arm / mach-omap2 / gpmc.c

/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/gpmc.h>

#undef DEBUG

#define GPMC_BASE		0x6800a000
#define GPMC_REVISION		0x00
#define GPMC_SYSCONFIG		0x10
#define GPMC_SYSSTATUS		0x14
#define GPMC_IRQSTATUS		0x18
#define GPMC_IRQENABLE		0x1c
#define GPMC_TIMEOUT_CONTROL	0x40
#define GPMC_ERR_ADDRESS	0x44
#define GPMC_ERR_TYPE		0x48
#define GPMC_CONFIG		0x50
#define GPMC_STATUS		0x54
#define GPMC_PREFETCH_CONFIG1	0x1e0
#define GPMC_PREFETCH_CONFIG2	0x1e4
#define GPMC_PREFETCH_CONTROL	0x1e8
#define GPMC_PREFETCH_STATUS	0x1f0
#define GPMC_ECC_CONFIG		0x1f4
#define GPMC_ECC_CONTROL	0x1f8
#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_CS0		0x60
#define GPMC_CS_SIZE		0x30

#define GPMC_CS_NUM		8
#define GPMC_MEM_START		0x00000000
#define GPMC_MEM_END		0x3FFFFFFF
#define BOOT_ROM_SPACE		0x100000	/* 1MB */

#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
#define GPMC_SECTION_SHIFT	28		/* 128 MB */

static struct resource	gpmc_mem_root;
static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
static spinlock_t	gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
static unsigned		gpmc_cs_map;

static void __iomem *gpmc_base =
	(void __iomem *) IO_ADDRESS(GPMC_BASE);
static void __iomem *gpmc_cs_base =
	(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;

static struct clk *gpmc_l3_clk;

static void gpmc_write_reg(int idx, u32 val)
{
	__raw_writel(val, gpmc_base + idx);
}

static u32 gpmc_read_reg(int idx)
{
	return __raw_readl(gpmc_base + idx);
}

void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	__raw_writel(val, reg_addr);
}

u32 gpmc_cs_read_reg(int cs, int idx)
{
	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
}

/* TODO: Add support for gpmc_fck to clock framework and use it */
static unsigned long gpmc_get_fclk_period(void)
{
	/* In picoseconds */
	return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
}

unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time)
#endif
{
	u32 l;
	int ticks, mask, nr_bits;

	if (time == 0)
		ticks = 0;
	else
		ticks = gpmc_ns_to_ticks(time);
	nr_bits = end_bit - st_bit + 1;
	if (ticks >= 1 << nr_bits)
		return -1;

	mask = (1 << nr_bits) - 1;
	l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
	printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
	       (l >> st_bit) & mask);
#endif
	l &= ~(mask << st_bit);
	l |= ticks << st_bit;
	gpmc_cs_write_reg(cs, reg, l);

	return 0;
}

#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
			t->field, #field) < 0)			\
		return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
		return -1
#endif

int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
	int div;
	u32 l;

	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	div = l / gpmc_get_fclk_period();
	if (div > 4)
		return -1;
	if (div < 0)
		div = 1;

	return div;
}

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
	int div;
	u32 l;

	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	if (div < 0)
		return -1;

	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

#ifdef DEBUG
	printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
	       cs, gpmc_get_fclk_period(), div);
#endif

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	l &= ~0x03;
	l |= (div - 1);

	return 0;
}

static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
{
	u32 l;
	u32 mask;

	mask = (1 << GPMC_SECTION_SHIFT) - size;
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~0x3f;
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	l &= ~(0x0f << 8);
	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	l |= 1 << 6;		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_disable_mem(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~(1 << 6);		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
	u32 l;
	u32 mask;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	mask = (l >> 8) & 0x0f;
	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}

static int gpmc_cs_mem_enabled(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	return l & (1 << 6);
}

static void gpmc_cs_set_reserved(int cs, int reserved)
{
	gpmc_cs_map &= ~(1 << cs);
	gpmc_cs_map |= (reserved ? 1 : 0) << cs;
}

static int gpmc_cs_reserved(int cs)
{
	return gpmc_cs_map & (1 << cs);
}

static unsigned long gpmc_mem_align(unsigned long size)
{
	int order;

	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	order = GPMC_CHUNK_SHIFT - 1;
	do {
		size >>= 1;
		order++;
	} while (size);
	size = 1 << order;
	return size;
}

static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
	struct resource	*res = &gpmc_cs_mem[cs];
	int r;

	size = gpmc_mem_align(size);
	spin_lock(&gpmc_mem_lock);
	res->start = base;
	res->end = base + size - 1;
	r = request_resource(&gpmc_mem_root, res);
	spin_unlock(&gpmc_mem_lock);

	return r;
}

int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
	struct resource *res = &gpmc_cs_mem[cs];
	int r = -1;

	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	size = gpmc_mem_align(size);
	if (size > (1 << GPMC_SECTION_SHIFT))
		return -ENOMEM;

	spin_lock(&gpmc_mem_lock);
	if (gpmc_cs_reserved(cs)) {
		r = -EBUSY;
		goto out;
	}
	if (gpmc_cs_mem_enabled(cs))
		r = adjust_resource(res, res->start & ~(size - 1), size);
	if (r < 0)
		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
				      size, NULL, NULL);
	if (r < 0)
		goto out;

	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	*base = res->start;
	gpmc_cs_set_reserved(cs, 1);
out:
	spin_unlock(&gpmc_mem_lock);
	return r;
}

void gpmc_cs_free(int cs)
{
	spin_lock(&gpmc_mem_lock);
	if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
		BUG();
		spin_unlock(&gpmc_mem_lock);
		return;
	}
	gpmc_cs_disable_mem(cs);
	release_resource(&gpmc_cs_mem[cs]);
	gpmc_cs_set_reserved(cs, 0);
	spin_unlock(&gpmc_mem_lock);
}

void __init gpmc_mem_init(void)
{
	int cs;
	unsigned long boot_rom_space = 0;

	/* never allocate the first page, to facilitate bug detection;
	 * even if we didn't boot from ROM.
	 */
	boot_rom_space = BOOT_ROM_SPACE;
	/* In apollon the CS0 is mapped as 0x0000 0000 */
	if (machine_is_omap_apollon())
		boot_rom_space = 0;
	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	gpmc_mem_root.end = GPMC_MEM_END;

	/* Reserve all regions that has been set up by bootloader */
	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
		u32 base, size;

		if (!gpmc_cs_mem_enabled(cs))
			continue;
		gpmc_cs_get_memconf(cs, &base, &size);
		if (gpmc_cs_insert_mem(cs, base, size) < 0)
			BUG();
	}
}

void __init gpmc_init(void)
{
	u32 l;

	gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
	BUG_ON(IS_ERR(gpmc_l3_clk));

	l = gpmc_read_reg(GPMC_REVISION);
	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	/* Set smart idle mode and automatic L3 clock gating */
	l = gpmc_read_reg(GPMC_SYSCONFIG);
	l &= 0x03 << 3;
	l |= (0x02 << 3) | (1 << 0);
	gpmc_write_reg(GPMC_SYSCONFIG, l);

	gpmc_mem_init();
}
Commit	Line	Data
4bbbc1ad JY	1	/*
	2	* GPMC support functions
	3	*
	4	* Copyright (C) 2005-2006 Nokia Corporation
	5	*
	6	* Author: Juha Yrjola
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
f37e4580 ID	16	#include <linux/ioport.h>
f37e4580 ID	17	#include <linux/spinlock.h>
4bbbc1ad JY	18
4bbbc1ad JY	19	#include <asm/io.h>
7f245162	20	#include <asm/mach-types.h>
4bbbc1ad JY	21	#include <asm/arch/gpmc.h>
	22
	23	#undef DEBUG
	24
	25	#define GPMC_BASE 0x6800a000
	26	#define GPMC_REVISION 0x00
	27	#define GPMC_SYSCONFIG 0x10
	28	#define GPMC_SYSSTATUS 0x14
	29	#define GPMC_IRQSTATUS 0x18
	30	#define GPMC_IRQENABLE 0x1c
	31	#define GPMC_TIMEOUT_CONTROL 0x40
	32	#define GPMC_ERR_ADDRESS 0x44
	33	#define GPMC_ERR_TYPE 0x48
	34	#define GPMC_CONFIG 0x50
	35	#define GPMC_STATUS 0x54
	36	#define GPMC_PREFETCH_CONFIG1 0x1e0
	37	#define GPMC_PREFETCH_CONFIG2 0x1e4
	38	#define GPMC_PREFETCH_CONTROL 0x1e8
	39	#define GPMC_PREFETCH_STATUS 0x1f0
	40	#define GPMC_ECC_CONFIG 0x1f4
	41	#define GPMC_ECC_CONTROL 0x1f8
	42	#define GPMC_ECC_SIZE_CONFIG 0x1fc
	43
	44	#define GPMC_CS0 0x60
	45	#define GPMC_CS_SIZE 0x30
	46
f37e4580 ID	47	#define GPMC_CS_NUM 8
	48	#define GPMC_MEM_START 0x00000000
	49	#define GPMC_MEM_END 0x3FFFFFFF
	50	#define BOOT_ROM_SPACE 0x100000 /* 1MB */
	51
	52	#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
	53	#define GPMC_SECTION_SHIFT 28 /* 128 MB */
	54
	55	static struct resource gpmc_mem_root;
	56	static struct resource gpmc_cs_mem[GPMC_CS_NUM];
	57	static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
	58	static unsigned gpmc_cs_map;
	59
4bbbc1ad JY	60	static void __iomem *gpmc_base =
	61	(void __iomem *) IO_ADDRESS(GPMC_BASE);
	62	static void __iomem *gpmc_cs_base =
	63	(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
	64
	65	static struct clk *gpmc_l3_clk;
	66
	67	static void gpmc_write_reg(int idx, u32 val)
	68	{
	69	__raw_writel(val, gpmc_base + idx);
	70	}
	71
	72	static u32 gpmc_read_reg(int idx)
	73	{
	74	return __raw_readl(gpmc_base + idx);
	75	}
	76
	77	void gpmc_cs_write_reg(int cs, int idx, u32 val)
	78	{
	79	void __iomem *reg_addr;
	80
	81	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	82	__raw_writel(val, reg_addr);
	83	}
	84
	85	u32 gpmc_cs_read_reg(int cs, int idx)
	86	{
	87	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
	88	}
	89
	90	/* TODO: Add support for gpmc_fck to clock framework and use it */
	91	static unsigned long gpmc_get_fclk_period(void)
	92	{
	93	/* In picoseconds */
	94	return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
	95	}
	96
	97	unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
	98	{
	99	unsigned long tick_ps;
	100
	101	/* Calculate in picosecs to yield more exact results */
	102	tick_ps = gpmc_get_fclk_period();
	103
	104	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
	105	}
	106
	107	#ifdef DEBUG
	108	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468	109	int time, const char *name)
4bbbc1ad JY	110	#else
	111	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
	112	int time)
	113	#endif
	114	{
	115	u32 l;
	116	int ticks, mask, nr_bits;
	117
	118	if (time == 0)
	119	ticks = 0;
	120	else
	121	ticks = gpmc_ns_to_ticks(time);
	122	nr_bits = end_bit - st_bit + 1;
	123	if (ticks >= 1 << nr_bits)
	124	return -1;
	125
	126	mask = (1 << nr_bits) - 1;
	127	l = gpmc_cs_read_reg(cs, reg);
	128	#ifdef DEBUG
	129	printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
2aab6468	130	cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
4bbbc1ad JY	131	(l >> st_bit) & mask);
	132	#endif
	133	l &= ~(mask << st_bit);
	134	l \|= ticks << st_bit;
	135	gpmc_cs_write_reg(cs, reg, l);
	136
	137	return 0;
	138	}
	139
	140	#ifdef DEBUG
	141	#define GPMC_SET_ONE(reg, st, end, field) \
	142	if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
	143	t->field, #field) < 0) \
	144	return -1
	145	#else
	146	#define GPMC_SET_ONE(reg, st, end, field) \
	147	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
	148	return -1
	149	#endif
	150
	151	int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
	152	{
	153	int div;
	154	u32 l;
	155
	156	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	157	div = l / gpmc_get_fclk_period();
	158	if (div > 4)
	159	return -1;
	160	if (div < 0)
	161	div = 1;
	162
	163	return div;
	164	}
	165
	166	int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
	167	{
	168	int div;
	169	u32 l;
	170
	171	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	172	if (div < 0)
	173	return -1;
	174
	175	GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
	176	GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
	177	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
	178
	179	GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
	180	GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
	181	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
	182
	183	GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
	184	GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
	185	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	186	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
	187
	188	GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
	189	GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
	190	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
	191
	192	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
	193
	194	#ifdef DEBUG
2aab6468 JY	195	printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
2aab6468 JY	196	cs, gpmc_get_fclk_period(), div);
4bbbc1ad JY	197	#endif
	198
	199	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	200	l &= ~0x03;
	201	l \|= (div - 1);
	202
	203	return 0;
	204	}
	205
f37e4580 ID	206	static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
	207	{
	208	u32 l;
	209	u32 mask;
	210
	211	mask = (1 << GPMC_SECTION_SHIFT) - size;
	212	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	213	l &= ~0x3f;
	214	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	215	l &= ~(0x0f << 8);
	216	l \|= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	217	l \|= 1 << 6; /* CSVALID */
	218	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	219	}
	220
	221	static void gpmc_cs_disable_mem(int cs)
	222	{
	223	u32 l;
	224
	225	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	226	l &= ~(1 << 6); /* CSVALID */
	227	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	228	}
	229
	230	static void gpmc_cs_get_memconf(int cs, u32 base, u32 size)
	231	{
	232	u32 l;
	233	u32 mask;
	234
	235	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	236	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	237	mask = (l >> 8) & 0x0f;
	238	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
	239	}
	240
	241	static int gpmc_cs_mem_enabled(int cs)
	242	{
	243	u32 l;
	244
	245	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	246	return l & (1 << 6);
	247	}
	248
	249	static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad	250	{
f37e4580 ID	251	gpmc_cs_map &= ~(1 << cs);
	252	gpmc_cs_map \|= (reserved ? 1 : 0) << cs;
	253	}
	254
	255	static int gpmc_cs_reserved(int cs)
	256	{
	257	return gpmc_cs_map & (1 << cs);
	258	}
	259
	260	static unsigned long gpmc_mem_align(unsigned long size)
	261	{
	262	int order;
	263
	264	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	265	order = GPMC_CHUNK_SHIFT - 1;
	266	do {
	267	size >>= 1;
	268	order++;
	269	} while (size);
	270	size = 1 << order;
	271	return size;
	272	}
	273
	274	static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
	275	{
	276	struct resource *res = &gpmc_cs_mem[cs];
	277	int r;
	278
	279	size = gpmc_mem_align(size);
	280	spin_lock(&gpmc_mem_lock);
	281	res->start = base;
	282	res->end = base + size - 1;
	283	r = request_resource(&gpmc_mem_root, res);
	284	spin_unlock(&gpmc_mem_lock);
	285
	286	return r;
	287	}
	288
	289	int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
	290	{
	291	struct resource *res = &gpmc_cs_mem[cs];
	292	int r = -1;
	293
	294	if (cs > GPMC_CS_NUM)
	295	return -ENODEV;
	296
	297	size = gpmc_mem_align(size);
	298	if (size > (1 << GPMC_SECTION_SHIFT))
	299	return -ENOMEM;
	300
	301	spin_lock(&gpmc_mem_lock);
	302	if (gpmc_cs_reserved(cs)) {
	303	r = -EBUSY;
	304	goto out;
	305	}
	306	if (gpmc_cs_mem_enabled(cs))
	307	r = adjust_resource(res, res->start & ~(size - 1), size);
	308	if (r < 0)
	309	r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
	310	size, NULL, NULL);
	311	if (r < 0)
	312	goto out;
	313
	314	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
315	*base = res->start;
316	gpmc_cs_set_reserved(cs, 1);
317	out:
318	spin_unlock(&gpmc_mem_lock);
319	return r;
320	}
321
322	void gpmc_cs_free(int cs)
323	{
324	spin_lock(&gpmc_mem_lock);
325	if (cs >= GPMC_CS_NUM \|\| !gpmc_cs_reserved(cs)) {
326	printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
327	BUG();
328	spin_unlock(&gpmc_mem_lock);
329	return;
330	}
331	gpmc_cs_disable_mem(cs);
332	release_resource(&gpmc_cs_mem[cs]);
333	gpmc_cs_set_reserved(cs, 0);
334	spin_unlock(&gpmc_mem_lock);
335	}
336
337	void __init gpmc_mem_init(void)
338	{
339	int cs;
340	unsigned long boot_rom_space = 0;
341
7f245162 KP	342	/* never allocate the first page, to facilitate bug detection;
	343	* even if we didn't boot from ROM.
	344	*/
	345	boot_rom_space = BOOT_ROM_SPACE;
	346	/* In apollon the CS0 is mapped as 0x0000 0000 */
	347	if (machine_is_omap_apollon())
	348	boot_rom_space = 0;
f37e4580 ID	349	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	350	gpmc_mem_root.end = GPMC_MEM_END;
	351
	352	/* Reserve all regions that has been set up by bootloader */
	353	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
	354	u32 base, size;
	355
	356	if (!gpmc_cs_mem_enabled(cs))
	357	continue;
	358	gpmc_cs_get_memconf(cs, &base, &size);
	359	if (gpmc_cs_insert_mem(cs, base, size) < 0)
	360	BUG();
	361	}
4bbbc1ad JY	362	}
	363
	364	void __init gpmc_init(void)
	365	{
	366	u32 l;
	367
	368	gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
	369	BUG_ON(IS_ERR(gpmc_l3_clk));
	370
	371	l = gpmc_read_reg(GPMC_REVISION);
	372	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	373	/* Set smart idle mode and automatic L3 clock gating */
	374	l = gpmc_read_reg(GPMC_SYSCONFIG);
	375	l &= 0x03 << 3;
	376	l \|= (0x02 << 3) \| (1 << 0);
	377	gpmc_write_reg(GPMC_SYSCONFIG, l);
f37e4580 ID	378
f37e4580 ID	379	gpmc_mem_init();
4bbbc1ad	380	}