[net-next-2.6.git] / arch / arm / mach-omap2 / gpmc.c

/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/module.h>

#include <asm/mach-types.h>
#include <mach/gpmc.h>

#include <mach/sdrc.h>

/* GPMC register offsets */
#define GPMC_REVISION		0x00
#define GPMC_SYSCONFIG		0x10
#define GPMC_SYSSTATUS		0x14
#define GPMC_IRQSTATUS		0x18
#define GPMC_IRQENABLE		0x1c
#define GPMC_TIMEOUT_CONTROL	0x40
#define GPMC_ERR_ADDRESS	0x44
#define GPMC_ERR_TYPE		0x48
#define GPMC_CONFIG		0x50
#define GPMC_STATUS		0x54
#define GPMC_PREFETCH_CONFIG1	0x1e0
#define GPMC_PREFETCH_CONFIG2	0x1e4
#define GPMC_PREFETCH_CONTROL	0x1ec
#define GPMC_PREFETCH_STATUS	0x1f0
#define GPMC_ECC_CONFIG		0x1f4
#define GPMC_ECC_CONTROL	0x1f8
#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_CS0		0x60
#define GPMC_CS_SIZE		0x30

#define GPMC_MEM_START		0x00000000
#define GPMC_MEM_END		0x3FFFFFFF
#define BOOT_ROM_SPACE		0x100000	/* 1MB */

#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
#define GPMC_SECTION_SHIFT	28		/* 128 MB */

#define PREFETCH_FIFOTHRESHOLD	(0x40 << 8)
#define CS_NUM_SHIFT		24
#define ENABLE_PREFETCH		(0x1 << 7)
#define DMA_MPU_MODE		2

static struct resource	gpmc_mem_root;
static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned		gpmc_cs_map;

static void __iomem *gpmc_base;

static struct clk *gpmc_l3_clk;

static void gpmc_write_reg(int idx, u32 val)
{
	__raw_writel(val, gpmc_base + idx);
}

static u32 gpmc_read_reg(int idx)
{
	return __raw_readl(gpmc_base + idx);
}

void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	__raw_writel(val, reg_addr);
}

u32 gpmc_cs_read_reg(int cs, int idx)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	return __raw_readl(reg_addr);
}

/* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
	unsigned long rate = clk_get_rate(gpmc_l3_clk);

	if (rate == 0) {
		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
		return 0;
	}

	rate /= 1000;
	rate = 1000000000 / rate;	/* In picoseconds */

	return rate;
}

unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

unsigned int gpmc_ticks_to_ns(unsigned int ticks)
{
	return ticks * gpmc_get_fclk_period() / 1000;
}

unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
{
	unsigned long ticks = gpmc_ns_to_ticks(time_ns);

	return ticks * gpmc_get_fclk_period() / 1000;
}

#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time)
#endif
{
	u32 l;
	int ticks, mask, nr_bits;

	if (time == 0)
		ticks = 0;
	else
		ticks = gpmc_ns_to_ticks(time);
	nr_bits = end_bit - st_bit + 1;
	if (ticks >= 1 << nr_bits) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
				cs, name, time, ticks, 1 << nr_bits);
#endif
		return -1;
	}

	mask = (1 << nr_bits) - 1;
	l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
	printk(KERN_INFO
		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
			(l >> st_bit) & mask, time);
#endif
	l &= ~(mask << st_bit);
	l |= ticks << st_bit;
	gpmc_cs_write_reg(cs, reg, l);

	return 0;
}

#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
			t->field, #field) < 0)			\
		return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
		return -1
#endif

int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
	int div;
	u32 l;

	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	div = l / gpmc_get_fclk_period();
	if (div > 4)
		return -1;
	if (div <= 0)
		div = 1;

	return div;
}

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
	int div;
	u32 l;

	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	if (div < 0)
		return -1;

	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

	if (cpu_is_omap34xx()) {
		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
	}

	/* caller is expected to have initialized CONFIG1 to cover
	 * at least sync vs async
	 */
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
				cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
		l &= ~0x03;
		l |= (div - 1);
		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	}

	return 0;
}

static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
{
	u32 l;
	u32 mask;

	mask = (1 << GPMC_SECTION_SHIFT) - size;
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~0x3f;
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	l &= ~(0x0f << 8);
	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	l |= 1 << 6;		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_disable_mem(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~(1 << 6);		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
	u32 l;
	u32 mask;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	mask = (l >> 8) & 0x0f;
	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}

static int gpmc_cs_mem_enabled(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	return l & (1 << 6);
}

int gpmc_cs_set_reserved(int cs, int reserved)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	gpmc_cs_map &= ~(1 << cs);
	gpmc_cs_map |= (reserved ? 1 : 0) << cs;

	return 0;
}

int gpmc_cs_reserved(int cs)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	return gpmc_cs_map & (1 << cs);
}

static unsigned long gpmc_mem_align(unsigned long size)
{
	int order;

	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	order = GPMC_CHUNK_SHIFT - 1;
	do {
		size >>= 1;
		order++;
	} while (size);
	size = 1 << order;
	return size;
}

static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
	struct resource	*res = &gpmc_cs_mem[cs];
	int r;

	size = gpmc_mem_align(size);
	spin_lock(&gpmc_mem_lock);
	res->start = base;
	res->end = base + size - 1;
	r = request_resource(&gpmc_mem_root, res);
	spin_unlock(&gpmc_mem_lock);

	return r;
}

int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
	struct resource *res = &gpmc_cs_mem[cs];
	int r = -1;

	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	size = gpmc_mem_align(size);
	if (size > (1 << GPMC_SECTION_SHIFT))
		return -ENOMEM;

	spin_lock(&gpmc_mem_lock);
	if (gpmc_cs_reserved(cs)) {
		r = -EBUSY;
		goto out;
	}
	if (gpmc_cs_mem_enabled(cs))
		r = adjust_resource(res, res->start & ~(size - 1), size);
	if (r < 0)
		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
				      size, NULL, NULL);
	if (r < 0)
		goto out;

	gpmc_cs_enable_mem(cs, res->start, resource_size(res));
	*base = res->start;
	gpmc_cs_set_reserved(cs, 1);
out:
	spin_unlock(&gpmc_mem_lock);
	return r;
}
EXPORT_SYMBOL(gpmc_cs_request);

void gpmc_cs_free(int cs)
{
	spin_lock(&gpmc_mem_lock);
	if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
		BUG();
		spin_unlock(&gpmc_mem_lock);
		return;
	}
	gpmc_cs_disable_mem(cs);
	release_resource(&gpmc_cs_mem[cs]);
	gpmc_cs_set_reserved(cs, 0);
	spin_unlock(&gpmc_mem_lock);
}
EXPORT_SYMBOL(gpmc_cs_free);

/**
 * gpmc_prefetch_enable - configures and starts prefetch transfer
 * @cs: nand cs (chip select) number
 * @dma_mode: dma mode enable (1) or disable (0)
 * @u32_count: number of bytes to be transferred
 * @is_write: prefetch read(0) or write post(1) mode
 */
int gpmc_prefetch_enable(int cs, int dma_mode,
				unsigned int u32_count, int is_write)
{
	uint32_t prefetch_config1;

	if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
		/* Set the amount of bytes to be prefetched */
		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);

		/* Set dma/mpu mode, the prefetch read / post write and
		 * enable the engine. Set which cs is has requested for.
		 */
		prefetch_config1 = ((cs << CS_NUM_SHIFT) |
					PREFETCH_FIFOTHRESHOLD |
					ENABLE_PREFETCH |
					(dma_mode << DMA_MPU_MODE) |
					(0x1 & is_write));
		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
	} else {
		return -EBUSY;
	}
	/*  Start the prefetch engine */
	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);

	return 0;
}
EXPORT_SYMBOL(gpmc_prefetch_enable);

/**
 * gpmc_prefetch_reset - disables and stops the prefetch engine
 */
void gpmc_prefetch_reset(void)
{
	/* Stop the PFPW engine */
	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);

	/* Reset/disable the PFPW engine */
	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
}
EXPORT_SYMBOL(gpmc_prefetch_reset);

/**
 * gpmc_prefetch_status - reads prefetch status of engine
 */
int  gpmc_prefetch_status(void)
{
	return gpmc_read_reg(GPMC_PREFETCH_STATUS);
}
EXPORT_SYMBOL(gpmc_prefetch_status);

static void __init gpmc_mem_init(void)
{
	int cs;
	unsigned long boot_rom_space = 0;

	/* never allocate the first page, to facilitate bug detection;
	 * even if we didn't boot from ROM.
	 */
	boot_rom_space = BOOT_ROM_SPACE;
	/* In apollon the CS0 is mapped as 0x0000 0000 */
	if (machine_is_omap_apollon())
		boot_rom_space = 0;
	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	gpmc_mem_root.end = GPMC_MEM_END;

	/* Reserve all regions that has been set up by bootloader */
	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
		u32 base, size;

		if (!gpmc_cs_mem_enabled(cs))
			continue;
		gpmc_cs_get_memconf(cs, &base, &size);
		if (gpmc_cs_insert_mem(cs, base, size) < 0)
			BUG();
	}
}

void __init gpmc_init(void)
{
	u32 l;
	char *ck;

	if (cpu_is_omap24xx()) {
		ck = "core_l3_ck";
		if (cpu_is_omap2420())
			l = OMAP2420_GPMC_BASE;
		else
			l = OMAP34XX_GPMC_BASE;
	} else if (cpu_is_omap34xx()) {
		ck = "gpmc_fck";
		l = OMAP34XX_GPMC_BASE;
	} else if (cpu_is_omap44xx()) {
		ck = "gpmc_fck";
		l = OMAP44XX_GPMC_BASE;
	}

	gpmc_l3_clk = clk_get(NULL, ck);
	if (IS_ERR(gpmc_l3_clk)) {
		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
		BUG();
	}

	gpmc_base = ioremap(l, SZ_4K);
	if (!gpmc_base) {
		clk_put(gpmc_l3_clk);
		printk(KERN_ERR "Could not get GPMC register memory\n");
		BUG();
	}

	l = gpmc_read_reg(GPMC_REVISION);
	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	/* Set smart idle mode and automatic L3 clock gating */
	l = gpmc_read_reg(GPMC_SYSCONFIG);
	l &= 0x03 << 3;
	l |= (0x02 << 3) | (1 << 0);
	gpmc_write_reg(GPMC_SYSCONFIG, l);
	gpmc_mem_init();
}
Commit	Line	Data
4bbbc1ad JY	1	/*
	2	* GPMC support functions
	3	*
	4	* Copyright (C) 2005-2006 Nokia Corporation
	5	*
	6	* Author: Juha Yrjola
	7	*
44169075 SS	8	* Copyright (C) 2009 Texas Instruments
	9	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	10	*
4bbbc1ad JY	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
fd1dc87d PW	15	#undef DEBUG
fd1dc87d PW	16
4bbbc1ad JY	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/err.h>
	20	#include <linux/clk.h>
f37e4580 ID	21	#include <linux/ioport.h>
f37e4580 ID	22	#include <linux/spinlock.h>
fced80c7	23	#include <linux/io.h>
fd1dc87d	24	#include <linux/module.h>
4bbbc1ad	25
7f245162	26	#include <asm/mach-types.h>
a09e64fb	27	#include <mach/gpmc.h>
4bbbc1ad	28
646e3ed1	29	#include <mach/sdrc.h>
72d0f1c3	30
fd1dc87d	31	/* GPMC register offsets */
4bbbc1ad JY	32	#define GPMC_REVISION 0x00
	33	#define GPMC_SYSCONFIG 0x10
	34	#define GPMC_SYSSTATUS 0x14
	35	#define GPMC_IRQSTATUS 0x18
	36	#define GPMC_IRQENABLE 0x1c
	37	#define GPMC_TIMEOUT_CONTROL 0x40
	38	#define GPMC_ERR_ADDRESS 0x44
	39	#define GPMC_ERR_TYPE 0x48
	40	#define GPMC_CONFIG 0x50
	41	#define GPMC_STATUS 0x54
	42	#define GPMC_PREFETCH_CONFIG1 0x1e0
	43	#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b	44	#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad JY	45	#define GPMC_PREFETCH_STATUS 0x1f0
	46	#define GPMC_ECC_CONFIG 0x1f4
	47	#define GPMC_ECC_CONTROL 0x1f8
	48	#define GPMC_ECC_SIZE_CONFIG 0x1fc
	49
	50	#define GPMC_CS0 0x60
	51	#define GPMC_CS_SIZE 0x30
	52
f37e4580 ID	53	#define GPMC_MEM_START 0x00000000
	54	#define GPMC_MEM_END 0x3FFFFFFF
	55	#define BOOT_ROM_SPACE 0x100000 /* 1MB */
	56
	57	#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
	58	#define GPMC_SECTION_SHIFT 28 /* 128 MB */
	59
59e9c5ae	60	#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
	61	#define CS_NUM_SHIFT 24
	62	#define ENABLE_PREFETCH (0x1 << 7)
	63	#define DMA_MPU_MODE 2
	64
f37e4580 ID	65	static struct resource gpmc_mem_root;
f37e4580 ID	66	static struct resource gpmc_cs_mem[GPMC_CS_NUM];
87b247c4	67	static DEFINE_SPINLOCK(gpmc_mem_lock);
f37e4580 ID	68	static unsigned gpmc_cs_map;
f37e4580 ID	69
fd1dc87d	70	static void __iomem *gpmc_base;
4bbbc1ad	71
fd1dc87d	72	static struct clk *gpmc_l3_clk;
4bbbc1ad JY	73
	74	static void gpmc_write_reg(int idx, u32 val)
	75	{
	76	__raw_writel(val, gpmc_base + idx);
	77	}
	78
	79	static u32 gpmc_read_reg(int idx)
	80	{
	81	return __raw_readl(gpmc_base + idx);
	82	}
	83
	84	void gpmc_cs_write_reg(int cs, int idx, u32 val)
	85	{
	86	void __iomem *reg_addr;
	87
fd1dc87d	88	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
4bbbc1ad JY	89	__raw_writel(val, reg_addr);
	90	}
	91
	92	u32 gpmc_cs_read_reg(int cs, int idx)
	93	{
fd1dc87d PW	94	void __iomem *reg_addr;
	95
	96	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	97	return __raw_readl(reg_addr);
4bbbc1ad JY	98	}
4bbbc1ad JY	99
fd1dc87d	100	/* TODO: Add support for gpmc_fck to clock framework and use it */
1c22cc13	101	unsigned long gpmc_get_fclk_period(void)
4bbbc1ad	102	{
fd1dc87d PW	103	unsigned long rate = clk_get_rate(gpmc_l3_clk);
	104
	105	if (rate == 0) {
	106	printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
	107	return 0;
	108	}
	109
	110	rate /= 1000;
	111	rate = 1000000000 / rate; /* In picoseconds */
	112
	113	return rate;
4bbbc1ad JY	114	}
	115
	116	unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
	117	{
	118	unsigned long tick_ps;
	119
	120	/* Calculate in picosecs to yield more exact results */
	121	tick_ps = gpmc_get_fclk_period();
	122
	123	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
	124	}
	125
fd1dc87d PW	126	unsigned int gpmc_ticks_to_ns(unsigned int ticks)
	127	{
	128	return ticks * gpmc_get_fclk_period() / 1000;
	129	}
	130
23300597 KS	131	unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
	132	{
	133	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
	134
	135	return ticks * gpmc_get_fclk_period() / 1000;
	136	}
	137
4bbbc1ad JY	138	#ifdef DEBUG
4bbbc1ad JY	139	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468	140	int time, const char *name)
4bbbc1ad JY	141	#else
	142	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
	143	int time)
	144	#endif
	145	{
	146	u32 l;
	147	int ticks, mask, nr_bits;
	148
	149	if (time == 0)
	150	ticks = 0;
	151	else
	152	ticks = gpmc_ns_to_ticks(time);
	153	nr_bits = end_bit - st_bit + 1;
1c22cc13 DB	154	if (ticks >= 1 << nr_bits) {
	155	#ifdef DEBUG
	156	printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
	157	cs, name, time, ticks, 1 << nr_bits);
	158	#endif
4bbbc1ad	159	return -1;
1c22cc13	160	}
4bbbc1ad JY	161
	162	mask = (1 << nr_bits) - 1;
	163	l = gpmc_cs_read_reg(cs, reg);
	164	#ifdef DEBUG
1c22cc13 DB	165	printk(KERN_INFO
1c22cc13 DB	166	"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468	167	cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13	168	(l >> st_bit) & mask, time);
4bbbc1ad JY	169	#endif
	170	l &= ~(mask << st_bit);
	171	l \|= ticks << st_bit;
	172	gpmc_cs_write_reg(cs, reg, l);
	173
	174	return 0;
	175	}
	176
	177	#ifdef DEBUG
	178	#define GPMC_SET_ONE(reg, st, end, field) \
	179	if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
	180	t->field, #field) < 0) \
	181	return -1
	182	#else
	183	#define GPMC_SET_ONE(reg, st, end, field) \
	184	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
	185	return -1
	186	#endif
	187
	188	int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
	189	{
	190	int div;
	191	u32 l;
	192
	193	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	194	div = l / gpmc_get_fclk_period();
	195	if (div > 4)
	196	return -1;
1c22cc13	197	if (div <= 0)
4bbbc1ad JY	198	div = 1;
	199
	200	return div;
	201	}
	202
	203	int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
	204	{
	205	int div;
	206	u32 l;
	207
	208	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	209	if (div < 0)
	210	return -1;
	211
	212	GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
	213	GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
	214	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
	215
	216	GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
	217	GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
	218	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
	219
	220	GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
	221	GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
	222	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	223	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
	224
	225	GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
	226	GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
	227	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
	228
	229	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
	230
cc26b3b0 SMK	231	if (cpu_is_omap34xx()) {
	232	GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
	233	GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
	234	}
	235
1c22cc13 DB	236	/* caller is expected to have initialized CONFIG1 to cover
	237	* at least sync vs async
	238	*/
	239	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	240	if (l & (GPMC_CONFIG1_READTYPE_SYNC \| GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad	241	#ifdef DEBUG
1c22cc13 DB	242	printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
1c22cc13 DB	243	cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad	244	#endif
1c22cc13 DB	245	l &= ~0x03;
	246	l \|= (div - 1);
	247	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	248	}
4bbbc1ad JY	249
	250	return 0;
	251	}
	252
f37e4580 ID	253	static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
	254	{
	255	u32 l;
	256	u32 mask;
	257
	258	mask = (1 << GPMC_SECTION_SHIFT) - size;
	259	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	260	l &= ~0x3f;
	261	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	262	l &= ~(0x0f << 8);
	263	l \|= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	264	l \|= 1 << 6; /* CSVALID */
	265	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	266	}
	267
	268	static void gpmc_cs_disable_mem(int cs)
	269	{
	270	u32 l;
	271
	272	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	273	l &= ~(1 << 6); /* CSVALID */
	274	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	275	}
	276
	277	static void gpmc_cs_get_memconf(int cs, u32 base, u32 size)
	278	{
	279	u32 l;
	280	u32 mask;
	281
	282	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	283	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	284	mask = (l >> 8) & 0x0f;
	285	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
	286	}
	287
	288	static int gpmc_cs_mem_enabled(int cs)
	289	{
	290	u32 l;
	291
	292	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	293	return l & (1 << 6);
	294	}
	295
c40fae95	296	int gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad	297	{
c40fae95 TL	298	if (cs > GPMC_CS_NUM)
	299	return -ENODEV;
	300
f37e4580 ID	301	gpmc_cs_map &= ~(1 << cs);
f37e4580 ID	302	gpmc_cs_map \|= (reserved ? 1 : 0) << cs;
c40fae95 TL	303
c40fae95 TL	304	return 0;
f37e4580 ID	305	}
f37e4580 ID	306
c40fae95	307	int gpmc_cs_reserved(int cs)
f37e4580	308	{
c40fae95 TL	309	if (cs > GPMC_CS_NUM)
	310	return -ENODEV;
	311
f37e4580 ID	312	return gpmc_cs_map & (1 << cs);
	313	}
	314
	315	static unsigned long gpmc_mem_align(unsigned long size)
	316	{
	317	int order;
	318
	319	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	320	order = GPMC_CHUNK_SHIFT - 1;
	321	do {
	322	size >>= 1;
	323	order++;
	324	} while (size);
	325	size = 1 << order;
	326	return size;
	327	}
	328
	329	static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
	330	{
	331	struct resource *res = &gpmc_cs_mem[cs];
	332	int r;
	333
	334	size = gpmc_mem_align(size);
	335	spin_lock(&gpmc_mem_lock);
	336	res->start = base;
	337	res->end = base + size - 1;
	338	r = request_resource(&gpmc_mem_root, res);
	339	spin_unlock(&gpmc_mem_lock);
	340
	341	return r;
	342	}
	343
	344	int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
	345	{
	346	struct resource *res = &gpmc_cs_mem[cs];
	347	int r = -1;
	348
	349	if (cs > GPMC_CS_NUM)
	350	return -ENODEV;
	351
	352	size = gpmc_mem_align(size);
	353	if (size > (1 << GPMC_SECTION_SHIFT))
	354	return -ENOMEM;
	355
	356	spin_lock(&gpmc_mem_lock);
	357	if (gpmc_cs_reserved(cs)) {
	358	r = -EBUSY;
	359	goto out;
	360	}
	361	if (gpmc_cs_mem_enabled(cs))
	362	r = adjust_resource(res, res->start & ~(size - 1), size);
	363	if (r < 0)
	364	r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
	365	size, NULL, NULL);
	366	if (r < 0)
	367	goto out;
	368
6d135242	369	gpmc_cs_enable_mem(cs, res->start, resource_size(res));
f37e4580 ID	370	*base = res->start;
	371	gpmc_cs_set_reserved(cs, 1);
	372	out:
	373	spin_unlock(&gpmc_mem_lock);
	374	return r;
	375	}
fd1dc87d	376	EXPORT_SYMBOL(gpmc_cs_request);
f37e4580 ID	377
	378	void gpmc_cs_free(int cs)
	379	{
	380	spin_lock(&gpmc_mem_lock);
	381	if (cs >= GPMC_CS_NUM \|\| !gpmc_cs_reserved(cs)) {
	382	printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
	383	BUG();
	384	spin_unlock(&gpmc_mem_lock);
	385	return;
	386	}
	387	gpmc_cs_disable_mem(cs);
	388	release_resource(&gpmc_cs_mem[cs]);
	389	gpmc_cs_set_reserved(cs, 0);
	390	spin_unlock(&gpmc_mem_lock);
	391	}
fd1dc87d	392	EXPORT_SYMBOL(gpmc_cs_free);
f37e4580	393
59e9c5ae	394	/**
	395	* gpmc_prefetch_enable - configures and starts prefetch transfer
	396	* @cs: nand cs (chip select) number
	397	* @dma_mode: dma mode enable (1) or disable (0)
	398	* @u32_count: number of bytes to be transferred
	399	* @is_write: prefetch read(0) or write post(1) mode
	400	*/
	401	int gpmc_prefetch_enable(int cs, int dma_mode,
	402	unsigned int u32_count, int is_write)
	403	{
	404	uint32_t prefetch_config1;
	405
	406	if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
	407	/* Set the amount of bytes to be prefetched */
	408	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
	409
	410	/* Set dma/mpu mode, the prefetch read / post write and
	411	* enable the engine. Set which cs is has requested for.
	412	*/
	413	prefetch_config1 = ((cs << CS_NUM_SHIFT) \|
	414	PREFETCH_FIFOTHRESHOLD \|
	415	ENABLE_PREFETCH \|
	416	(dma_mode << DMA_MPU_MODE) \|
	417	(0x1 & is_write));
	418	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
	419	} else {
	420	return -EBUSY;
	421	}
	422	/* Start the prefetch engine */
	423	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
	424
	425	return 0;
	426	}
	427	EXPORT_SYMBOL(gpmc_prefetch_enable);
	428
	429	/**
	430	* gpmc_prefetch_reset - disables and stops the prefetch engine
	431	*/
	432	void gpmc_prefetch_reset(void)
	433	{
	434	/* Stop the PFPW engine */
	435	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
	436
	437	/* Reset/disable the PFPW engine */
	438	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
	439	}
	440	EXPORT_SYMBOL(gpmc_prefetch_reset);
	441
	442	/**
	443	* gpmc_prefetch_status - reads prefetch status of engine
	444	*/
	445	int gpmc_prefetch_status(void)
	446	{
	447	return gpmc_read_reg(GPMC_PREFETCH_STATUS);
	448	}
	449	EXPORT_SYMBOL(gpmc_prefetch_status);
	450
fd1dc87d	451	static void __init gpmc_mem_init(void)
f37e4580 ID	452	{
	453	int cs;
	454	unsigned long boot_rom_space = 0;
	455
7f245162 KP	456	/* never allocate the first page, to facilitate bug detection;
	457	* even if we didn't boot from ROM.
	458	*/
	459	boot_rom_space = BOOT_ROM_SPACE;
	460	/* In apollon the CS0 is mapped as 0x0000 0000 */
	461	if (machine_is_omap_apollon())
	462	boot_rom_space = 0;
f37e4580 ID	463	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	464	gpmc_mem_root.end = GPMC_MEM_END;
	465
	466	/* Reserve all regions that has been set up by bootloader */
	467	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
	468	u32 base, size;
	469
	470	if (!gpmc_cs_mem_enabled(cs))
	471	continue;
	472	gpmc_cs_get_memconf(cs, &base, &size);
	473	if (gpmc_cs_insert_mem(cs, base, size) < 0)
	474	BUG();
	475	}
4bbbc1ad JY	476	}
	477
	478	void __init gpmc_init(void)
	479	{
	480	u32 l;
fd1dc87d PW	481	char *ck;
	482
	483	if (cpu_is_omap24xx()) {
	484	ck = "core_l3_ck";
	485	if (cpu_is_omap2420())
	486	l = OMAP2420_GPMC_BASE;
	487	else
	488	l = OMAP34XX_GPMC_BASE;
	489	} else if (cpu_is_omap34xx()) {
	490	ck = "gpmc_fck";
	491	l = OMAP34XX_GPMC_BASE;
44169075 SS	492	} else if (cpu_is_omap44xx()) {
	493	ck = "gpmc_fck";
	494	l = OMAP44XX_GPMC_BASE;
fd1dc87d	495	}
4bbbc1ad	496
fd1dc87d PW	497	gpmc_l3_clk = clk_get(NULL, ck);
	498	if (IS_ERR(gpmc_l3_clk)) {
	499	printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
85d7a070	500	BUG();
fd1dc87d PW	501	}
	502
	503	gpmc_base = ioremap(l, SZ_4K);
	504	if (!gpmc_base) {
	505	clk_put(gpmc_l3_clk);
	506	printk(KERN_ERR "Could not get GPMC register memory\n");
85d7a070	507	BUG();
fd1dc87d PW	508	}
fd1dc87d PW	509
4bbbc1ad JY	510	l = gpmc_read_reg(GPMC_REVISION);
	511	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	512	/* Set smart idle mode and automatic L3 clock gating */
	513	l = gpmc_read_reg(GPMC_SYSCONFIG);
	514	l &= 0x03 << 3;
	515	l \|= (0x02 << 3) \| (1 << 0);
	516	gpmc_write_reg(GPMC_SYSCONFIG, l);
f37e4580	517	gpmc_mem_init();
4bbbc1ad	518	}