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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / arch / arm / mach-omap2 / clock3xxx_data.c
CommitLineData
82e9bd58
PW		 1/*
2 * OMAP3 clock data
3 *
93340a22
PW		 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
82e9bd58
PW		 6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
82e9bd58
PW		 19#include <linux/kernel.h>
20#include <linux/clk.h>
93340a22 21#include <linux/list.h>
82e9bd58
PW		 22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
657ebfad 27#include "clock3xxx.h"
82e9bd58 28#include "clock34xx.h"
657ebfad
PW		 29#include "clock36xx.h"
30#include "clock3517.h"
31
82e9bd58
PW		 32#include "cm.h"
33#include "cm-regbits-34xx.h"
34#include "prm.h"
35#include "prm-regbits-34xx.h"
36
37/*
38 * clocks
39 */
40
41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43/* Maximum DPLL multiplier, divider values for OMAP3 */
93340a22 44#define OMAP3_MAX_DPLL_MULT 2047
358965d7 45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
82e9bd58
PW		 46#define OMAP3_MAX_DPLL_DIV 128
47
48/*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56/* Forward declarations for DPLL bypass clocks */
57static struct clk dpll1_fck;
58static struct clk dpll2_fck;
59
60/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
82e9bd58
PW		 67};
68
69static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
82e9bd58
PW		 73};
74
75/* Virtual source clocks for osc_sys_ck */
76static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
82e9bd58
PW		 80};
81
82static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
82e9bd58
PW		 86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
82e9bd58
PW		 92};
93
94static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
82e9bd58
PW		 98};
99
100static struct clk virt_26m_ck = {
101 .name = "virt_26m_ck",
102 .ops = &clkops_null,
103 .rate = 26000000,
82e9bd58
PW		 104};
105
106static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null,
109 .rate = 38400000,
82e9bd58
PW		 110};
111
112static const struct clksel_rate osc_sys_12m_rates[] = {
63405360 113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 114 { .div = 0 }
115};
116
117static const struct clksel_rate osc_sys_13m_rates[] = {
63405360 118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 119 { .div = 0 }
120};
121
122static const struct clksel_rate osc_sys_16_8m_rates[] = {
63405360 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
82e9bd58
PW		 124 { .div = 0 }
125};
126
127static const struct clksel_rate osc_sys_19_2m_rates[] = {
63405360 128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
82e9bd58
PW		 129 { .div = 0 }
130};
131
132static const struct clksel_rate osc_sys_26m_rates[] = {
63405360 133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
82e9bd58
PW		 134 { .div = 0 }
135};
136
137static const struct clksel_rate osc_sys_38_4m_rates[] = {
63405360 138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
82e9bd58
PW		 139 { .div = 0 }
140};
141
142static const struct clksel osc_sys_clksel[] = {
143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
149 { .parent = NULL },
150};
151
152/* Oscillator clock */
153/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154static struct clk osc_sys_ck = {
155 .name = "osc_sys_ck",
156 .ops = &clkops_null,
157 .init = &omap2_init_clksel_parent,
158 .clksel_reg = OMAP3430_PRM_CLKSEL,
159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
160 .clksel = osc_sys_clksel,
161 /* REVISIT: deal with autoextclkmode? */
82e9bd58
PW		 162 .recalc = &omap2_clksel_recalc,
163};
164
165static const struct clksel_rate div2_rates[] = {
63405360
PW		 166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
82e9bd58
PW		 168 { .div = 0 }
169};
170
171static const struct clksel sys_clksel[] = {
172 { .parent = &osc_sys_ck, .rates = div2_rates },
173 { .parent = NULL }
174};
175
176/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178static struct clk sys_ck = {
179 .name = "sys_ck",
180 .ops = &clkops_null,
181 .parent = &osc_sys_ck,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
184 .clksel_mask = OMAP_SYSCLKDIV_MASK,
185 .clksel = sys_clksel,
186 .recalc = &omap2_clksel_recalc,
187};
188
189static struct clk sys_altclk = {
190 .name = "sys_altclk",
191 .ops = &clkops_null,
192};
193
194/* Optional external clock input for some McBSPs */
195static struct clk mcbsp_clks = {
196 .name = "mcbsp_clks",
197 .ops = &clkops_null,
198};
199
200/* PRM EXTERNAL CLOCK OUTPUT */
201
202static struct clk sys_clkout1 = {
203 .name = "sys_clkout1",
204 .ops = &clkops_omap2_dflt,
205 .parent = &osc_sys_ck,
206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
208 .recalc = &followparent_recalc,
209};
210
211/* DPLLS */
212
213/* CM CLOCKS */
214
215static const struct clksel_rate div16_dpll_rates[] = {
63405360
PW		 216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
82e9bd58
PW		 232 { .div = 0 }
233};
234
2a9f5a4d
PW		 235static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
678bc9a2
VB		 252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
269};
270
82e9bd58
PW		 271/* DPLL1 */
272/* MPU clock source */
273/* Type: DPLL */
274static struct dpll_data dpll1_dd = {
275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
278 .clk_bypass = &dpll1_fck,
279 .clk_ref = &sys_ck,
280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295};
296
297static struct clk dpll1_ck = {
298 .name = "dpll1_ck",
299 .ops = &clkops_null,
300 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate,
303 .set_rate = &omap3_noncore_dpll_set_rate,
304 .clkdm_name = "dpll1_clkdm",
305 .recalc = &omap3_dpll_recalc,
306};
307
308/*
309 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
310 * DPLL isn't bypassed.
311 */
312static struct clk dpll1_x2_ck = {
313 .name = "dpll1_x2_ck",
314 .ops = &clkops_null,
315 .parent = &dpll1_ck,
316 .clkdm_name = "dpll1_clkdm",
317 .recalc = &omap3_clkoutx2_recalc,
318};
319
320/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
321static const struct clksel div16_dpll1_x2m2_clksel[] = {
322 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
323 { .parent = NULL }
324};
325
326/*
327 * Does not exist in the TRM - needed to separate the M2 divider from
328 * bypass selection in mpu_ck
329 */
330static struct clk dpll1_x2m2_ck = {
331 .name = "dpll1_x2m2_ck",
332 .ops = &clkops_null,
333 .parent = &dpll1_x2_ck,
334 .init = &omap2_init_clksel_parent,
335 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
336 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
337 .clksel = div16_dpll1_x2m2_clksel,
338 .clkdm_name = "dpll1_clkdm",
339 .recalc = &omap2_clksel_recalc,
340};
341
342/* DPLL2 */
343/* IVA2 clock source */
344/* Type: DPLL */
345
346static struct dpll_data dpll2_dd = {
347 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
348 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
349 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
350 .clk_bypass = &dpll2_fck,
351 .clk_ref = &sys_ck,
352 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
353 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
354 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
355 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
356 (1 << DPLL_LOW_POWER_BYPASS),
357 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
358 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
359 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
360 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
361 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
362 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
363 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
364 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368};
369
370static struct clk dpll2_ck = {
371 .name = "dpll2_ck",
657ebfad 372 .ops = &clkops_omap3_noncore_dpll_ops,
82e9bd58
PW		 373 .parent = &sys_ck,
374 .dpll_data = &dpll2_dd,
375 .round_rate = &omap2_dpll_round_rate,
376 .set_rate = &omap3_noncore_dpll_set_rate,
377 .clkdm_name = "dpll2_clkdm",
378 .recalc = &omap3_dpll_recalc,
379};
380
381static const struct clksel div16_dpll2_m2x2_clksel[] = {
382 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
383 { .parent = NULL }
384};
385
386/*
387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
388 * or CLKOUTX2. CLKOUT seems most plausible.
389 */
390static struct clk dpll2_m2_ck = {
391 .name = "dpll2_m2_ck",
392 .ops = &clkops_null,
393 .parent = &dpll2_ck,
394 .init = &omap2_init_clksel_parent,
395 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
396 OMAP3430_CM_CLKSEL2_PLL),
397 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
398 .clksel = div16_dpll2_m2x2_clksel,
399 .clkdm_name = "dpll2_clkdm",
400 .recalc = &omap2_clksel_recalc,
401};
402
403/*
404 * DPLL3
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
407 */
408static struct dpll_data dpll3_dd = {
409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
410 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
411 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
412 .clk_bypass = &sys_ck,
413 .clk_ref = &sys_ck,
414 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
417 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
418 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
419 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
421 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
423 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
424 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428};
429
430static struct clk dpll3_ck = {
431 .name = "dpll3_ck",
432 .ops = &clkops_null,
433 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate,
436 .clkdm_name = "dpll3_clkdm",
437 .recalc = &omap3_dpll_recalc,
438};
439
440/*
441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
442 * DPLL isn't bypassed
443 */
444static struct clk dpll3_x2_ck = {
445 .name = "dpll3_x2_ck",
446 .ops = &clkops_null,
447 .parent = &dpll3_ck,
448 .clkdm_name = "dpll3_clkdm",
449 .recalc = &omap3_clkoutx2_recalc,
450};
451
452static const struct clksel_rate div31_dpll3_rates[] = {
63405360
PW		 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
82e9bd58
PW		 484 { .div = 0 },
485};
486
487static const struct clksel div31_dpll3m2_clksel[] = {
488 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
489 { .parent = NULL }
490};
491
492/* DPLL3 output M2 - primary control point for CORE speed */
493static struct clk dpll3_m2_ck = {
494 .name = "dpll3_m2_ck",
495 .ops = &clkops_null,
496 .parent = &dpll3_ck,
497 .init = &omap2_init_clksel_parent,
498 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
499 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
500 .clksel = div31_dpll3m2_clksel,
501 .clkdm_name = "dpll3_clkdm",
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap3_core_dpll_m2_set_rate,
504 .recalc = &omap2_clksel_recalc,
505};
506
507static struct clk core_ck = {
508 .name = "core_ck",
509 .ops = &clkops_null,
510 .parent = &dpll3_m2_ck,
511 .recalc = &followparent_recalc,
512};
513
514static struct clk dpll3_m2x2_ck = {
515 .name = "dpll3_m2x2_ck",
516 .ops = &clkops_null,
517 .parent = &dpll3_m2_ck,
518 .clkdm_name = "dpll3_clkdm",
519 .recalc = &omap3_clkoutx2_recalc,
520};
521
522/* The PWRDN bit is apparently only available on 3430ES2 and above */
523static const struct clksel div16_dpll3_clksel[] = {
524 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
525 { .parent = NULL }
526};
527
528/* This virtual clock is the source for dpll3_m3x2_ck */
529static struct clk dpll3_m3_ck = {
530 .name = "dpll3_m3_ck",
531 .ops = &clkops_null,
532 .parent = &dpll3_ck,
533 .init = &omap2_init_clksel_parent,
534 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
535 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
536 .clksel = div16_dpll3_clksel,
537 .clkdm_name = "dpll3_clkdm",
538 .recalc = &omap2_clksel_recalc,
539};
540
541/* The PWRDN bit is apparently only available on 3430ES2 and above */
542static struct clk dpll3_m3x2_ck = {
543 .name = "dpll3_m3x2_ck",
544 .ops = &clkops_omap2_dflt_wait,
545 .parent = &dpll3_m3_ck,
546 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
547 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
548 .flags = INVERT_ENABLE,
549 .clkdm_name = "dpll3_clkdm",
550 .recalc = &omap3_clkoutx2_recalc,
551};
552
553static struct clk emu_core_alwon_ck = {
554 .name = "emu_core_alwon_ck",
555 .ops = &clkops_null,
556 .parent = &dpll3_m3x2_ck,
557 .clkdm_name = "dpll3_clkdm",
558 .recalc = &followparent_recalc,
559};
560
561/* DPLL4 */
562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563/* Type: DPLL */
358965d7 564static struct dpll_data dpll4_dd;
2a9f5a4d 565
358965d7 566static struct dpll_data dpll4_dd_34xx __initdata = {
82e9bd58
PW		 567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
568 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
569 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
570 .clk_bypass = &sys_ck,
571 .clk_ref = &sys_ck,
572 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
573 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
574 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
575 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
576 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
577 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
578 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
579 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
580 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
581 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
582 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
583 .max_multiplier = OMAP3_MAX_DPLL_MULT,
584 .min_divider = 1,
585 .max_divider = OMAP3_MAX_DPLL_DIV,
586 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
587};
588
358965d7
RW		 589static struct dpll_data dpll4_dd_3630 __initdata = {
590 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
591 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
592 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
593 .clk_bypass = &sys_ck,
594 .clk_ref = &sys_ck,
595 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
596 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
597 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
598 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
599 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
600 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
601 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
602 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
603 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
604 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
605 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
606 .min_divider = 1,
607 .max_divider = OMAP3_MAX_DPLL_DIV,
608 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
609 .flags = DPLL_J_TYPE
610};
611
82e9bd58
PW		 612static struct clk dpll4_ck = {
613 .name = "dpll4_ck",
657ebfad 614 .ops = &clkops_omap3_noncore_dpll_ops,
82e9bd58
PW		 615 .parent = &sys_ck,
616 .dpll_data = &dpll4_dd,
617 .round_rate = &omap2_dpll_round_rate,
618 .set_rate = &omap3_dpll4_set_rate,
619 .clkdm_name = "dpll4_clkdm",
620 .recalc = &omap3_dpll_recalc,
621};
622
623/*
624 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
625 * DPLL isn't bypassed --
626 * XXX does this serve any downstream clocks?
627 */
628static struct clk dpll4_x2_ck = {
629 .name = "dpll4_x2_ck",
630 .ops = &clkops_null,
631 .parent = &dpll4_ck,
632 .clkdm_name = "dpll4_clkdm",
633 .recalc = &omap3_clkoutx2_recalc,
634};
635
2a9f5a4d
PW		 636static const struct clksel dpll4_clksel[] = {
637 { .parent = &dpll4_ck, .rates = dpll4_rates },
678bc9a2
VB		 638 { .parent = NULL }
639};
640
82e9bd58 641/* This virtual clock is the source for dpll4_m2x2_ck */
2a9f5a4d 642static struct clk dpll4_m2_ck = {
678bc9a2
VB		 643 .name = "dpll4_m2_ck",
644 .ops = &clkops_null,
645 .parent = &dpll4_ck,
646 .init = &omap2_init_clksel_parent,
647 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
648 .clksel_mask = OMAP3630_DIV_96M_MASK,
2a9f5a4d 649 .clksel = dpll4_clksel,
678bc9a2
VB		 650 .clkdm_name = "dpll4_clkdm",
651 .recalc = &omap2_clksel_recalc,
652};
653
82e9bd58
PW		 654/* The PWRDN bit is apparently only available on 3430ES2 and above */
655static struct clk dpll4_m2x2_ck = {
656 .name = "dpll4_m2x2_ck",
657 .ops = &clkops_omap2_dflt_wait,
658 .parent = &dpll4_m2_ck,
659 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
660 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
661 .flags = INVERT_ENABLE,
662 .clkdm_name = "dpll4_clkdm",
663 .recalc = &omap3_clkoutx2_recalc,
664};
665
666/*
667 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
668 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
669 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
670 * CM_96K_(F)CLK.
671 */
7356f0b2
VB		 672
673/* Adding 192MHz Clock node needed by SGX */
674static struct clk omap_192m_alwon_fck = {
675 .name = "omap_192m_alwon_fck",
82e9bd58
PW		 676 .ops = &clkops_null,
677 .parent = &dpll4_m2x2_ck,
678 .recalc = &followparent_recalc,
679};
680
7356f0b2
VB		 681static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
682 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
d74b4949 683 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
7356f0b2
VB		 684 { .div = 0 }
685};
686
687static const struct clksel omap_96m_alwon_fck_clksel[] = {
688 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
689 { .parent = NULL }
82e9bd58
PW		 690};
691
692static const struct clksel_rate omap_96m_dpll_rates[] = {
63405360 693 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 694 { .div = 0 }
695};
696
697static const struct clksel_rate omap_96m_sys_rates[] = {
63405360 698 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 699 { .div = 0 }
700};
701
7356f0b2
VB		 702static struct clk omap_96m_alwon_fck = {
703 .name = "omap_96m_alwon_fck",
704 .ops = &clkops_null,
705 .parent = &dpll4_m2x2_ck,
706 .recalc = &followparent_recalc,
707};
708
709static struct clk omap_96m_alwon_fck_3630 = {
710 .name = "omap_96m_alwon_fck",
711 .parent = &omap_192m_alwon_fck,
712 .init = &omap2_init_clksel_parent,
713 .ops = &clkops_null,
714 .recalc = &omap2_clksel_recalc,
715 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
716 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
717 .clksel = omap_96m_alwon_fck_clksel
718};
719
720static struct clk cm_96m_fck = {
721 .name = "cm_96m_fck",
722 .ops = &clkops_null,
723 .parent = &omap_96m_alwon_fck,
724 .recalc = &followparent_recalc,
725};
726
82e9bd58
PW		 727static const struct clksel omap_96m_fck_clksel[] = {
728 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
729 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
730 { .parent = NULL }
731};
732
733static struct clk omap_96m_fck = {
734 .name = "omap_96m_fck",
735 .ops = &clkops_null,
736 .parent = &sys_ck,
737 .init = &omap2_init_clksel_parent,
738 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
739 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
740 .clksel = omap_96m_fck_clksel,
741 .recalc = &omap2_clksel_recalc,
742};
743
744/* This virtual clock is the source for dpll4_m3x2_ck */
2a9f5a4d 745static struct clk dpll4_m3_ck = {
82e9bd58
PW		 746 .name = "dpll4_m3_ck",
747 .ops = &clkops_null,
748 .parent = &dpll4_ck,
749 .init = &omap2_init_clksel_parent,
750 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
751 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
2a9f5a4d 752 .clksel = dpll4_clksel,
678bc9a2
VB		 753 .clkdm_name = "dpll4_clkdm",
754 .recalc = &omap2_clksel_recalc,
755};
756
82e9bd58
PW		 757/* The PWRDN bit is apparently only available on 3430ES2 and above */
758static struct clk dpll4_m3x2_ck = {
759 .name = "dpll4_m3x2_ck",
760 .ops = &clkops_omap2_dflt_wait,
761 .parent = &dpll4_m3_ck,
82e9bd58
PW		 762 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
763 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
764 .flags = INVERT_ENABLE,
765 .clkdm_name = "dpll4_clkdm",
766 .recalc = &omap3_clkoutx2_recalc,
767};
768
769static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
63405360 770 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 771 { .div = 0 }
772};
773
774static const struct clksel_rate omap_54m_alt_rates[] = {
63405360 775 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 776 { .div = 0 }
777};
778
779static const struct clksel omap_54m_clksel[] = {
780 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
781 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
782 { .parent = NULL }
783};
784
785static struct clk omap_54m_fck = {
786 .name = "omap_54m_fck",
787 .ops = &clkops_null,
788 .init = &omap2_init_clksel_parent,
789 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
790 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
791 .clksel = omap_54m_clksel,
792 .recalc = &omap2_clksel_recalc,
793};
794
795static const struct clksel_rate omap_48m_cm96m_rates[] = {
63405360 796 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 797 { .div = 0 }
798};
799
800static const struct clksel_rate omap_48m_alt_rates[] = {
63405360 801 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 802 { .div = 0 }
803};
804
805static const struct clksel omap_48m_clksel[] = {
806 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
807 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
808 { .parent = NULL }
809};
810
811static struct clk omap_48m_fck = {
812 .name = "omap_48m_fck",
813 .ops = &clkops_null,
814 .init = &omap2_init_clksel_parent,
815 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
816 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
817 .clksel = omap_48m_clksel,
818 .recalc = &omap2_clksel_recalc,
819};
820
821static struct clk omap_12m_fck = {
822 .name = "omap_12m_fck",
823 .ops = &clkops_null,
824 .parent = &omap_48m_fck,
825 .fixed_div = 4,
e9b98f60 826 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 827};
828
2a9f5a4d
PW		 829/* This virtual clock is the source for dpll4_m4x2_ck */
830static struct clk dpll4_m4_ck = {
82e9bd58
PW		 831 .name = "dpll4_m4_ck",
832 .ops = &clkops_null,
833 .parent = &dpll4_ck,
834 .init = &omap2_init_clksel_parent,
835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
836 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
2a9f5a4d 837 .clksel = dpll4_clksel,
678bc9a2
VB		 838 .clkdm_name = "dpll4_clkdm",
839 .recalc = &omap2_clksel_recalc,
840 .set_rate = &omap2_clksel_set_rate,
841 .round_rate = &omap2_clksel_round_rate,
842};
843
82e9bd58
PW		 844/* The PWRDN bit is apparently only available on 3430ES2 and above */
845static struct clk dpll4_m4x2_ck = {
846 .name = "dpll4_m4x2_ck",
847 .ops = &clkops_omap2_dflt_wait,
848 .parent = &dpll4_m4_ck,
849 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
d54a45e2 850 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
82e9bd58
PW		 851 .flags = INVERT_ENABLE,
852 .clkdm_name = "dpll4_clkdm",
853 .recalc = &omap3_clkoutx2_recalc,
854};
855
856/* This virtual clock is the source for dpll4_m5x2_ck */
2a9f5a4d 857static struct clk dpll4_m5_ck = {
82e9bd58
PW		 858 .name = "dpll4_m5_ck",
859 .ops = &clkops_null,
860 .parent = &dpll4_ck,
861 .init = &omap2_init_clksel_parent,
862 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
863 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
2a9f5a4d 864 .clksel = dpll4_clksel,
678bc9a2 865 .clkdm_name = "dpll4_clkdm",
e8d37377
VZ		 866 .set_rate = &omap2_clksel_set_rate,
867 .round_rate = &omap2_clksel_round_rate,
678bc9a2
VB		 868 .recalc = &omap2_clksel_recalc,
869};
870
82e9bd58
PW		 871/* The PWRDN bit is apparently only available on 3430ES2 and above */
872static struct clk dpll4_m5x2_ck = {
873 .name = "dpll4_m5x2_ck",
874 .ops = &clkops_omap2_dflt_wait,
875 .parent = &dpll4_m5_ck,
876 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
877 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
878 .flags = INVERT_ENABLE,
879 .clkdm_name = "dpll4_clkdm",
880 .recalc = &omap3_clkoutx2_recalc,
881};
882
883/* This virtual clock is the source for dpll4_m6x2_ck */
2a9f5a4d 884static struct clk dpll4_m6_ck = {
82e9bd58
PW		 885 .name = "dpll4_m6_ck",
886 .ops = &clkops_null,
887 .parent = &dpll4_ck,
888 .init = &omap2_init_clksel_parent,
889 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
890 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
2a9f5a4d 891 .clksel = dpll4_clksel,
678bc9a2
VB		 892 .clkdm_name = "dpll4_clkdm",
893 .recalc = &omap2_clksel_recalc,
894};
895
82e9bd58
PW		 896/* The PWRDN bit is apparently only available on 3430ES2 and above */
897static struct clk dpll4_m6x2_ck = {
898 .name = "dpll4_m6x2_ck",
899 .ops = &clkops_omap2_dflt_wait,
900 .parent = &dpll4_m6_ck,
82e9bd58
PW		 901 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
902 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
903 .flags = INVERT_ENABLE,
904 .clkdm_name = "dpll4_clkdm",
905 .recalc = &omap3_clkoutx2_recalc,
906};
907
908static struct clk emu_per_alwon_ck = {
909 .name = "emu_per_alwon_ck",
910 .ops = &clkops_null,
911 .parent = &dpll4_m6x2_ck,
912 .clkdm_name = "dpll4_clkdm",
913 .recalc = &followparent_recalc,
914};
915
916/* DPLL5 */
917/* Supplies 120MHz clock, USIM source clock */
918/* Type: DPLL */
919/* 3430ES2 only */
920static struct dpll_data dpll5_dd = {
921 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
922 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
923 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
924 .clk_bypass = &sys_ck,
925 .clk_ref = &sys_ck,
926 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
927 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
928 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
929 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
930 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
931 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
932 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
933 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
934 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
935 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
936 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
937 .max_multiplier = OMAP3_MAX_DPLL_MULT,
938 .min_divider = 1,
939 .max_divider = OMAP3_MAX_DPLL_DIV,
940 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
941};
942
943static struct clk dpll5_ck = {
944 .name = "dpll5_ck",
657ebfad 945 .ops = &clkops_omap3_noncore_dpll_ops,
82e9bd58
PW		 946 .parent = &sys_ck,
947 .dpll_data = &dpll5_dd,
948 .round_rate = &omap2_dpll_round_rate,
949 .set_rate = &omap3_noncore_dpll_set_rate,
950 .clkdm_name = "dpll5_clkdm",
951 .recalc = &omap3_dpll_recalc,
952};
953
954static const struct clksel div16_dpll5_clksel[] = {
955 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
956 { .parent = NULL }
957};
958
959static struct clk dpll5_m2_ck = {
960 .name = "dpll5_m2_ck",
961 .ops = &clkops_null,
962 .parent = &dpll5_ck,
963 .init = &omap2_init_clksel_parent,
964 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
965 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
966 .clksel = div16_dpll5_clksel,
967 .clkdm_name = "dpll5_clkdm",
968 .recalc = &omap2_clksel_recalc,
969};
970
971/* CM EXTERNAL CLOCK OUTPUTS */
972
973static const struct clksel_rate clkout2_src_core_rates[] = {
63405360 974 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 975 { .div = 0 }
976};
977
978static const struct clksel_rate clkout2_src_sys_rates[] = {
63405360 979 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 980 { .div = 0 }
981};
982
983static const struct clksel_rate clkout2_src_96m_rates[] = {
63405360 984 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
82e9bd58
PW		 985 { .div = 0 }
986};
987
988static const struct clksel_rate clkout2_src_54m_rates[] = {
63405360 989 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
82e9bd58
PW		 990 { .div = 0 }
991};
992
993static const struct clksel clkout2_src_clksel[] = {
994 { .parent = &core_ck, .rates = clkout2_src_core_rates },
995 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
996 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
997 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
998 { .parent = NULL }
999};
1000
1001static struct clk clkout2_src_ck = {
1002 .name = "clkout2_src_ck",
1003 .ops = &clkops_omap2_dflt,
1004 .init = &omap2_init_clksel_parent,
1005 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1006 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1007 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1008 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1009 .clksel = clkout2_src_clksel,
1010 .clkdm_name = "core_clkdm",
1011 .recalc = &omap2_clksel_recalc,
1012};
1013
1014static const struct clksel_rate sys_clkout2_rates[] = {
63405360
PW		 1015 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1016 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1017 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1018 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1019 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1020 { .div = 0 },
1021};
1022
1023static const struct clksel sys_clkout2_clksel[] = {
1024 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1025 { .parent = NULL },
1026};
1027
1028static struct clk sys_clkout2 = {
1029 .name = "sys_clkout2",
1030 .ops = &clkops_null,
1031 .init = &omap2_init_clksel_parent,
1032 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1033 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1034 .clksel = sys_clkout2_clksel,
1035 .recalc = &omap2_clksel_recalc,
71ee297a
LWA		 1036 .round_rate = &omap2_clksel_round_rate,
1037 .set_rate = &omap2_clksel_set_rate
82e9bd58
PW		 1038};
1039
1040/* CM OUTPUT CLOCKS */
1041
1042static struct clk corex2_fck = {
1043 .name = "corex2_fck",
1044 .ops = &clkops_null,
1045 .parent = &dpll3_m2x2_ck,
1046 .recalc = &followparent_recalc,
1047};
1048
1049/* DPLL power domain clock controls */
1050
1051static const struct clksel_rate div4_rates[] = {
63405360
PW		 1052 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1053 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1054 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1055 { .div = 0 }
1056};
1057
1058static const struct clksel div4_core_clksel[] = {
1059 { .parent = &core_ck, .rates = div4_rates },
1060 { .parent = NULL }
1061};
1062
1063/*
1064 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1065 * may be inconsistent here?
1066 */
1067static struct clk dpll1_fck = {
1068 .name = "dpll1_fck",
1069 .ops = &clkops_null,
1070 .parent = &core_ck,
1071 .init = &omap2_init_clksel_parent,
1072 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1073 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1074 .clksel = div4_core_clksel,
1075 .recalc = &omap2_clksel_recalc,
1076};
1077
1078static struct clk mpu_ck = {
1079 .name = "mpu_ck",
1080 .ops = &clkops_null,
1081 .parent = &dpll1_x2m2_ck,
1082 .clkdm_name = "mpu_clkdm",
1083 .recalc = &followparent_recalc,
1084};
1085
1086/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1087static const struct clksel_rate arm_fck_rates[] = {
63405360
PW		 1088 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1089 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1090 { .div = 0 },
1091};
1092
1093static const struct clksel arm_fck_clksel[] = {
1094 { .parent = &mpu_ck, .rates = arm_fck_rates },
1095 { .parent = NULL }
1096};
1097
1098static struct clk arm_fck = {
1099 .name = "arm_fck",
1100 .ops = &clkops_null,
1101 .parent = &mpu_ck,
1102 .init = &omap2_init_clksel_parent,
1103 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1104 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1105 .clksel = arm_fck_clksel,
1106 .clkdm_name = "mpu_clkdm",
1107 .recalc = &omap2_clksel_recalc,
1108};
1109
1110/* XXX What about neon_clkdm ? */
1111
1112/*
1113 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1114 * although it is referenced - so this is a guess
1115 */
1116static struct clk emu_mpu_alwon_ck = {
1117 .name = "emu_mpu_alwon_ck",
1118 .ops = &clkops_null,
1119 .parent = &mpu_ck,
1120 .recalc = &followparent_recalc,
1121};
1122
1123static struct clk dpll2_fck = {
1124 .name = "dpll2_fck",
1125 .ops = &clkops_null,
1126 .parent = &core_ck,
1127 .init = &omap2_init_clksel_parent,
1128 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1129 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1130 .clksel = div4_core_clksel,
1131 .recalc = &omap2_clksel_recalc,
1132};
1133
1134static struct clk iva2_ck = {
1135 .name = "iva2_ck",
1136 .ops = &clkops_omap2_dflt_wait,
1137 .parent = &dpll2_m2_ck,
82e9bd58
PW		 1138 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1139 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1140 .clkdm_name = "iva2_clkdm",
1141 .recalc = &followparent_recalc,
1142};
1143
1144/* Common interface clocks */
1145
1146static const struct clksel div2_core_clksel[] = {
1147 { .parent = &core_ck, .rates = div2_rates },
1148 { .parent = NULL }
1149};
1150
1151static struct clk l3_ick = {
1152 .name = "l3_ick",
1153 .ops = &clkops_null,
1154 .parent = &core_ck,
1155 .init = &omap2_init_clksel_parent,
1156 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1157 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1158 .clksel = div2_core_clksel,
1159 .clkdm_name = "core_l3_clkdm",
1160 .recalc = &omap2_clksel_recalc,
1161};
1162
1163static const struct clksel div2_l3_clksel[] = {
1164 { .parent = &l3_ick, .rates = div2_rates },
1165 { .parent = NULL }
1166};
1167
1168static struct clk l4_ick = {
1169 .name = "l4_ick",
1170 .ops = &clkops_null,
1171 .parent = &l3_ick,
1172 .init = &omap2_init_clksel_parent,
1173 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1174 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1175 .clksel = div2_l3_clksel,
1176 .clkdm_name = "core_l4_clkdm",
1177 .recalc = &omap2_clksel_recalc,
1178
1179};
1180
1181static const struct clksel div2_l4_clksel[] = {
1182 { .parent = &l4_ick, .rates = div2_rates },
1183 { .parent = NULL }
1184};
1185
1186static struct clk rm_ick = {
1187 .name = "rm_ick",
1188 .ops = &clkops_null,
1189 .parent = &l4_ick,
1190 .init = &omap2_init_clksel_parent,
1191 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1192 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1193 .clksel = div2_l4_clksel,
1194 .recalc = &omap2_clksel_recalc,
1195};
1196
1197/* GFX power domain */
1198
1199/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1200
1201static const struct clksel gfx_l3_clksel[] = {
1202 { .parent = &l3_ick, .rates = gfx_l3_rates },
1203 { .parent = NULL }
1204};
1205
1206/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1207static struct clk gfx_l3_ck = {
1208 .name = "gfx_l3_ck",
1209 .ops = &clkops_omap2_dflt_wait,
1210 .parent = &l3_ick,
82e9bd58
PW		 1211 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1212 .enable_bit = OMAP_EN_GFX_SHIFT,
1213 .recalc = &followparent_recalc,
1214};
1215
1216static struct clk gfx_l3_fck = {
1217 .name = "gfx_l3_fck",
1218 .ops = &clkops_null,
1219 .parent = &gfx_l3_ck,
1220 .init = &omap2_init_clksel_parent,
1221 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1222 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1223 .clksel = gfx_l3_clksel,
1224 .clkdm_name = "gfx_3430es1_clkdm",
1225 .recalc = &omap2_clksel_recalc,
1226};
1227
1228static struct clk gfx_l3_ick = {
1229 .name = "gfx_l3_ick",
1230 .ops = &clkops_null,
1231 .parent = &gfx_l3_ck,
1232 .clkdm_name = "gfx_3430es1_clkdm",
1233 .recalc = &followparent_recalc,
1234};
1235
1236static struct clk gfx_cg1_ck = {
1237 .name = "gfx_cg1_ck",
1238 .ops = &clkops_omap2_dflt_wait,
1239 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1240 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1241 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1242 .clkdm_name = "gfx_3430es1_clkdm",
1243 .recalc = &followparent_recalc,
1244};
1245
1246static struct clk gfx_cg2_ck = {
1247 .name = "gfx_cg2_ck",
1248 .ops = &clkops_omap2_dflt_wait,
1249 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1250 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1252 .clkdm_name = "gfx_3430es1_clkdm",
1253 .recalc = &followparent_recalc,
1254};
1255
1256/* SGX power domain - 3430ES2 only */
1257
1258static const struct clksel_rate sgx_core_rates[] = {
7356f0b2 1259 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
63405360
PW		 1260 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1261 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1262 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1263 { .div = 0 },
1264};
1265
7356f0b2 1266static const struct clksel_rate sgx_192m_rates[] = {
d74b4949 1267 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
7356f0b2
VB		 1268 { .div = 0 },
1269};
1270
1271static const struct clksel_rate sgx_corex2_rates[] = {
d74b4949 1272 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
7356f0b2
VB		 1273 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1274 { .div = 0 },
1275};
1276
82e9bd58 1277static const struct clksel_rate sgx_96m_rates[] = {
63405360 1278 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1279 { .div = 0 },
1280};
1281
1282static const struct clksel sgx_clksel[] = {
1283 { .parent = &core_ck, .rates = sgx_core_rates },
1284 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
7356f0b2
VB		 1285 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1286 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1287 { .parent = NULL }
82e9bd58
PW		 1288};
1289
1290static struct clk sgx_fck = {
1291 .name = "sgx_fck",
1292 .ops = &clkops_omap2_dflt_wait,
1293 .init = &omap2_init_clksel_parent,
1294 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1295 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1297 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1298 .clksel = sgx_clksel,
1299 .clkdm_name = "sgx_clkdm",
1300 .recalc = &omap2_clksel_recalc,
7356f0b2
VB		 1301 .set_rate = &omap2_clksel_set_rate,
1302 .round_rate = &omap2_clksel_round_rate
82e9bd58
PW		 1303};
1304
1305static struct clk sgx_ick = {
1306 .name = "sgx_ick",
1307 .ops = &clkops_omap2_dflt_wait,
1308 .parent = &l3_ick,
1309 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311 .clkdm_name = "sgx_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315/* CORE power domain */
1316
1317static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1319 .ops = &clkops_omap2_dflt_wait,
1320 .parent = &sys_ck,
1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1323 .clkdm_name = "d2d_clkdm",
1324 .recalc = &followparent_recalc,
1325};
1326
1327static struct clk modem_fck = {
1328 .name = "modem_fck",
1329 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &sys_ck,
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1333 .clkdm_name = "d2d_clkdm",
1334 .recalc = &followparent_recalc,
1335};
1336
1337static struct clk sad2d_ick = {
1338 .name = "sad2d_ick",
1339 .ops = &clkops_omap2_dflt_wait,
1340 .parent = &l3_ick,
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1343 .clkdm_name = "d2d_clkdm",
1344 .recalc = &followparent_recalc,
1345};
1346
1347static struct clk mad2d_ick = {
1348 .name = "mad2d_ick",
1349 .ops = &clkops_omap2_dflt_wait,
1350 .parent = &l3_ick,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1353 .clkdm_name = "d2d_clkdm",
1354 .recalc = &followparent_recalc,
1355};
1356
1357static const struct clksel omap343x_gpt_clksel[] = {
1358 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1359 { .parent = &sys_ck, .rates = gpt_sys_rates },
1360 { .parent = NULL}
1361};
1362
1363static struct clk gpt10_fck = {
1364 .name = "gpt10_fck",
1365 .ops = &clkops_omap2_dflt_wait,
1366 .parent = &sys_ck,
1367 .init = &omap2_init_clksel_parent,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1370 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1371 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1372 .clksel = omap343x_gpt_clksel,
1373 .clkdm_name = "core_l4_clkdm",
1374 .recalc = &omap2_clksel_recalc,
1375};
1376
1377static struct clk gpt11_fck = {
1378 .name = "gpt11_fck",
1379 .ops = &clkops_omap2_dflt_wait,
1380 .parent = &sys_ck,
1381 .init = &omap2_init_clksel_parent,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1384 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1386 .clksel = omap343x_gpt_clksel,
1387 .clkdm_name = "core_l4_clkdm",
1388 .recalc = &omap2_clksel_recalc,
1389};
1390
1391static struct clk cpefuse_fck = {
1392 .name = "cpefuse_fck",
1393 .ops = &clkops_omap2_dflt,
1394 .parent = &sys_ck,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1396 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk ts_fck = {
1401 .name = "ts_fck",
1402 .ops = &clkops_omap2_dflt,
1403 .parent = &omap_32k_fck,
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1405 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1406 .recalc = &followparent_recalc,
1407};
1408
1409static struct clk usbtll_fck = {
1410 .name = "usbtll_fck",
25499d93 1411 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1412 .parent = &dpll5_m2_ck,
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1414 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1415 .recalc = &followparent_recalc,
1416};
1417
1418/* CORE 96M FCLK-derived clocks */
1419
1420static struct clk core_96m_fck = {
1421 .name = "core_96m_fck",
1422 .ops = &clkops_null,
1423 .parent = &omap_96m_fck,
1424 .clkdm_name = "core_l4_clkdm",
1425 .recalc = &followparent_recalc,
1426};
1427
1428static struct clk mmchs3_fck = {
b92c170d 1429 .name = "mmchs3_fck",
82e9bd58 1430 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1431 .parent = &core_96m_fck,
1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1434 .clkdm_name = "core_l4_clkdm",
1435 .recalc = &followparent_recalc,
1436};
1437
1438static struct clk mmchs2_fck = {
b92c170d 1439 .name = "mmchs2_fck",
82e9bd58 1440 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1441 .parent = &core_96m_fck,
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1444 .clkdm_name = "core_l4_clkdm",
1445 .recalc = &followparent_recalc,
1446};
1447
1448static struct clk mspro_fck = {
1449 .name = "mspro_fck",
1450 .ops = &clkops_omap2_dflt_wait,
1451 .parent = &core_96m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1454 .clkdm_name = "core_l4_clkdm",
1455 .recalc = &followparent_recalc,
1456};
1457
1458static struct clk mmchs1_fck = {
b92c170d 1459 .name = "mmchs1_fck",
82e9bd58
PW		 1460 .ops = &clkops_omap2_dflt_wait,
1461 .parent = &core_96m_fck,
1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1464 .clkdm_name = "core_l4_clkdm",
1465 .recalc = &followparent_recalc,
1466};
1467
1468static struct clk i2c3_fck = {
b92c170d 1469 .name = "i2c3_fck",
82e9bd58 1470 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1471 .parent = &core_96m_fck,
1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1474 .clkdm_name = "core_l4_clkdm",
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk i2c2_fck = {
b92c170d 1479 .name = "i2c2_fck",
82e9bd58 1480 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1481 .parent = &core_96m_fck,
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1484 .clkdm_name = "core_l4_clkdm",
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk i2c1_fck = {
b92c170d 1489 .name = "i2c1_fck",
82e9bd58 1490 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1491 .parent = &core_96m_fck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1494 .clkdm_name = "core_l4_clkdm",
1495 .recalc = &followparent_recalc,
1496};
1497
1498/*
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1501 */
1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
63405360 1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1504 { .div = 0 }
1505};
1506
1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
63405360 1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1509 { .div = 0 }
1510};
1511
1512static const struct clksel mcbsp_15_clksel[] = {
1513 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1514 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1515 { .parent = NULL }
1516};
1517
1518static struct clk mcbsp5_fck = {
b92c170d 1519 .name = "mcbsp5_fck",
82e9bd58 1520 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1521 .init = &omap2_init_clksel_parent,
1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1524 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1525 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1526 .clksel = mcbsp_15_clksel,
1527 .clkdm_name = "core_l4_clkdm",
1528 .recalc = &omap2_clksel_recalc,
1529};
1530
1531static struct clk mcbsp1_fck = {
b92c170d 1532 .name = "mcbsp1_fck",
82e9bd58 1533 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1534 .init = &omap2_init_clksel_parent,
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1537 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1538 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1539 .clksel = mcbsp_15_clksel,
1540 .clkdm_name = "core_l4_clkdm",
1541 .recalc = &omap2_clksel_recalc,
1542};
1543
1544/* CORE_48M_FCK-derived clocks */
1545
1546static struct clk core_48m_fck = {
1547 .name = "core_48m_fck",
1548 .ops = &clkops_null,
1549 .parent = &omap_48m_fck,
1550 .clkdm_name = "core_l4_clkdm",
1551 .recalc = &followparent_recalc,
1552};
1553
1554static struct clk mcspi4_fck = {
b92c170d 1555 .name = "mcspi4_fck",
82e9bd58 1556 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1557 .parent = &core_48m_fck,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1560 .recalc = &followparent_recalc,
1561};
1562
1563static struct clk mcspi3_fck = {
b92c170d 1564 .name = "mcspi3_fck",
82e9bd58 1565 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1566 .parent = &core_48m_fck,
1567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1569 .recalc = &followparent_recalc,
1570};
1571
1572static struct clk mcspi2_fck = {
b92c170d 1573 .name = "mcspi2_fck",
82e9bd58 1574 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1575 .parent = &core_48m_fck,
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1578 .recalc = &followparent_recalc,
1579};
1580
1581static struct clk mcspi1_fck = {
b92c170d 1582 .name = "mcspi1_fck",
82e9bd58 1583 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1584 .parent = &core_48m_fck,
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1587 .recalc = &followparent_recalc,
1588};
1589
1590static struct clk uart2_fck = {
1591 .name = "uart2_fck",
1592 .ops = &clkops_omap2_dflt_wait,
1593 .parent = &core_48m_fck,
1594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1595 .enable_bit = OMAP3430_EN_UART2_SHIFT,
9b5bc5fa 1596 .clkdm_name = "core_l4_clkdm",
82e9bd58
PW		 1597 .recalc = &followparent_recalc,
1598};
1599
1600static struct clk uart1_fck = {
1601 .name = "uart1_fck",
1602 .ops = &clkops_omap2_dflt_wait,
1603 .parent = &core_48m_fck,
1604 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1605 .enable_bit = OMAP3430_EN_UART1_SHIFT,
9b5bc5fa 1606 .clkdm_name = "core_l4_clkdm",
82e9bd58
PW		 1607 .recalc = &followparent_recalc,
1608};
1609
1610static struct clk fshostusb_fck = {
1611 .name = "fshostusb_fck",
1612 .ops = &clkops_omap2_dflt_wait,
1613 .parent = &core_48m_fck,
1614 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1615 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1616 .recalc = &followparent_recalc,
1617};
1618
1619/* CORE_12M_FCK based clocks */
1620
1621static struct clk core_12m_fck = {
1622 .name = "core_12m_fck",
1623 .ops = &clkops_null,
1624 .parent = &omap_12m_fck,
1625 .clkdm_name = "core_l4_clkdm",
1626 .recalc = &followparent_recalc,
1627};
1628
1629static struct clk hdq_fck = {
1630 .name = "hdq_fck",
1631 .ops = &clkops_omap2_dflt_wait,
1632 .parent = &core_12m_fck,
1633 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1634 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1635 .recalc = &followparent_recalc,
1636};
1637
1638/* DPLL3-derived clock */
1639
1640static const struct clksel_rate ssi_ssr_corex2_rates[] = {
63405360
PW		 1641 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1642 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1643 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1644 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1645 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1646 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
82e9bd58
PW		 1647 { .div = 0 }
1648};
1649
1650static const struct clksel ssi_ssr_clksel[] = {
1651 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1652 { .parent = NULL }
1653};
1654
1655static struct clk ssi_ssr_fck_3430es1 = {
1656 .name = "ssi_ssr_fck",
1657 .ops = &clkops_omap2_dflt,
1658 .init = &omap2_init_clksel_parent,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1661 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1662 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1663 .clksel = ssi_ssr_clksel,
1664 .clkdm_name = "core_l4_clkdm",
1665 .recalc = &omap2_clksel_recalc,
1666};
1667
1668static struct clk ssi_ssr_fck_3430es2 = {
1669 .name = "ssi_ssr_fck",
1670 .ops = &clkops_omap3430es2_ssi_wait,
1671 .init = &omap2_init_clksel_parent,
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1673 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1674 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1675 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1676 .clksel = ssi_ssr_clksel,
1677 .clkdm_name = "core_l4_clkdm",
1678 .recalc = &omap2_clksel_recalc,
1679};
1680
1681static struct clk ssi_sst_fck_3430es1 = {
1682 .name = "ssi_sst_fck",
1683 .ops = &clkops_null,
1684 .parent = &ssi_ssr_fck_3430es1,
1685 .fixed_div = 2,
e9b98f60 1686 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 1687};
1688
1689static struct clk ssi_sst_fck_3430es2 = {
1690 .name = "ssi_sst_fck",
1691 .ops = &clkops_null,
1692 .parent = &ssi_ssr_fck_3430es2,
1693 .fixed_div = 2,
e9b98f60 1694 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 1695};
1696
1697
1698
1699/* CORE_L3_ICK based clocks */
1700
1701/*
1702 * XXX must add clk_enable/clk_disable for these if standard code won't
1703 * handle it
1704 */
1705static struct clk core_l3_ick = {
1706 .name = "core_l3_ick",
1707 .ops = &clkops_null,
1708 .parent = &l3_ick,
1709 .clkdm_name = "core_l3_clkdm",
1710 .recalc = &followparent_recalc,
1711};
1712
1713static struct clk hsotgusb_ick_3430es1 = {
1714 .name = "hsotgusb_ick",
1715 .ops = &clkops_omap2_dflt,
1716 .parent = &core_l3_ick,
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1719 .clkdm_name = "core_l3_clkdm",
1720 .recalc = &followparent_recalc,
1721};
1722
1723static struct clk hsotgusb_ick_3430es2 = {
1724 .name = "hsotgusb_ick",
1725 .ops = &clkops_omap3430es2_hsotgusb_wait,
1726 .parent = &core_l3_ick,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1729 .clkdm_name = "core_l3_clkdm",
1730 .recalc = &followparent_recalc,
1731};
1732
1733static struct clk sdrc_ick = {
1734 .name = "sdrc_ick",
1735 .ops = &clkops_omap2_dflt_wait,
1736 .parent = &core_l3_ick,
1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1739 .flags = ENABLE_ON_INIT,
1740 .clkdm_name = "core_l3_clkdm",
1741 .recalc = &followparent_recalc,
1742};
1743
1744static struct clk gpmc_fck = {
1745 .name = "gpmc_fck",
1746 .ops = &clkops_null,
1747 .parent = &core_l3_ick,
1748 .flags = ENABLE_ON_INIT, /* huh? */
1749 .clkdm_name = "core_l3_clkdm",
1750 .recalc = &followparent_recalc,
1751};
1752
1753/* SECURITY_L3_ICK based clocks */
1754
1755static struct clk security_l3_ick = {
1756 .name = "security_l3_ick",
1757 .ops = &clkops_null,
1758 .parent = &l3_ick,
1759 .recalc = &followparent_recalc,
1760};
1761
1762static struct clk pka_ick = {
1763 .name = "pka_ick",
1764 .ops = &clkops_omap2_dflt_wait,
1765 .parent = &security_l3_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1767 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1768 .recalc = &followparent_recalc,
1769};
1770
1771/* CORE_L4_ICK based clocks */
1772
1773static struct clk core_l4_ick = {
1774 .name = "core_l4_ick",
1775 .ops = &clkops_null,
1776 .parent = &l4_ick,
1777 .clkdm_name = "core_l4_clkdm",
1778 .recalc = &followparent_recalc,
1779};
1780
1781static struct clk usbtll_ick = {
1782 .name = "usbtll_ick",
1783 .ops = &clkops_omap2_dflt_wait,
1784 .parent = &core_l4_ick,
1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1786 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1787 .clkdm_name = "core_l4_clkdm",
1788 .recalc = &followparent_recalc,
1789};
1790
1791static struct clk mmchs3_ick = {
b92c170d 1792 .name = "mmchs3_ick",
82e9bd58 1793 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1794 .parent = &core_l4_ick,
1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1797 .clkdm_name = "core_l4_clkdm",
1798 .recalc = &followparent_recalc,
1799};
1800
1801/* Intersystem Communication Registers - chassis mode only */
1802static struct clk icr_ick = {
1803 .name = "icr_ick",
1804 .ops = &clkops_omap2_dflt_wait,
1805 .parent = &core_l4_ick,
1806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1808 .clkdm_name = "core_l4_clkdm",
1809 .recalc = &followparent_recalc,
1810};
1811
1812static struct clk aes2_ick = {
1813 .name = "aes2_ick",
1814 .ops = &clkops_omap2_dflt_wait,
1815 .parent = &core_l4_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1818 .clkdm_name = "core_l4_clkdm",
1819 .recalc = &followparent_recalc,
1820};
1821
1822static struct clk sha12_ick = {
1823 .name = "sha12_ick",
1824 .ops = &clkops_omap2_dflt_wait,
1825 .parent = &core_l4_ick,
1826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1827 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1828 .clkdm_name = "core_l4_clkdm",
1829 .recalc = &followparent_recalc,
1830};
1831
1832static struct clk des2_ick = {
1833 .name = "des2_ick",
1834 .ops = &clkops_omap2_dflt_wait,
1835 .parent = &core_l4_ick,
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1838 .clkdm_name = "core_l4_clkdm",
1839 .recalc = &followparent_recalc,
1840};
1841
1842static struct clk mmchs2_ick = {
b92c170d 1843 .name = "mmchs2_ick",
82e9bd58 1844 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1845 .parent = &core_l4_ick,
1846 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1848 .clkdm_name = "core_l4_clkdm",
1849 .recalc = &followparent_recalc,
1850};
1851
1852static struct clk mmchs1_ick = {
b92c170d 1853 .name = "mmchs1_ick",
82e9bd58
PW		 1854 .ops = &clkops_omap2_dflt_wait,
1855 .parent = &core_l4_ick,
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1858 .clkdm_name = "core_l4_clkdm",
1859 .recalc = &followparent_recalc,
1860};
1861
1862static struct clk mspro_ick = {
1863 .name = "mspro_ick",
1864 .ops = &clkops_omap2_dflt_wait,
1865 .parent = &core_l4_ick,
1866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1868 .clkdm_name = "core_l4_clkdm",
1869 .recalc = &followparent_recalc,
1870};
1871
1872static struct clk hdq_ick = {
1873 .name = "hdq_ick",
1874 .ops = &clkops_omap2_dflt_wait,
1875 .parent = &core_l4_ick,
1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1878 .clkdm_name = "core_l4_clkdm",
1879 .recalc = &followparent_recalc,
1880};
1881
1882static struct clk mcspi4_ick = {
b92c170d 1883 .name = "mcspi4_ick",
82e9bd58 1884 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1885 .parent = &core_l4_ick,
1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1888 .clkdm_name = "core_l4_clkdm",
1889 .recalc = &followparent_recalc,
1890};
1891
1892static struct clk mcspi3_ick = {
b92c170d 1893 .name = "mcspi3_ick",
82e9bd58 1894 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1895 .parent = &core_l4_ick,
1896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1898 .clkdm_name = "core_l4_clkdm",
1899 .recalc = &followparent_recalc,
1900};
1901
1902static struct clk mcspi2_ick = {
b92c170d 1903 .name = "mcspi2_ick",
82e9bd58 1904 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1905 .parent = &core_l4_ick,
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1908 .clkdm_name = "core_l4_clkdm",
1909 .recalc = &followparent_recalc,
1910};
1911
1912static struct clk mcspi1_ick = {
b92c170d 1913 .name = "mcspi1_ick",
82e9bd58 1914 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1915 .parent = &core_l4_ick,
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1918 .clkdm_name = "core_l4_clkdm",
1919 .recalc = &followparent_recalc,
1920};
1921
1922static struct clk i2c3_ick = {
b92c170d 1923 .name = "i2c3_ick",
82e9bd58 1924 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1925 .parent = &core_l4_ick,
1926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1928 .clkdm_name = "core_l4_clkdm",
1929 .recalc = &followparent_recalc,
1930};
1931
1932static struct clk i2c2_ick = {
b92c170d 1933 .name = "i2c2_ick",
82e9bd58 1934 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1935 .parent = &core_l4_ick,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1938 .clkdm_name = "core_l4_clkdm",
1939 .recalc = &followparent_recalc,
1940};
1941
1942static struct clk i2c1_ick = {
b92c170d 1943 .name = "i2c1_ick",
82e9bd58 1944 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1945 .parent = &core_l4_ick,
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1948 .clkdm_name = "core_l4_clkdm",
1949 .recalc = &followparent_recalc,
1950};
1951
1952static struct clk uart2_ick = {
1953 .name = "uart2_ick",
1954 .ops = &clkops_omap2_dflt_wait,
1955 .parent = &core_l4_ick,
1956 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1958 .clkdm_name = "core_l4_clkdm",
1959 .recalc = &followparent_recalc,
1960};
1961
1962static struct clk uart1_ick = {
1963 .name = "uart1_ick",
1964 .ops = &clkops_omap2_dflt_wait,
1965 .parent = &core_l4_ick,
1966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1968 .clkdm_name = "core_l4_clkdm",
1969 .recalc = &followparent_recalc,
1970};
1971
1972static struct clk gpt11_ick = {
1973 .name = "gpt11_ick",
1974 .ops = &clkops_omap2_dflt_wait,
1975 .parent = &core_l4_ick,
1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1978 .clkdm_name = "core_l4_clkdm",
1979 .recalc = &followparent_recalc,
1980};
1981
1982static struct clk gpt10_ick = {
1983 .name = "gpt10_ick",
1984 .ops = &clkops_omap2_dflt_wait,
1985 .parent = &core_l4_ick,
1986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1988 .clkdm_name = "core_l4_clkdm",
1989 .recalc = &followparent_recalc,
1990};
1991
1992static struct clk mcbsp5_ick = {
b92c170d 1993 .name = "mcbsp5_ick",
82e9bd58 1994 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1995 .parent = &core_l4_ick,
1996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1997 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1998 .clkdm_name = "core_l4_clkdm",
1999 .recalc = &followparent_recalc,
2000};
2001
2002static struct clk mcbsp1_ick = {
b92c170d 2003 .name = "mcbsp1_ick",
82e9bd58 2004 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2005 .parent = &core_l4_ick,
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2008 .clkdm_name = "core_l4_clkdm",
2009 .recalc = &followparent_recalc,
2010};
2011
2012static struct clk fac_ick = {
2013 .name = "fac_ick",
2014 .ops = &clkops_omap2_dflt_wait,
2015 .parent = &core_l4_ick,
2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2018 .clkdm_name = "core_l4_clkdm",
2019 .recalc = &followparent_recalc,
2020};
2021
2022static struct clk mailboxes_ick = {
2023 .name = "mailboxes_ick",
2024 .ops = &clkops_omap2_dflt_wait,
2025 .parent = &core_l4_ick,
2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2028 .clkdm_name = "core_l4_clkdm",
2029 .recalc = &followparent_recalc,
2030};
2031
2032static struct clk omapctrl_ick = {
2033 .name = "omapctrl_ick",
2034 .ops = &clkops_omap2_dflt_wait,
2035 .parent = &core_l4_ick,
2036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2037 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2038 .flags = ENABLE_ON_INIT,
2039 .recalc = &followparent_recalc,
2040};
2041
2042/* SSI_L4_ICK based clocks */
2043
2044static struct clk ssi_l4_ick = {
2045 .name = "ssi_l4_ick",
2046 .ops = &clkops_null,
2047 .parent = &l4_ick,
2048 .clkdm_name = "core_l4_clkdm",
2049 .recalc = &followparent_recalc,
2050};
2051
2052static struct clk ssi_ick_3430es1 = {
2053 .name = "ssi_ick",
2054 .ops = &clkops_omap2_dflt,
2055 .parent = &ssi_l4_ick,
2056 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2057 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2058 .clkdm_name = "core_l4_clkdm",
2059 .recalc = &followparent_recalc,
2060};
2061
2062static struct clk ssi_ick_3430es2 = {
2063 .name = "ssi_ick",
2064 .ops = &clkops_omap3430es2_ssi_wait,
2065 .parent = &ssi_l4_ick,
2066 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2067 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2068 .clkdm_name = "core_l4_clkdm",
2069 .recalc = &followparent_recalc,
2070};
2071
2072/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2073 * but l4_ick makes more sense to me */
2074
2075static const struct clksel usb_l4_clksel[] = {
2076 { .parent = &l4_ick, .rates = div2_rates },
2077 { .parent = NULL },
2078};
2079
2080static struct clk usb_l4_ick = {
2081 .name = "usb_l4_ick",
2082 .ops = &clkops_omap2_dflt_wait,
2083 .parent = &l4_ick,
2084 .init = &omap2_init_clksel_parent,
2085 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2086 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2087 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2088 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2089 .clksel = usb_l4_clksel,
2090 .recalc = &omap2_clksel_recalc,
2091};
2092
2093/* SECURITY_L4_ICK2 based clocks */
2094
2095static struct clk security_l4_ick2 = {
2096 .name = "security_l4_ick2",
2097 .ops = &clkops_null,
2098 .parent = &l4_ick,
2099 .recalc = &followparent_recalc,
2100};
2101
2102static struct clk aes1_ick = {
2103 .name = "aes1_ick",
2104 .ops = &clkops_omap2_dflt_wait,
2105 .parent = &security_l4_ick2,
2106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2107 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2108 .recalc = &followparent_recalc,
2109};
2110
2111static struct clk rng_ick = {
2112 .name = "rng_ick",
2113 .ops = &clkops_omap2_dflt_wait,
2114 .parent = &security_l4_ick2,
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2116 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk sha11_ick = {
2121 .name = "sha11_ick",
2122 .ops = &clkops_omap2_dflt_wait,
2123 .parent = &security_l4_ick2,
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2126 .recalc = &followparent_recalc,
2127};
2128
2129static struct clk des1_ick = {
2130 .name = "des1_ick",
2131 .ops = &clkops_omap2_dflt_wait,
2132 .parent = &security_l4_ick2,
2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2134 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2135 .recalc = &followparent_recalc,
2136};
2137
2138/* DSS */
2139static struct clk dss1_alwon_fck_3430es1 = {
2140 .name = "dss1_alwon_fck",
2141 .ops = &clkops_omap2_dflt,
2142 .parent = &dpll4_m4x2_ck,
2143 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2144 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2145 .clkdm_name = "dss_clkdm",
2146 .recalc = &followparent_recalc,
2147};
2148
2149static struct clk dss1_alwon_fck_3430es2 = {
2150 .name = "dss1_alwon_fck",
2151 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2152 .parent = &dpll4_m4x2_ck,
2153 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2154 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2155 .clkdm_name = "dss_clkdm",
2156 .recalc = &followparent_recalc,
2157};
2158
2159static struct clk dss_tv_fck = {
2160 .name = "dss_tv_fck",
2161 .ops = &clkops_omap2_dflt,
2162 .parent = &omap_54m_fck,
2163 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2164 .enable_bit = OMAP3430_EN_TV_SHIFT,
2165 .clkdm_name = "dss_clkdm",
2166 .recalc = &followparent_recalc,
2167};
2168
2169static struct clk dss_96m_fck = {
2170 .name = "dss_96m_fck",
2171 .ops = &clkops_omap2_dflt,
2172 .parent = &omap_96m_fck,
2173 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2174 .enable_bit = OMAP3430_EN_TV_SHIFT,
2175 .clkdm_name = "dss_clkdm",
2176 .recalc = &followparent_recalc,
2177};
2178
2179static struct clk dss2_alwon_fck = {
2180 .name = "dss2_alwon_fck",
2181 .ops = &clkops_omap2_dflt,
2182 .parent = &sys_ck,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2184 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2185 .clkdm_name = "dss_clkdm",
2186 .recalc = &followparent_recalc,
2187};
2188
2189static struct clk dss_ick_3430es1 = {
2190 /* Handles both L3 and L4 clocks */
2191 .name = "dss_ick",
2192 .ops = &clkops_omap2_dflt,
2193 .parent = &l4_ick,
2194 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2195 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2196 .clkdm_name = "dss_clkdm",
2197 .recalc = &followparent_recalc,
2198};
2199
2200static struct clk dss_ick_3430es2 = {
2201 /* Handles both L3 and L4 clocks */
2202 .name = "dss_ick",
2203 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2204 .parent = &l4_ick,
2205 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2206 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2207 .clkdm_name = "dss_clkdm",
2208 .recalc = &followparent_recalc,
2209};
2210
2211/* CAM */
2212
2213static struct clk cam_mclk = {
2214 .name = "cam_mclk",
2215 .ops = &clkops_omap2_dflt,
2216 .parent = &dpll4_m5x2_ck,
2217 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2218 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2219 .clkdm_name = "cam_clkdm",
2220 .recalc = &followparent_recalc,
2221};
2222
2223static struct clk cam_ick = {
2224 /* Handles both L3 and L4 clocks */
2225 .name = "cam_ick",
2226 .ops = &clkops_omap2_dflt,
2227 .parent = &l4_ick,
2228 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2229 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2230 .clkdm_name = "cam_clkdm",
2231 .recalc = &followparent_recalc,
2232};
2233
2234static struct clk csi2_96m_fck = {
2235 .name = "csi2_96m_fck",
2236 .ops = &clkops_omap2_dflt,
2237 .parent = &core_96m_fck,
2238 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2239 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2240 .clkdm_name = "cam_clkdm",
2241 .recalc = &followparent_recalc,
2242};
2243
2244/* USBHOST - 3430ES2 only */
2245
2246static struct clk usbhost_120m_fck = {
2247 .name = "usbhost_120m_fck",
2248 .ops = &clkops_omap2_dflt,
2249 .parent = &dpll5_m2_ck,
2250 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2251 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2252 .clkdm_name = "usbhost_clkdm",
2253 .recalc = &followparent_recalc,
2254};
2255
2256static struct clk usbhost_48m_fck = {
2257 .name = "usbhost_48m_fck",
2258 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2259 .parent = &omap_48m_fck,
2260 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2261 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2262 .clkdm_name = "usbhost_clkdm",
2263 .recalc = &followparent_recalc,
2264};
2265
2266static struct clk usbhost_ick = {
2267 /* Handles both L3 and L4 clocks */
2268 .name = "usbhost_ick",
2269 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2270 .parent = &l4_ick,
2271 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2272 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2273 .clkdm_name = "usbhost_clkdm",
2274 .recalc = &followparent_recalc,
2275};
2276
2277/* WKUP */
2278
2279static const struct clksel_rate usim_96m_rates[] = {
63405360
PW		 2280 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2281 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2282 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2283 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2284 { .div = 0 },
2285};
2286
2287static const struct clksel_rate usim_120m_rates[] = {
63405360
PW		 2288 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2289 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2290 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2291 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2292 { .div = 0 },
2293};
2294
2295static const struct clksel usim_clksel[] = {
2296 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2297 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2298 { .parent = &sys_ck, .rates = div2_rates },
2299 { .parent = NULL },
2300};
2301
2302/* 3430ES2 only */
2303static struct clk usim_fck = {
2304 .name = "usim_fck",
2305 .ops = &clkops_omap2_dflt_wait,
2306 .init = &omap2_init_clksel_parent,
2307 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2308 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2309 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2310 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2311 .clksel = usim_clksel,
2312 .recalc = &omap2_clksel_recalc,
2313};
2314
2315/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2316static struct clk gpt1_fck = {
2317 .name = "gpt1_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2319 .init = &omap2_init_clksel_parent,
2320 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2321 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2322 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2323 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2324 .clksel = omap343x_gpt_clksel,
2325 .clkdm_name = "wkup_clkdm",
2326 .recalc = &omap2_clksel_recalc,
2327};
2328
2329static struct clk wkup_32k_fck = {
2330 .name = "wkup_32k_fck",
2331 .ops = &clkops_null,
2332 .parent = &omap_32k_fck,
2333 .clkdm_name = "wkup_clkdm",
2334 .recalc = &followparent_recalc,
2335};
2336
2337static struct clk gpio1_dbck = {
2338 .name = "gpio1_dbck",
2339 .ops = &clkops_omap2_dflt,
2340 .parent = &wkup_32k_fck,
2341 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2342 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2343 .clkdm_name = "wkup_clkdm",
2344 .recalc = &followparent_recalc,
2345};
2346
2347static struct clk wdt2_fck = {
2348 .name = "wdt2_fck",
2349 .ops = &clkops_omap2_dflt_wait,
2350 .parent = &wkup_32k_fck,
2351 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2352 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2353 .clkdm_name = "wkup_clkdm",
2354 .recalc = &followparent_recalc,
2355};
2356
2357static struct clk wkup_l4_ick = {
2358 .name = "wkup_l4_ick",
2359 .ops = &clkops_null,
2360 .parent = &sys_ck,
2361 .clkdm_name = "wkup_clkdm",
2362 .recalc = &followparent_recalc,
2363};
2364
2365/* 3430ES2 only */
2366/* Never specifically named in the TRM, so we have to infer a likely name */
2367static struct clk usim_ick = {
2368 .name = "usim_ick",
2369 .ops = &clkops_omap2_dflt_wait,
2370 .parent = &wkup_l4_ick,
2371 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2372 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2373 .clkdm_name = "wkup_clkdm",
2374 .recalc = &followparent_recalc,
2375};
2376
2377static struct clk wdt2_ick = {
2378 .name = "wdt2_ick",
2379 .ops = &clkops_omap2_dflt_wait,
2380 .parent = &wkup_l4_ick,
2381 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2382 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2383 .clkdm_name = "wkup_clkdm",
2384 .recalc = &followparent_recalc,
2385};
2386
2387static struct clk wdt1_ick = {
2388 .name = "wdt1_ick",
2389 .ops = &clkops_omap2_dflt_wait,
2390 .parent = &wkup_l4_ick,
2391 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2392 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2393 .clkdm_name = "wkup_clkdm",
2394 .recalc = &followparent_recalc,
2395};
2396
2397static struct clk gpio1_ick = {
2398 .name = "gpio1_ick",
2399 .ops = &clkops_omap2_dflt_wait,
2400 .parent = &wkup_l4_ick,
2401 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2402 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2403 .clkdm_name = "wkup_clkdm",
2404 .recalc = &followparent_recalc,
2405};
2406
2407static struct clk omap_32ksync_ick = {
2408 .name = "omap_32ksync_ick",
2409 .ops = &clkops_omap2_dflt_wait,
2410 .parent = &wkup_l4_ick,
2411 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2412 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2413 .clkdm_name = "wkup_clkdm",
2414 .recalc = &followparent_recalc,
2415};
2416
2417/* XXX This clock no longer exists in 3430 TRM rev F */
2418static struct clk gpt12_ick = {
2419 .name = "gpt12_ick",
2420 .ops = &clkops_omap2_dflt_wait,
2421 .parent = &wkup_l4_ick,
2422 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2423 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2424 .clkdm_name = "wkup_clkdm",
2425 .recalc = &followparent_recalc,
2426};
2427
2428static struct clk gpt1_ick = {
2429 .name = "gpt1_ick",
2430 .ops = &clkops_omap2_dflt_wait,
2431 .parent = &wkup_l4_ick,
2432 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2433 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2434 .clkdm_name = "wkup_clkdm",
2435 .recalc = &followparent_recalc,
2436};
2437
2438
2439
2440/* PER clock domain */
2441
2442static struct clk per_96m_fck = {
2443 .name = "per_96m_fck",
2444 .ops = &clkops_null,
2445 .parent = &omap_96m_alwon_fck,
2446 .clkdm_name = "per_clkdm",
2447 .recalc = &followparent_recalc,
2448};
2449
2450static struct clk per_48m_fck = {
2451 .name = "per_48m_fck",
2452 .ops = &clkops_null,
2453 .parent = &omap_48m_fck,
2454 .clkdm_name = "per_clkdm",
2455 .recalc = &followparent_recalc,
2456};
2457
2458static struct clk uart3_fck = {
2459 .name = "uart3_fck",
2460 .ops = &clkops_omap2_dflt_wait,
2461 .parent = &per_48m_fck,
2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2463 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2464 .clkdm_name = "per_clkdm",
2465 .recalc = &followparent_recalc,
2466};
2467
2468static struct clk gpt2_fck = {
2469 .name = "gpt2_fck",
2470 .ops = &clkops_omap2_dflt_wait,
2471 .init = &omap2_init_clksel_parent,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2474 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2475 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2476 .clksel = omap343x_gpt_clksel,
2477 .clkdm_name = "per_clkdm",
2478 .recalc = &omap2_clksel_recalc,
2479};
2480
2481static struct clk gpt3_fck = {
2482 .name = "gpt3_fck",
2483 .ops = &clkops_omap2_dflt_wait,
2484 .init = &omap2_init_clksel_parent,
2485 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2486 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2487 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2488 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2489 .clksel = omap343x_gpt_clksel,
2490 .clkdm_name = "per_clkdm",
2491 .recalc = &omap2_clksel_recalc,
2492};
2493
2494static struct clk gpt4_fck = {
2495 .name = "gpt4_fck",
2496 .ops = &clkops_omap2_dflt_wait,
2497 .init = &omap2_init_clksel_parent,
2498 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2499 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2500 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2501 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2502 .clksel = omap343x_gpt_clksel,
2503 .clkdm_name = "per_clkdm",
2504 .recalc = &omap2_clksel_recalc,
2505};
2506
2507static struct clk gpt5_fck = {
2508 .name = "gpt5_fck",
2509 .ops = &clkops_omap2_dflt_wait,
2510 .init = &omap2_init_clksel_parent,
2511 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2512 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2513 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2514 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2515 .clksel = omap343x_gpt_clksel,
2516 .clkdm_name = "per_clkdm",
2517 .recalc = &omap2_clksel_recalc,
2518};
2519
2520static struct clk gpt6_fck = {
2521 .name = "gpt6_fck",
2522 .ops = &clkops_omap2_dflt_wait,
2523 .init = &omap2_init_clksel_parent,
2524 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2525 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2526 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2527 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2528 .clksel = omap343x_gpt_clksel,
2529 .clkdm_name = "per_clkdm",
2530 .recalc = &omap2_clksel_recalc,
2531};
2532
2533static struct clk gpt7_fck = {
2534 .name = "gpt7_fck",
2535 .ops = &clkops_omap2_dflt_wait,
2536 .init = &omap2_init_clksel_parent,
2537 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2538 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2539 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2540 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2541 .clksel = omap343x_gpt_clksel,
2542 .clkdm_name = "per_clkdm",
2543 .recalc = &omap2_clksel_recalc,
2544};
2545
2546static struct clk gpt8_fck = {
2547 .name = "gpt8_fck",
2548 .ops = &clkops_omap2_dflt_wait,
2549 .init = &omap2_init_clksel_parent,
2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2552 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2553 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2554 .clksel = omap343x_gpt_clksel,
2555 .clkdm_name = "per_clkdm",
2556 .recalc = &omap2_clksel_recalc,
2557};
2558
2559static struct clk gpt9_fck = {
2560 .name = "gpt9_fck",
2561 .ops = &clkops_omap2_dflt_wait,
2562 .init = &omap2_init_clksel_parent,
2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2565 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2566 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2567 .clksel = omap343x_gpt_clksel,
2568 .clkdm_name = "per_clkdm",
2569 .recalc = &omap2_clksel_recalc,
2570};
2571
2572static struct clk per_32k_alwon_fck = {
2573 .name = "per_32k_alwon_fck",
2574 .ops = &clkops_null,
2575 .parent = &omap_32k_fck,
2576 .clkdm_name = "per_clkdm",
2577 .recalc = &followparent_recalc,
2578};
2579
2580static struct clk gpio6_dbck = {
2581 .name = "gpio6_dbck",
2582 .ops = &clkops_omap2_dflt,
2583 .parent = &per_32k_alwon_fck,
2584 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2585 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2586 .clkdm_name = "per_clkdm",
2587 .recalc = &followparent_recalc,
2588};
2589
2590static struct clk gpio5_dbck = {
2591 .name = "gpio5_dbck",
2592 .ops = &clkops_omap2_dflt,
2593 .parent = &per_32k_alwon_fck,
2594 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2595 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2596 .clkdm_name = "per_clkdm",
2597 .recalc = &followparent_recalc,
2598};
2599
2600static struct clk gpio4_dbck = {
2601 .name = "gpio4_dbck",
2602 .ops = &clkops_omap2_dflt,
2603 .parent = &per_32k_alwon_fck,
2604 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2605 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2606 .clkdm_name = "per_clkdm",
2607 .recalc = &followparent_recalc,
2608};
2609
2610static struct clk gpio3_dbck = {
2611 .name = "gpio3_dbck",
2612 .ops = &clkops_omap2_dflt,
2613 .parent = &per_32k_alwon_fck,
2614 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2615 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2616 .clkdm_name = "per_clkdm",
2617 .recalc = &followparent_recalc,
2618};
2619
2620static struct clk gpio2_dbck = {
2621 .name = "gpio2_dbck",
2622 .ops = &clkops_omap2_dflt,
2623 .parent = &per_32k_alwon_fck,
2624 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2625 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2626 .clkdm_name = "per_clkdm",
2627 .recalc = &followparent_recalc,
2628};
2629
2630static struct clk wdt3_fck = {
2631 .name = "wdt3_fck",
2632 .ops = &clkops_omap2_dflt_wait,
2633 .parent = &per_32k_alwon_fck,
2634 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2635 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2636 .clkdm_name = "per_clkdm",
2637 .recalc = &followparent_recalc,
2638};
2639
2640static struct clk per_l4_ick = {
2641 .name = "per_l4_ick",
2642 .ops = &clkops_null,
2643 .parent = &l4_ick,
2644 .clkdm_name = "per_clkdm",
2645 .recalc = &followparent_recalc,
2646};
2647
2648static struct clk gpio6_ick = {
2649 .name = "gpio6_ick",
2650 .ops = &clkops_omap2_dflt_wait,
2651 .parent = &per_l4_ick,
2652 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2654 .clkdm_name = "per_clkdm",
2655 .recalc = &followparent_recalc,
2656};
2657
2658static struct clk gpio5_ick = {
2659 .name = "gpio5_ick",
2660 .ops = &clkops_omap2_dflt_wait,
2661 .parent = &per_l4_ick,
2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2664 .clkdm_name = "per_clkdm",
2665 .recalc = &followparent_recalc,
2666};
2667
2668static struct clk gpio4_ick = {
2669 .name = "gpio4_ick",
2670 .ops = &clkops_omap2_dflt_wait,
2671 .parent = &per_l4_ick,
2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2674 .clkdm_name = "per_clkdm",
2675 .recalc = &followparent_recalc,
2676};
2677
2678static struct clk gpio3_ick = {
2679 .name = "gpio3_ick",
2680 .ops = &clkops_omap2_dflt_wait,
2681 .parent = &per_l4_ick,
2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2684 .clkdm_name = "per_clkdm",
2685 .recalc = &followparent_recalc,
2686};
2687
2688static struct clk gpio2_ick = {
2689 .name = "gpio2_ick",
2690 .ops = &clkops_omap2_dflt_wait,
2691 .parent = &per_l4_ick,
2692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2694 .clkdm_name = "per_clkdm",
2695 .recalc = &followparent_recalc,
2696};
2697
2698static struct clk wdt3_ick = {
2699 .name = "wdt3_ick",
2700 .ops = &clkops_omap2_dflt_wait,
2701 .parent = &per_l4_ick,
2702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2704 .clkdm_name = "per_clkdm",
2705 .recalc = &followparent_recalc,
2706};
2707
2708static struct clk uart3_ick = {
2709 .name = "uart3_ick",
2710 .ops = &clkops_omap2_dflt_wait,
2711 .parent = &per_l4_ick,
2712 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2714 .clkdm_name = "per_clkdm",
2715 .recalc = &followparent_recalc,
2716};
2717
2718static struct clk gpt9_ick = {
2719 .name = "gpt9_ick",
2720 .ops = &clkops_omap2_dflt_wait,
2721 .parent = &per_l4_ick,
2722 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2724 .clkdm_name = "per_clkdm",
2725 .recalc = &followparent_recalc,
2726};
2727
2728static struct clk gpt8_ick = {
2729 .name = "gpt8_ick",
2730 .ops = &clkops_omap2_dflt_wait,
2731 .parent = &per_l4_ick,
2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2734 .clkdm_name = "per_clkdm",
2735 .recalc = &followparent_recalc,
2736};
2737
2738static struct clk gpt7_ick = {
2739 .name = "gpt7_ick",
2740 .ops = &clkops_omap2_dflt_wait,
2741 .parent = &per_l4_ick,
2742 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2744 .clkdm_name = "per_clkdm",
2745 .recalc = &followparent_recalc,
2746};
2747
2748static struct clk gpt6_ick = {
2749 .name = "gpt6_ick",
2750 .ops = &clkops_omap2_dflt_wait,
2751 .parent = &per_l4_ick,
2752 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2754 .clkdm_name = "per_clkdm",
2755 .recalc = &followparent_recalc,
2756};
2757
2758static struct clk gpt5_ick = {
2759 .name = "gpt5_ick",
2760 .ops = &clkops_omap2_dflt_wait,
2761 .parent = &per_l4_ick,
2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2764 .clkdm_name = "per_clkdm",
2765 .recalc = &followparent_recalc,
2766};
2767
2768static struct clk gpt4_ick = {
2769 .name = "gpt4_ick",
2770 .ops = &clkops_omap2_dflt_wait,
2771 .parent = &per_l4_ick,
2772 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2774 .clkdm_name = "per_clkdm",
2775 .recalc = &followparent_recalc,
2776};
2777
2778static struct clk gpt3_ick = {
2779 .name = "gpt3_ick",
2780 .ops = &clkops_omap2_dflt_wait,
2781 .parent = &per_l4_ick,
2782 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2783 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2784 .clkdm_name = "per_clkdm",
2785 .recalc = &followparent_recalc,
2786};
2787
2788static struct clk gpt2_ick = {
2789 .name = "gpt2_ick",
2790 .ops = &clkops_omap2_dflt_wait,
2791 .parent = &per_l4_ick,
2792 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2793 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2794 .clkdm_name = "per_clkdm",
2795 .recalc = &followparent_recalc,
2796};
2797
2798static struct clk mcbsp2_ick = {
b92c170d 2799 .name = "mcbsp2_ick",
82e9bd58 2800 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2801 .parent = &per_l4_ick,
2802 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2803 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2804 .clkdm_name = "per_clkdm",
2805 .recalc = &followparent_recalc,
2806};
2807
2808static struct clk mcbsp3_ick = {
b92c170d 2809 .name = "mcbsp3_ick",
82e9bd58 2810 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2811 .parent = &per_l4_ick,
2812 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2813 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2814 .clkdm_name = "per_clkdm",
2815 .recalc = &followparent_recalc,
2816};
2817
2818static struct clk mcbsp4_ick = {
b92c170d 2819 .name = "mcbsp4_ick",
82e9bd58 2820 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2821 .parent = &per_l4_ick,
2822 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2823 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2824 .clkdm_name = "per_clkdm",
2825 .recalc = &followparent_recalc,
2826};
2827
2828static const struct clksel mcbsp_234_clksel[] = {
073463ca 2829 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
82e9bd58
PW		 2830 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2831 { .parent = NULL }
2832};
2833
2834static struct clk mcbsp2_fck = {
b92c170d 2835 .name = "mcbsp2_fck",
82e9bd58 2836 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2837 .init = &omap2_init_clksel_parent,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2839 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2840 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2841 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2842 .clksel = mcbsp_234_clksel,
2843 .clkdm_name = "per_clkdm",
2844 .recalc = &omap2_clksel_recalc,
2845};
2846
2847static struct clk mcbsp3_fck = {
b92c170d 2848 .name = "mcbsp3_fck",
82e9bd58 2849 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2850 .init = &omap2_init_clksel_parent,
2851 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2852 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2853 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2854 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2855 .clksel = mcbsp_234_clksel,
2856 .clkdm_name = "per_clkdm",
2857 .recalc = &omap2_clksel_recalc,
2858};
2859
2860static struct clk mcbsp4_fck = {
b92c170d 2861 .name = "mcbsp4_fck",
82e9bd58 2862 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2863 .init = &omap2_init_clksel_parent,
2864 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2865 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2866 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2867 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2868 .clksel = mcbsp_234_clksel,
2869 .clkdm_name = "per_clkdm",
2870 .recalc = &omap2_clksel_recalc,
2871};
2872
2873/* EMU clocks */
2874
2875/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2876
2877static const struct clksel_rate emu_src_sys_rates[] = {
63405360 2878 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2879 { .div = 0 },
2880};
2881
2882static const struct clksel_rate emu_src_core_rates[] = {
63405360 2883 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2884 { .div = 0 },
2885};
2886
2887static const struct clksel_rate emu_src_per_rates[] = {
63405360 2888 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2889 { .div = 0 },
2890};
2891
2892static const struct clksel_rate emu_src_mpu_rates[] = {
63405360 2893 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2894 { .div = 0 },
2895};
2896
2897static const struct clksel emu_src_clksel[] = {
2898 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2899 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2900 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2901 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2902 { .parent = NULL },
2903};
2904
2905/*
2906 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2907 * to switch the source of some of the EMU clocks.
2908 * XXX Are there CLKEN bits for these EMU clks?
2909 */
2910static struct clk emu_src_ck = {
2911 .name = "emu_src_ck",
2912 .ops = &clkops_null,
2913 .init = &omap2_init_clksel_parent,
2914 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2915 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2916 .clksel = emu_src_clksel,
2917 .clkdm_name = "emu_clkdm",
2918 .recalc = &omap2_clksel_recalc,
2919};
2920
2921static const struct clksel_rate pclk_emu_rates[] = {
63405360
PW		 2922 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2923 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2924 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2925 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2926 { .div = 0 },
2927};
2928
2929static const struct clksel pclk_emu_clksel[] = {
2930 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2931 { .parent = NULL },
2932};
2933
2934static struct clk pclk_fck = {
2935 .name = "pclk_fck",
2936 .ops = &clkops_null,
2937 .init = &omap2_init_clksel_parent,
2938 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2939 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2940 .clksel = pclk_emu_clksel,
2941 .clkdm_name = "emu_clkdm",
2942 .recalc = &omap2_clksel_recalc,
2943};
2944
2945static const struct clksel_rate pclkx2_emu_rates[] = {
63405360
PW		 2946 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2947 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2948 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2949 { .div = 0 },
2950};
2951
2952static const struct clksel pclkx2_emu_clksel[] = {
2953 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2954 { .parent = NULL },
2955};
2956
2957static struct clk pclkx2_fck = {
2958 .name = "pclkx2_fck",
2959 .ops = &clkops_null,
2960 .init = &omap2_init_clksel_parent,
2961 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2962 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2963 .clksel = pclkx2_emu_clksel,
2964 .clkdm_name = "emu_clkdm",
2965 .recalc = &omap2_clksel_recalc,
2966};
2967
2968static const struct clksel atclk_emu_clksel[] = {
2969 { .parent = &emu_src_ck, .rates = div2_rates },
2970 { .parent = NULL },
2971};
2972
2973static struct clk atclk_fck = {
2974 .name = "atclk_fck",
2975 .ops = &clkops_null,
2976 .init = &omap2_init_clksel_parent,
2977 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2978 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2979 .clksel = atclk_emu_clksel,
2980 .clkdm_name = "emu_clkdm",
2981 .recalc = &omap2_clksel_recalc,
2982};
2983
2984static struct clk traceclk_src_fck = {
2985 .name = "traceclk_src_fck",
2986 .ops = &clkops_null,
2987 .init = &omap2_init_clksel_parent,
2988 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2989 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2990 .clksel = emu_src_clksel,
2991 .clkdm_name = "emu_clkdm",
2992 .recalc = &omap2_clksel_recalc,
2993};
2994
2995static const struct clksel_rate traceclk_rates[] = {
63405360
PW		 2996 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2997 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2998 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
82e9bd58
PW		 2999 { .div = 0 },
3000};
3001
3002static const struct clksel traceclk_clksel[] = {
3003 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3004 { .parent = NULL },
3005};
3006
3007static struct clk traceclk_fck = {
3008 .name = "traceclk_fck",
3009 .ops = &clkops_null,
3010 .init = &omap2_init_clksel_parent,
3011 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3012 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3013 .clksel = traceclk_clksel,
3014 .clkdm_name = "emu_clkdm",
3015 .recalc = &omap2_clksel_recalc,
3016};
3017
3018/* SR clocks */
3019
3020/* SmartReflex fclk (VDD1) */
3021static struct clk sr1_fck = {
3022 .name = "sr1_fck",
3023 .ops = &clkops_omap2_dflt_wait,
3024 .parent = &sys_ck,
3025 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3026 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3027 .recalc = &followparent_recalc,
3028};
3029
3030/* SmartReflex fclk (VDD2) */
3031static struct clk sr2_fck = {
3032 .name = "sr2_fck",
3033 .ops = &clkops_omap2_dflt_wait,
3034 .parent = &sys_ck,
3035 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3036 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3037 .recalc = &followparent_recalc,
3038};
3039
3040static struct clk sr_l4_ick = {
3041 .name = "sr_l4_ick",
3042 .ops = &clkops_null, /* RMK: missing? */
3043 .parent = &l4_ick,
3044 .clkdm_name = "core_l4_clkdm",
3045 .recalc = &followparent_recalc,
3046};
3047
3048/* SECURE_32K_FCK clocks */
3049
3050static struct clk gpt12_fck = {
3051 .name = "gpt12_fck",
3052 .ops = &clkops_null,
3053 .parent = &secure_32k_fck,
3054 .recalc = &followparent_recalc,
3055};
3056
3057static struct clk wdt1_fck = {
3058 .name = "wdt1_fck",
3059 .ops = &clkops_null,
3060 .parent = &secure_32k_fck,
3061 .recalc = &followparent_recalc,
3062};
3063
3cc4a2fc
RL		 3064/* Clocks for AM35XX */
3065static struct clk ipss_ick = {
3066 .name = "ipss_ick",
3067 .ops = &clkops_am35xx_ipss_wait,
3068 .parent = &core_l3_ick,
3069 .clkdm_name = "core_l3_clkdm",
3070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3071 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3072 .recalc = &followparent_recalc,
3073};
3074
3075static struct clk emac_ick = {
3076 .name = "emac_ick",
3077 .ops = &clkops_am35xx_ipss_module_wait,
3078 .parent = &ipss_ick,
3079 .clkdm_name = "core_l3_clkdm",
3080 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3081 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3082 .recalc = &followparent_recalc,
3083};
3084
3085static struct clk rmii_ck = {
3086 .name = "rmii_ck",
3087 .ops = &clkops_null,
3cc4a2fc
RL		 3088 .rate = 50000000,
3089};
3090
3091static struct clk emac_fck = {
3092 .name = "emac_fck",
3093 .ops = &clkops_omap2_dflt,
3094 .parent = &rmii_ck,
3095 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3096 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3097 .recalc = &followparent_recalc,
3098};
3099
3100static struct clk hsotgusb_ick_am35xx = {
3101 .name = "hsotgusb_ick",
3102 .ops = &clkops_am35xx_ipss_module_wait,
3103 .parent = &ipss_ick,
3104 .clkdm_name = "core_l3_clkdm",
3105 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3106 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3107 .recalc = &followparent_recalc,
3108};
3109
3110static struct clk hsotgusb_fck_am35xx = {
3111 .name = "hsotgusb_fck",
3112 .ops = &clkops_omap2_dflt,
3113 .parent = &sys_ck,
3114 .clkdm_name = "core_l3_clkdm",
3115 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3116 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3117 .recalc = &followparent_recalc,
3118};
3119
3120static struct clk hecc_ck = {
3121 .name = "hecc_ck",
3122 .ops = &clkops_am35xx_ipss_module_wait,
3123 .parent = &sys_ck,
3124 .clkdm_name = "core_l3_clkdm",
3125 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3126 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3127 .recalc = &followparent_recalc,
3128};
3129
3130static struct clk vpfe_ick = {
3131 .name = "vpfe_ick",
3132 .ops = &clkops_am35xx_ipss_module_wait,
3133 .parent = &ipss_ick,
3134 .clkdm_name = "core_l3_clkdm",
3135 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3136 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3137 .recalc = &followparent_recalc,
3138};
3139
3140static struct clk pclk_ck = {
3141 .name = "pclk_ck",
3142 .ops = &clkops_null,
3cc4a2fc
RL		 3143 .rate = 27000000,
3144};
3145
3146static struct clk vpfe_fck = {
3147 .name = "vpfe_fck",
3148 .ops = &clkops_omap2_dflt,
3149 .parent = &pclk_ck,
3150 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3151 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3152 .recalc = &followparent_recalc,
3153};
3154
3155/*
3156 * The UART1/2 functional clock acts as the functional
3157 * clock for UART4. No separate fclk control available.
3158 */
3159static struct clk uart4_ick_am35xx = {
3160 .name = "uart4_ick",
3161 .ops = &clkops_omap2_dflt_wait,
3162 .parent = &core_l4_ick,
3163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3164 .enable_bit = AM35XX_EN_UART4_SHIFT,
3165 .clkdm_name = "core_l4_clkdm",
3166 .recalc = &followparent_recalc,
3167};
3168
3126c7bc
RK		 3169static struct clk dummy_apb_pclk = {
3170 .name = "apb_pclk",
3171 .ops = &clkops_null,
3172};
82e9bd58
PW		 3173
3174/*
3175 * clkdev
3176 */
3177
ced82529
RL		 3178/* XXX At some point we should rename this file to clock3xxx_data.c */
3179static struct omap_clk omap3xxx_clks[] = {
3126c7bc 3180 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
ced82529
RL		 3181 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3182 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3183 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3184 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3185 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3186 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3187 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3188 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3189 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3190 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3191 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3192 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3193 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3194 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3195 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
82e9bd58
PW		 3196 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3197 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
ced82529
RL		 3198 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3199 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3200 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3201 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3202 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3203 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3204 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3205 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3206 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3207 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
7356f0b2 3208 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
ced82529
RL		 3209 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3210 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3211 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3212 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3213 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3214 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3215 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3216 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3217 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3218 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3219 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3220 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3221 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3222 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3223 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3224 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3225 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3226 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3227 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3228 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3229 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3230 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3231 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3232 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3233 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3234 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
82e9bd58
PW		 3235 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3236 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
ced82529
RL		 3237 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3238 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3239 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
82e9bd58
PW		 3240 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3241 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3242 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3243 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3244 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
ced82529
RL		 3245 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3246 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
82e9bd58
PW		 3247 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3248 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3249 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3250 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
ced82529
RL		 3251 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3252 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3253 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3254 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3255 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3256 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3257 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3258 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
82e9bd58 3259 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
ced82529
RL		 3260 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3261 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3262 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3263 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3264 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3265 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3266 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3267 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3268 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3269 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3270 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3271 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3272 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
82e9bd58 3273 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
ced82529
RL		 3274 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3275 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
82e9bd58
PW		 3276 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3277 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3278 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3279 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
ced82529 3280 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
82e9bd58
PW		 3281 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3282 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
ced82529
RL		 3283 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3284 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
82e9bd58
PW		 3285 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3286 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
ced82529
RL		 3287 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3288 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3289 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
82e9bd58
PW		 3290 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3291 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
ee5500c4 3292 CLK("omap-sham", "ick", &sha12_ick, CK_343X),
82e9bd58 3293 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
ced82529
RL		 3294 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3295 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
82e9bd58 3296 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
ced82529
RL		 3297 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3298 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3299 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3300 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3301 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3302 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3303 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3304 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3305 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3306 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3307 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3308 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3309 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3310 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
82e9bd58
PW		 3311 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3312 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
ced82529 3313 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
82e9bd58
PW		 3314 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3315 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3317 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3318 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3319 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3320 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3321 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3322 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3323 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
ced82529
RL		 3324 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3325 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3326 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3327 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
82e9bd58 3328 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
ced82529 3329 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
82e9bd58
PW		 3330 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3331 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3332 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
ced82529
RL		 3333 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3334 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3335 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
82e9bd58 3336 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
ced82529
RL		 3337 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3338 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3339 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3340 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
82e9bd58
PW		 3341 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3342 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
ced82529
RL		 3343 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3344 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3345 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3346 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3347 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3348 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3349 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3350 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3351 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3352 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3353 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3354 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3355 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3356 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3357 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3358 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3359 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3360 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3361 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3362 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3363 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3364 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3365 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3366 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3367 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3368 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3369 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3370 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3371 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3372 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3373 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3374 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3375 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3376 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3377 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3378 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3379 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3380 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3381 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3382 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3383 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3384 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3385 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3386 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3387 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3388 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3389 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3390 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3391 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3392 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3393 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3394 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
82e9bd58
PW		 3395 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3396 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3397 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
ced82529
RL		 3398 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3399 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3400 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3cc4a2fc
RL		 3401 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3402 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3403 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
b98dd73c
S		 3404 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3405 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3cc4a2fc
RL		 3406 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3407 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3408 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3409 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3410 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3411 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
82e9bd58
PW		 3412};
3413
3414
e80a9729 3415int __init omap3xxx_clk_init(void)
82e9bd58 3416{
82e9bd58 3417 struct omap_clk *c;
2c8a177e 3418 u32 cpu_clkflg = CK_3XXX;
82e9bd58 3419
8098bb0d 3420 if (cpu_is_omap3517()) {
3421 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3422 cpu_clkflg |= CK_3517;
3423 } else if (cpu_is_omap3505()) {
3424 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3425 cpu_clkflg |= CK_3505;
3426 } else if (cpu_is_omap34xx()) {
63405360 3427 cpu_mask = RATE_IN_3XXX;
2c8a177e 3428 cpu_clkflg |= CK_343X;
82e9bd58
PW		 3429
3430 /*
3431 * Update this if there are further clock changes between ES2
3432 * and production parts
3433 */
3434 if (omap_rev() == OMAP3430_REV_ES1_0) {
3435 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3436 cpu_clkflg |= CK_3430ES1;
3437 } else {
63405360 3438 cpu_mask |= RATE_IN_3430ES2PLUS;
82e9bd58
PW		 3439 cpu_clkflg |= CK_3430ES2;
3440 }
3441 }
63405360 3442
7356f0b2
VB		 3443 if (omap3_has_192mhz_clk())
3444 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
82e9bd58 3445
a7e069fc 3446 if (cpu_is_omap3630()) {
678bc9a2
VB		 3447 cpu_mask |= RATE_IN_36XX;
3448 cpu_clkflg |= CK_36XX;
3449
3450 /*
3451 * XXX This type of dynamic rewriting of the clock tree is
3452 * deprecated and should be revised soon.
2a9f5a4d 3453 *
a7e069fc
MT		 3454 * For 3630: override clkops_omap2_dflt_wait for the
3455 * clocks affected from PWRDN reset Limitation
3456 */
3457 dpll3_m3x2_ck.ops =
3458 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3459 dpll4_m2x2_ck.ops =
3460 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3461 dpll4_m3x2_ck.ops =
3462 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3463 dpll4_m4x2_ck.ops =
3464 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3465 dpll4_m5x2_ck.ops =
3466 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3467 dpll4_m6x2_ck.ops =
3468 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3469 }
3470
2a9f5a4d
PW		 3471 /*
3472 * XXX This type of dynamic rewriting of the clock tree is
3473 * deprecated and should be revised soon.
3474 */
358965d7
RW		 3475 if (cpu_is_omap3630())
3476 dpll4_dd = dpll4_dd_3630;
3477 else
3478 dpll4_dd = dpll4_dd_34xx;
3479
82e9bd58
PW		 3480 clk_init(&omap2_clk_functions);
3481
657ebfad
PW		 3482 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3483 c++)
82e9bd58
PW		 3484 clk_preinit(c->lk.clk);
3485
657ebfad
PW		 3486 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3487 c++)
82e9bd58
PW		 3488 if (c->cpu & cpu_clkflg) {
3489 clkdev_add(&c->lk);
3490 clk_register(c->lk.clk);
3491 omap2_init_clk_clkdm(c->lk.clk);
3492 }
3493
82e9bd58
PW		 3494 recalculate_root_clocks();
3495
3496 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3497 "%ld.%01ld/%ld/%ld MHz\n",
3498 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3499 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3500
3501 /*
3502 * Only enable those clocks we will need, let the drivers
3503 * enable other clocks as necessary
3504 */
3505 clk_enable_init_clocks();
3506
3507 /*
3508 * Lock DPLL5 and put it in autoidle.
3509 */
3510 if (omap_rev() >= OMAP3430_REV_ES2_0)
3511 omap3_clk_lock_dpll5();
3512
3513 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3514 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3515 arm_fck_p = clk_get(NULL, "arm_fck");
3516
3517 return 0;
3518}
Clone of davem's net-next-2.6 tree