[net-next-2.6.git] / arch / arm / mach-omap2 / clock.h

/*
 *  linux/arch/arm/mach-omap2/clock.h
 *
 *  Copyright (C) 2005-2009 Texas Instruments, Inc.
 *  Copyright (C) 2004-2009 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H

#include <plat/clock.h>

/* The maximum error between a target DPLL rate and the rounded rate in Hz */
#define DEFAULT_DPLL_RATE_TOLERANCE	50000

/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K		0x0
#define CORE_CLK_SRC_DPLL		0x1
#define CORE_CLK_SRC_DPLL_X2		0x2

/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
#define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
#define OMAP2XXX_EN_DPLL_LOCKED			0x3

/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP3XXX_EN_DPLL_LOCKED			0x7

/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
#define OMAP4XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP4XXX_EN_DPLL_LOCKED			0x7

/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP	0x1
#define DPLL_LOW_POWER_BYPASS	0x5
#define DPLL_LOCKED		0x7

int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap3_dpll_recalc(struct clk *clk);
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
void omap3_dpll_allow_idle(struct clk *clk);
void omap3_dpll_deny_idle(struct clk *clk);
u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);

#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
#else
#define omap2_clk_disable_unused	NULL
#endif

unsigned long omap2_clksel_recalc(struct clk *clk);
void omap2_init_clk_clkdm(struct clk *clk);
void omap2_init_clksel_parent(struct clk *clk);
u32 omap2_clksel_get_divisor(struct clk *clk);
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
				u32 *new_div);
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);


#ifdef CONFIG_ARCH_OMAP2
void omap2xxx_clk_prepare_for_reboot(void);
#else
static inline void omap2xxx_clk_prepare_for_reboot(void)
{
}
#endif

#ifdef CONFIG_ARCH_OMAP3
void omap3_clk_prepare_for_reboot(void);
#else
static inline void omap3_clk_prepare_for_reboot(void)
{
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void omap4_clk_prepare_for_reboot(void);
#else
static inline void omap4_clk_prepare_for_reboot(void)
{
}
#endif

int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
				u8 *idlest_bit);
void omap2xxx_clk_commit(struct clk *clk);

extern u8 cpu_mask;

extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt;

extern struct clk_functions omap2_clk_functions;
extern struct clk *vclk, *sclk;

extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];

#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_CPU_FREQ)
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#else
#define omap2_clk_init_cpufreq_table	0
#define omap2_clk_exit_cpufreq_table	0
#endif

#endif
Commit	Line	Data
543d9378 PW	1	/*
	2	* linux/arch/arm/mach-omap2/clock.h
	3	*
d8a94458 PW	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
d8a94458 PW	5	* Copyright (C) 2004-2009 Nokia Corporation
543d9378	6	*
a16e9703 TL	7	* Contacts:
a16e9703 TL	8	* Richard Woodruff <r-woodruff2@ti.com>
543d9378 PW	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
	17	#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
	18
ce491cf8	19	#include <plat/clock.h>
543d9378	20
88b8ba90 PW	21	/* The maximum error between a target DPLL rate and the rounded rate in Hz */
	22	#define DEFAULT_DPLL_RATE_TOLERANCE 50000
	23
c0bf3132 RK	24	/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
	25	#define CORE_CLK_SRC_32K 0x0
	26	#define CORE_CLK_SRC_DPLL 0x1
	27	#define CORE_CLK_SRC_DPLL_X2 0x2
	28
	29	/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
	30	#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
	31	#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
	32	#define OMAP2XXX_EN_DPLL_LOCKED 0x3
	33
	34	/* OMAP3xxx CM_CLKEN_PLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	35	#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
	36	#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
	37	#define OMAP3XXX_EN_DPLL_LOCKED 0x7
	38
16975a79 RN	39	/* OMAP4xxx CM_CLKMODE_DPLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	40	#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
	41	#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
	42	#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
	43	#define OMAP4XXX_EN_DPLL_LOCKED 0x7
	44
a1391d27 RN	45	/* CM_CLKEN_PLL.EN bit values - not all are available for every DPLL */
	46	#define DPLL_LOW_POWER_STOP 0x1
	47	#define DPLL_LOW_POWER_BYPASS 0x5
	48	#define DPLL_LOCKED 0x7
	49
543d9378 PW	50	int omap2_clk_enable(struct clk *clk);
	51	void omap2_clk_disable(struct clk *clk);
	52	long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
	53	int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
	54	int omap2_clk_set_parent(struct clk clk, struct clk new_parent);
fecb494b	55	int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
88b8ba90	56	long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
a1391d27 RN	57	unsigned long omap3_dpll_recalc(struct clk *clk);
	58	unsigned long omap3_clkoutx2_recalc(struct clk *clk);
	59	void omap3_dpll_allow_idle(struct clk *clk);
	60	void omap3_dpll_deny_idle(struct clk *clk);
	61	u32 omap3_dpll_autoidle_read(struct clk *clk);
	62	int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
	63	int omap3_noncore_dpll_enable(struct clk *clk);
	64	void omap3_noncore_dpll_disable(struct clk *clk);
543d9378 PW	65
	66	#ifdef CONFIG_OMAP_RESET_CLOCKS
	67	void omap2_clk_disable_unused(struct clk *clk);
	68	#else
	69	#define omap2_clk_disable_unused NULL
	70	#endif
	71
8b9dbc16	72	unsigned long omap2_clksel_recalc(struct clk *clk);
333943ba	73	void omap2_init_clk_clkdm(struct clk *clk);
543d9378 PW	74	void omap2_init_clksel_parent(struct clk *clk);
	75	u32 omap2_clksel_get_divisor(struct clk *clk);
	76	u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
	77	u32 *new_div);
	78	u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
	79	u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
543d9378 PW	80	long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
543d9378 PW	81	int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
df791b3e	82	int omap2_clksel_set_parent(struct clk clk, struct clk new_parent);
543d9378	83	u32 omap2_get_dpll_rate(struct clk *clk);
911bd739	84	void omap2_init_dpll_parent(struct clk *clk);
543d9378	85	int omap2_wait_clock_ready(void __iomem reg, u32 cval, const char name);
56213ca4 TL	86
	87
	88	#ifdef CONFIG_ARCH_OMAP2
	89	void omap2xxx_clk_prepare_for_reboot(void);
	90	#else
	91	static inline void omap2xxx_clk_prepare_for_reboot(void)
	92	{
	93	}
	94	#endif
	95
	96	#ifdef CONFIG_ARCH_OMAP3
	97	void omap3_clk_prepare_for_reboot(void);
	98	#else
	99	static inline void omap3_clk_prepare_for_reboot(void)
	100	{
	101	}
	102	#endif
	103
	104	#ifdef CONFIG_ARCH_OMAP4
	105	void omap4_clk_prepare_for_reboot(void);
	106	#else
	107	static inline void omap4_clk_prepare_for_reboot(void)
	108	{
	109	}
	110	#endif
	111
72350b29 PW	112	int omap2_dflt_clk_enable(struct clk *clk);
	113	void omap2_dflt_clk_disable(struct clk *clk);
	114	void omap2_clk_dflt_find_companion(struct clk clk, void __iomem *other_reg,
	115	u8 *other_bit);
	116	void omap2_clk_dflt_find_idlest(struct clk clk, void __iomem *idlest_reg,
	117	u8 *idlest_bit);
df791b3e	118	void omap2xxx_clk_commit(struct clk *clk);
543d9378	119
d8a94458 PW	120	extern u8 cpu_mask;
d8a94458 PW	121
b36ee724	122	extern const struct clkops clkops_omap2_dflt_wait;
bc51da4e	123	extern const struct clkops clkops_omap2_dflt;
b36ee724	124
82e9bd58	125	extern struct clk_functions omap2_clk_functions;
d8a94458	126	extern struct clk vclk, sclk;
82e9bd58	127
d8a94458 PW	128	extern const struct clksel_rate gpt_32k_rates[];
	129	extern const struct clksel_rate gpt_sys_rates[];
	130	extern const struct clksel_rate gfx_l3_rates[];
543d9378	131
69ecefca PW	132	#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_CPU_FREQ)
	133	extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
	134	extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
	135	#else
	136	#define omap2_clk_init_cpufreq_table 0
	137	#define omap2_clk_exit_cpufreq_table 0
	138	#endif
543d9378 PW	139
543d9378 PW	140	#endif