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1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | |
3 | * | |
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4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2009 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
18 | ||
ce491cf8 | 19 | #include <plat/clock.h> |
543d9378 | 20 | |
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21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | |
23 | ||
c0bf3132 RK |
24 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
25 | #define CORE_CLK_SRC_32K 0x0 | |
26 | #define CORE_CLK_SRC_DPLL 0x1 | |
27 | #define CORE_CLK_SRC_DPLL_X2 0x2 | |
28 | ||
29 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | |
30 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | |
31 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | |
32 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | |
33 | ||
34 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | |
35 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | |
36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | |
37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | |
38 | ||
16975a79 RN |
39 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
40 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | |
41 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | |
42 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | |
43 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | |
44 | ||
a1391d27 RN |
45 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
46 | #define DPLL_LOW_POWER_STOP 0x1 | |
47 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
48 | #define DPLL_LOCKED 0x7 | |
49 | ||
646e3ed1 | 50 | int omap2_clk_init(void); |
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51 | int omap2_clk_enable(struct clk *clk); |
52 | void omap2_clk_disable(struct clk *clk); | |
53 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | |
54 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |
55 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | |
fecb494b | 56 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
88b8ba90 | 57 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
a1391d27 RN |
58 | unsigned long omap3_dpll_recalc(struct clk *clk); |
59 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | |
60 | void omap3_dpll_allow_idle(struct clk *clk); | |
61 | void omap3_dpll_deny_idle(struct clk *clk); | |
62 | u32 omap3_dpll_autoidle_read(struct clk *clk); | |
63 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | |
64 | int omap3_noncore_dpll_enable(struct clk *clk); | |
65 | void omap3_noncore_dpll_disable(struct clk *clk); | |
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66 | |
67 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
68 | void omap2_clk_disable_unused(struct clk *clk); | |
69 | #else | |
70 | #define omap2_clk_disable_unused NULL | |
71 | #endif | |
72 | ||
8b9dbc16 | 73 | unsigned long omap2_clksel_recalc(struct clk *clk); |
333943ba | 74 | void omap2_init_clk_clkdm(struct clk *clk); |
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75 | void omap2_init_clksel_parent(struct clk *clk); |
76 | u32 omap2_clksel_get_divisor(struct clk *clk); | |
77 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |
78 | u32 *new_div); | |
79 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | |
80 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | |
8b9dbc16 | 81 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); |
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82 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
83 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | |
84 | u32 omap2_get_dpll_rate(struct clk *clk); | |
85 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | |
ff00fcc9 | 86 | void omap2_clk_prepare_for_reboot(void); |
72350b29 PW |
87 | int omap2_dflt_clk_enable(struct clk *clk); |
88 | void omap2_dflt_clk_disable(struct clk *clk); | |
89 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |
90 | u8 *other_bit); | |
91 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | |
92 | u8 *idlest_bit); | |
543d9378 | 93 | |
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94 | extern u8 cpu_mask; |
95 | ||
b36ee724 | 96 | extern const struct clkops clkops_omap2_dflt_wait; |
bc51da4e | 97 | extern const struct clkops clkops_omap2_dflt; |
b36ee724 | 98 | |
82e9bd58 | 99 | extern struct clk_functions omap2_clk_functions; |
d8a94458 | 100 | extern struct clk *vclk, *sclk; |
82e9bd58 | 101 | |
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102 | extern const struct clksel_rate gpt_32k_rates[]; |
103 | extern const struct clksel_rate gpt_sys_rates[]; | |
104 | extern const struct clksel_rate gfx_l3_rates[]; | |
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105 | |
106 | ||
107 | #endif |