[net-next-2.6.git] / arch / arm / mach-omap1 / serial.c

/*
 * linux/arch/arm/mach-omap1/serial.c
 *
 * OMAP1 serial support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach-types.h>

#include <plat/board.h>
#include <plat/mux.h>
#include <mach/gpio.h>
#include <plat/fpga.h>

static struct clk * uart1_ck;
static struct clk * uart2_ck;
static struct clk * uart3_ck;

static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
					  int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
				    int value)
{
	offset <<= p->regshift;
	__raw_writeb(value, p->membase + offset);
}

/*
 * Internal UARTs need to be initialized for the 8250 autoconfig to work
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */
static void __init omap_serial_reset(struct plat_serial8250_port *p)
{
	omap_serial_outp(p, UART_OMAP_MDR1, 0x07);	/* disable UART */
	omap_serial_outp(p, UART_OMAP_SCR, 0x08);	/* TX watermark */
	omap_serial_outp(p, UART_OMAP_MDR1, 0x00);	/* enable UART */

	if (!cpu_is_omap15xx()) {
		omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
		while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
	}
}

static struct plat_serial8250_port serial_platform_data[] = {
	{
		.mapbase	= OMAP_UART1_BASE,
		.irq		= INT_UART1,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{
		.mapbase	= OMAP_UART2_BASE,
		.irq		= INT_UART2,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{
		.mapbase	= OMAP_UART3_BASE,
		.irq		= INT_UART3,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{ },
};

static struct platform_device serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= serial_platform_data,
	},
};

/*
 * Note that on Innovator-1510 UART2 pins conflict with USB2.
 * By default UART2 does not work on Innovator-1510 if you have
 * USB OHCI enabled. To use UART2, you must disable USB2 first.
 */
void __init omap_serial_init(void)
{
	int i;

	if (cpu_is_omap7xx()) {
		serial_platform_data[0].regshift = 0;
		serial_platform_data[1].regshift = 0;
		serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
		serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
	}

	if (cpu_is_omap15xx()) {
		serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
		serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
		serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
	}

	for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {

		/* Static mapping, never released */
		serial_platform_data[i].membase =
			ioremap(serial_platform_data[i].mapbase, SZ_2K);
		if (!serial_platform_data[i].membase) {
			printk(KERN_ERR "Could not ioremap uart%i\n", i);
			continue;
		}
		switch (i) {
		case 0:
			uart1_ck = clk_get(NULL, "uart1_ck");
			if (IS_ERR(uart1_ck))
				printk("Could not get uart1_ck\n");
			else {
				clk_enable(uart1_ck);
				if (cpu_is_omap15xx())
					clk_set_rate(uart1_ck, 12000000);
			}
			break;
		case 1:
			uart2_ck = clk_get(NULL, "uart2_ck");
			if (IS_ERR(uart2_ck))
				printk("Could not get uart2_ck\n");
			else {
				clk_enable(uart2_ck);
				if (cpu_is_omap15xx())
					clk_set_rate(uart2_ck, 12000000);
				else
					clk_set_rate(uart2_ck, 48000000);
			}
			break;
		case 2:
			uart3_ck = clk_get(NULL, "uart3_ck");
			if (IS_ERR(uart3_ck))
				printk("Could not get uart3_ck\n");
			else {
				clk_enable(uart3_ck);
				if (cpu_is_omap15xx())
					clk_set_rate(uart3_ck, 12000000);
			}
			break;
		}
		omap_serial_reset(&serial_platform_data[i]);
	}
}

#ifdef CONFIG_OMAP_SERIAL_WAKE

static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
{
	/* Need to do something with serial port right after wake-up? */
	return IRQ_HANDLED;
}

/*
 * Reroutes serial RX lines to GPIO lines for the duration of
 * sleep to allow waking up the device from serial port even
 * in deep sleep.
 */
void omap_serial_wake_trigger(int enable)
{
	if (!cpu_is_omap16xx())
		return;

	if (uart1_ck != NULL) {
		if (enable)
			omap_cfg_reg(V14_16XX_GPIO37);
		else
			omap_cfg_reg(V14_16XX_UART1_RX);
	}
	if (uart2_ck != NULL) {
		if (enable)
			omap_cfg_reg(R9_16XX_GPIO18);
		else
			omap_cfg_reg(R9_16XX_UART2_RX);
	}
	if (uart3_ck != NULL) {
		if (enable)
			omap_cfg_reg(L14_16XX_GPIO49);
		else
			omap_cfg_reg(L14_16XX_UART3_RX);
	}
}

static void __init omap_serial_set_port_wakeup(int gpio_nr)
{
	int ret;

	ret = gpio_request(gpio_nr, "UART wake");
	if (ret < 0) {
		printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
		       gpio_nr);
		return;
	}
	gpio_direction_input(gpio_nr);
	ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
			  IRQF_TRIGGER_RISING, "serial wakeup", NULL);
	if (ret) {
		gpio_free(gpio_nr);
		printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
		       gpio_nr);
		return;
	}
	enable_irq_wake(gpio_to_irq(gpio_nr));
}

static int __init omap_serial_wakeup_init(void)
{
	if (!cpu_is_omap16xx())
		return 0;

	if (uart1_ck != NULL)
		omap_serial_set_port_wakeup(37);
	if (uart2_ck != NULL)
		omap_serial_set_port_wakeup(18);
	if (uart3_ck != NULL)
		omap_serial_set_port_wakeup(49);

	return 0;
}
late_initcall(omap_serial_wakeup_init);

#endif	/* CONFIG_OMAP_SERIAL_WAKE */

static int __init omap_init(void)
{
	return platform_device_register(&serial_device);
}
arch_initcall(omap_init);
Commit	Line	Data
f577ffd7	1	/*
f30c2269	2	* linux/arch/arm/mach-omap1/serial.c
f577ffd7	3	*
65d873ca	4	* OMAP1 serial support.
f577ffd7 TL	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
f577ffd7 TL	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
d533c128	14	#include <linux/irq.h>
f577ffd7 TL	15	#include <linux/delay.h>
	16	#include <linux/serial.h>
	17	#include <linux/tty.h>
	18	#include <linux/serial_8250.h>
	19	#include <linux/serial_reg.h>
f8ce2547	20	#include <linux/clk.h>
fced80c7	21	#include <linux/io.h>
f577ffd7	22
f577ffd7	23	#include <asm/mach-types.h>
f577ffd7	24
ce491cf8 TL	25	#include <plat/board.h>
ce491cf8 TL	26	#include <plat/mux.h>
a09e64fb	27	#include <mach/gpio.h>
ce491cf8	28	#include <plat/fpga.h>
f577ffd7	29
120db2cb TL	30	static struct clk * uart1_ck;
	31	static struct clk * uart2_ck;
	32	static struct clk * uart3_ck;
f577ffd7 TL	33
	34	static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
	35	int offset)
	36	{
	37	offset <<= up->regshift;
	38	return (unsigned int)__raw_readb(up->membase + offset);
	39	}
	40
	41	static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
	42	int value)
	43	{
	44	offset <<= p->regshift;
	45	__raw_writeb(value, p->membase + offset);
	46	}
	47
	48	/*
	49	* Internal UARTs need to be initialized for the 8250 autoconfig to work
	50	* properly. Note that the TX watermark initialization may not be needed
	51	* once the 8250.c watermark handling code is merged.
	52	*/
	53	static void __init omap_serial_reset(struct plat_serial8250_port *p)
	54	{
	55	omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */
	56	omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */
	57	omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */
	58
65d873ca	59	if (!cpu_is_omap15xx()) {
f577ffd7 TL	60	omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
	61	while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
	62	}
	63	}
	64
	65	static struct plat_serial8250_port serial_platform_data[] = {
	66	{
e8a91c95	67	.mapbase = OMAP_UART1_BASE,
f577ffd7 TL	68	.irq = INT_UART1,
	69	.flags = UPF_BOOT_AUTOCONF,
	70	.iotype = UPIO_MEM,
	71	.regshift = 2,
	72	.uartclk = OMAP16XX_BASE_BAUD * 16,
	73	},
	74	{
e8a91c95	75	.mapbase = OMAP_UART2_BASE,
f577ffd7 TL	76	.irq = INT_UART2,
	77	.flags = UPF_BOOT_AUTOCONF,
	78	.iotype = UPIO_MEM,
	79	.regshift = 2,
	80	.uartclk = OMAP16XX_BASE_BAUD * 16,
	81	},
	82	{
e8a91c95	83	.mapbase = OMAP_UART3_BASE,
f577ffd7 TL	84	.irq = INT_UART3,
	85	.flags = UPF_BOOT_AUTOCONF,
	86	.iotype = UPIO_MEM,
	87	.regshift = 2,
	88	.uartclk = OMAP16XX_BASE_BAUD * 16,
	89	},
	90	{ },
	91	};
	92
	93	static struct platform_device serial_device = {
	94	.name = "serial8250",
6df29deb	95	.id = PLAT8250_DEV_PLATFORM,
f577ffd7 TL	96	.dev = {
	97	.platform_data = serial_platform_data,
	98	},
	99	};
	100
	101	/*
	102	* Note that on Innovator-1510 UART2 pins conflict with USB2.
	103	* By default UART2 does not work on Innovator-1510 if you have
	104	* USB OHCI enabled. To use UART2, you must disable USB2 first.
	105	*/
3179a019	106	void __init omap_serial_init(void)
f577ffd7 TL	107	{
	108	int i;
	109
d8723ae2	110	if (cpu_is_omap7xx()) {
f577ffd7 TL	111	serial_platform_data[0].regshift = 0;
f577ffd7 TL	112	serial_platform_data[1].regshift = 0;
372b1c32 AB	113	serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
372b1c32 AB	114	serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
56739a69 ZM	115	}
56739a69 ZM	116
65d873ca	117	if (cpu_is_omap15xx()) {
f577ffd7 TL	118	serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
	119	serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
	120	serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
	121	}
	122
9d30b99f	123	for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {
f577ffd7	124
84f90c9c TL	125	/* Static mapping, never released */
	126	serial_platform_data[i].membase =
	127	ioremap(serial_platform_data[i].mapbase, SZ_2K);
	128	if (!serial_platform_data[i].membase) {
	129	printk(KERN_ERR "Could not ioremap uart%i\n", i);
	130	continue;
	131	}
f577ffd7 TL	132	switch (i) {
	133	case 0:
	134	uart1_ck = clk_get(NULL, "uart1_ck");
	135	if (IS_ERR(uart1_ck))
	136	printk("Could not get uart1_ck\n");
	137	else {
30ff720b	138	clk_enable(uart1_ck);
65d873ca	139	if (cpu_is_omap15xx())
f577ffd7 TL	140	clk_set_rate(uart1_ck, 12000000);
f577ffd7 TL	141	}
f577ffd7 TL	142	break;
	143	case 1:
	144	uart2_ck = clk_get(NULL, "uart2_ck");
	145	if (IS_ERR(uart2_ck))
	146	printk("Could not get uart2_ck\n");
	147	else {
30ff720b	148	clk_enable(uart2_ck);
65d873ca	149	if (cpu_is_omap15xx())
f577ffd7 TL	150	clk_set_rate(uart2_ck, 12000000);
	151	else
	152	clk_set_rate(uart2_ck, 48000000);
	153	}
f577ffd7 TL	154	break;
	155	case 2:
	156	uart3_ck = clk_get(NULL, "uart3_ck");
	157	if (IS_ERR(uart3_ck))
	158	printk("Could not get uart3_ck\n");
	159	else {
30ff720b	160	clk_enable(uart3_ck);
65d873ca	161	if (cpu_is_omap15xx())
f577ffd7 TL	162	clk_set_rate(uart3_ck, 12000000);
f577ffd7 TL	163	}
f577ffd7 TL	164	break;
	165	}
	166	omap_serial_reset(&serial_platform_data[i]);
	167	}
	168	}
	169
7c38cf02 TL	170	#ifdef CONFIG_OMAP_SERIAL_WAKE
7c38cf02 TL	171
0cd61b68	172	static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
7c38cf02 TL	173	{
	174	/* Need to do something with serial port right after wake-up? */
	175	return IRQ_HANDLED;
	176	}
	177
	178	/*
	179	* Reroutes serial RX lines to GPIO lines for the duration of
	180	* sleep to allow waking up the device from serial port even
	181	* in deep sleep.
	182	*/
	183	void omap_serial_wake_trigger(int enable)
	184	{
	185	if (!cpu_is_omap16xx())
	186	return;
	187
	188	if (uart1_ck != NULL) {
	189	if (enable)
	190	omap_cfg_reg(V14_16XX_GPIO37);
	191	else
	192	omap_cfg_reg(V14_16XX_UART1_RX);
	193	}
	194	if (uart2_ck != NULL) {
	195	if (enable)
	196	omap_cfg_reg(R9_16XX_GPIO18);
	197	else
	198	omap_cfg_reg(R9_16XX_UART2_RX);
	199	}
	200	if (uart3_ck != NULL) {
	201	if (enable)
	202	omap_cfg_reg(L14_16XX_GPIO49);
	203	else
	204	omap_cfg_reg(L14_16XX_UART3_RX);
	205	}
	206	}
	207
	208	static void __init omap_serial_set_port_wakeup(int gpio_nr)
	209	{
	210	int ret;
	211
f2d18fea	212	ret = gpio_request(gpio_nr, "UART wake");
7c38cf02 TL	213	if (ret < 0) {
	214	printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
	215	gpio_nr);
	216	return;
	217	}
40e3925b	218	gpio_direction_input(gpio_nr);
15f74b03	219	ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
52e405ea	220	IRQF_TRIGGER_RISING, "serial wakeup", NULL);
7c38cf02	221	if (ret) {
f2d18fea	222	gpio_free(gpio_nr);
7c38cf02 TL	223	printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
	224	gpio_nr);
	225	return;
	226	}
15f74b03	227	enable_irq_wake(gpio_to_irq(gpio_nr));
7c38cf02 TL	228	}
	229
	230	static int __init omap_serial_wakeup_init(void)
	231	{
	232	if (!cpu_is_omap16xx())
	233	return 0;
	234
	235	if (uart1_ck != NULL)
	236	omap_serial_set_port_wakeup(37);
	237	if (uart2_ck != NULL)
	238	omap_serial_set_port_wakeup(18);
	239	if (uart3_ck != NULL)
	240	omap_serial_set_port_wakeup(49);
	241
	242	return 0;
	243	}
	244	late_initcall(omap_serial_wakeup_init);
	245
	246	#endif /* CONFIG_OMAP_SERIAL_WAKE */
	247
f577ffd7 TL	248	static int __init omap_init(void)
	249	{
	250	return platform_device_register(&serial_device);
	251	}
	252	arch_initcall(omap_init);