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Merge branch 'audit.b64' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit...
[net-next-2.6.git] / arch / arm / mach-mx5 / board-mx51_babbage.c
CommitLineData
b996b583 1/*
64f102b6 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
b996b583
AK		 3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
f00b771a 15#include <linux/i2c.h>
231637f5
DN		 16#include <linux/gpio.h>
17#include <linux/delay.h>
18#include <linux/io.h>
2ba5a2c0 19#include <linux/fsl_devices.h>
3efee47d 20#include <linux/fec.h>
f2d36ecb
DN		 21#include <linux/gpio_keys.h>
22#include <linux/input.h>
b996b583
AK		 23
24#include <mach/common.h>
25#include <mach/hardware.h>
b996b583 26#include <mach/iomux-mx51.h>
231637f5 27#include <mach/mxc_ehci.h>
b996b583
AK		 28
29#include <asm/irq.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
04b73b15 35#include "devices-imx51.h"
b996b583 36#include "devices.h"
64f102b6 37#include "cpu_op-mx51.h"
b996b583 38
231637f5
DN		 39#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
40#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
3efee47d
FE		 41#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
42#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
f2d36ecb 43#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
231637f5
DN		 44
45/* USB_CTRL_1 */
46#define MX51_USB_CTRL_1_OFFSET 0x10
47#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48
49#define MX51_USB_PLLDIV_12_MHZ 0x00
50#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
51#define MX51_USB_PLL_DIV_24_MHZ 0x02
52
f2d36ecb
DN		 53static struct gpio_keys_button babbage_buttons[] = {
54 {
55 .gpio = BABBAGE_POWER_KEY,
56 .code = BTN_0,
57 .desc = "PWR",
58 .active_low = 1,
59 .wakeup = 1,
60 },
61};
62
63static const struct gpio_keys_platform_data imx_button_data __initconst = {
64 .buttons = babbage_buttons,
65 .nbuttons = ARRAY_SIZE(babbage_buttons),
66};
67
b996b583
AK		 68static struct pad_desc mx51babbage_pads[] = {
69 /* UART1 */
70 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD,
72 MX51_PAD_UART1_RTS__UART1_RTS,
73 MX51_PAD_UART1_CTS__UART1_CTS,
74
75 /* UART2 */
76 MX51_PAD_UART2_RXD__UART2_RXD,
77 MX51_PAD_UART2_TXD__UART2_TXD,
78
79 /* UART3 */
80 MX51_PAD_EIM_D25__UART3_RXD,
81 MX51_PAD_EIM_D26__UART3_TXD,
82 MX51_PAD_EIM_D27__UART3_RTS,
83 MX51_PAD_EIM_D24__UART3_CTS,
231637f5 84
f00b771a
DN		 85 /* I2C1 */
86 MX51_PAD_EIM_D16__I2C1_SDA,
87 MX51_PAD_EIM_D19__I2C1_SCL,
88
89 /* I2C2 */
90 MX51_PAD_KEY_COL4__I2C2_SCL,
91 MX51_PAD_KEY_COL5__I2C2_SDA,
92
93 /* HSI2C */
94 MX51_PAD_I2C1_CLK__HSI2C_CLK,
95 MX51_PAD_I2C1_DAT__HSI2C_DAT,
96
231637f5
DN		 97 /* USB HOST1 */
98 MX51_PAD_USBH1_CLK__USBH1_CLK,
99 MX51_PAD_USBH1_DIR__USBH1_DIR,
100 MX51_PAD_USBH1_NXT__USBH1_NXT,
101 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
102 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
103 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
104 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
105 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
106 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
107 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
108 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109
110 /* USB HUB reset line*/
68d03da2 111 MX51_PAD_GPIO_1_7__GPIO_1_7,
3efee47d
FE		 112
113 /* FEC */
114 MX51_PAD_EIM_EB2__FEC_MDIO,
115 MX51_PAD_EIM_EB3__FEC_RDAT1,
116 MX51_PAD_EIM_CS2__FEC_RDAT2,
117 MX51_PAD_EIM_CS3__FEC_RDAT3,
118 MX51_PAD_EIM_CS4__FEC_RX_ER,
119 MX51_PAD_EIM_CS5__FEC_CRS,
120 MX51_PAD_NANDF_RB2__FEC_COL,
121 MX51_PAD_NANDF_RB3__FEC_RXCLK,
122 MX51_PAD_NANDF_RB6__FEC_RDAT0,
123 MX51_PAD_NANDF_RB7__FEC_TDAT0,
124 MX51_PAD_NANDF_CS2__FEC_TX_ER,
125 MX51_PAD_NANDF_CS3__FEC_MDC,
126 MX51_PAD_NANDF_CS4__FEC_TDAT1,
127 MX51_PAD_NANDF_CS5__FEC_TDAT2,
128 MX51_PAD_NANDF_CS6__FEC_TDAT3,
129 MX51_PAD_NANDF_CS7__FEC_TX_EN,
130 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
131
132 /* FEC PHY reset line */
133 MX51_PAD_EIM_A20__GPIO_2_14,
7223066c
SG		 134
135 /* SD 1 */
136 MX51_PAD_SD1_CMD__SD1_CMD,
137 MX51_PAD_SD1_CLK__SD1_CLK,
138 MX51_PAD_SD1_DATA0__SD1_DATA0,
139 MX51_PAD_SD1_DATA1__SD1_DATA1,
140 MX51_PAD_SD1_DATA2__SD1_DATA2,
141 MX51_PAD_SD1_DATA3__SD1_DATA3,
142
143 /* SD 2 */
144 MX51_PAD_SD2_CMD__SD2_CMD,
145 MX51_PAD_SD2_CLK__SD2_CLK,
146 MX51_PAD_SD2_DATA0__SD2_DATA0,
147 MX51_PAD_SD2_DATA1__SD2_DATA1,
148 MX51_PAD_SD2_DATA2__SD2_DATA2,
149 MX51_PAD_SD2_DATA3__SD2_DATA3,
b996b583
AK		 150};
151
152/* Serial ports */
153#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
04b73b15 154static const struct imxuart_platform_data uart_pdata __initconst = {
b996b583
AK		 155 .flags = IMXUART_HAVE_RTSCTS,
156};
157
158static inline void mxc_init_imx_uart(void)
159{
04b73b15
UKK		 160 imx51_add_imx_uart(0, &uart_pdata);
161 imx51_add_imx_uart(1, &uart_pdata);
162 imx51_add_imx_uart(2, &uart_pdata);
b996b583
AK		 163}
164#else /* !SERIAL_IMX */
165static inline void mxc_init_imx_uart(void)
166{
167}
168#endif /* SERIAL_IMX */
169
44505c07 170static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
f00b771a
DN		 171 .bitrate = 100000,
172};
173
174static struct imxi2c_platform_data babbage_hsi2c_data = {
175 .bitrate = 400000,
176};
177
231637f5
DN		 178static int gpio_usbh1_active(void)
179{
180 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
d6b273bf 181 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
231637f5
DN		 182 int ret;
183
184 /* Set USBH1_STP to GPIO and toggle it */
185 mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
186 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
187
188 if (ret) {
189 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
190 return ret;
191 }
192 gpio_direction_output(BABBAGE_USBH1_STP, 0);
193 gpio_set_value(BABBAGE_USBH1_STP, 1);
194 msleep(100);
195 gpio_free(BABBAGE_USBH1_STP);
d6b273bf
DN		 196
197 /* De-assert USB PHY RESETB */
198 mxc_iomux_v3_setup_pad(&phyreset_gpio);
199 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
200
201 if (ret) {
202 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
203 return ret;
204 }
205 gpio_direction_output(BABBAGE_PHY_RESET, 1);
231637f5
DN		 206 return 0;
207}
208
209static inline void babbage_usbhub_reset(void)
210{
211 int ret;
212
213 /* Bring USB hub out of reset */
214 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
215 if (ret) {
216 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
217 return;
218 }
219 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
220
221 /* USB HUB RESET - De-assert USB HUB RESET_N */
222 msleep(1);
223 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
224 msleep(1);
225 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
226}
227
3efee47d
FE		 228static inline void babbage_fec_reset(void)
229{
230 int ret;
231
232 /* reset FEC PHY */
233 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
234 if (ret) {
235 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
236 return;
237 }
238 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
239 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
240 msleep(1);
241 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
242}
243
231637f5
DN		 244/* This function is board specific as the bit mask for the plldiv will also
245be different for other Freescale SoCs, thus a common bitmask is not
246possible and cannot get place in /plat-mxc/ehci.c.*/
247static int initialize_otg_port(struct platform_device *pdev)
248{
249 u32 v;
250 void __iomem *usb_base;
e7a895bf 251 void __iomem *usbother_base;
231637f5
DN		 252
253 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
254 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
255
256 /* Set the PHY clock to 19.2MHz */
257 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
258 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
259 v |= MX51_USB_PLL_DIV_19_2_MHZ;
260 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
261 iounmap(usb_base);
262 return 0;
263}
264
265static int initialize_usbh1_port(struct platform_device *pdev)
266{
267 u32 v;
268 void __iomem *usb_base;
e7a895bf 269 void __iomem *usbother_base;
231637f5
DN		 270
271 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
272 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
273
274 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
275 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
276 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
277 iounmap(usb_base);
278 return 0;
279}
280
281static struct mxc_usbh_platform_data dr_utmi_config = {
282 .init = initialize_otg_port,
283 .portsc = MXC_EHCI_UTMI_16BIT,
284 .flags = MXC_EHCI_INTERNAL_PHY,
285};
286
2ba5a2c0
DN		 287static struct fsl_usb2_platform_data usb_pdata = {
288 .operating_mode = FSL_USB2_DR_DEVICE,
289 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
290};
291
231637f5
DN		 292static struct mxc_usbh_platform_data usbh1_config = {
293 .init = initialize_usbh1_port,
294 .portsc = MXC_EHCI_MODE_ULPI,
295 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
296};
297
2ba5a2c0
DN		 298static int otg_mode_host;
299
300static int __init babbage_otg_mode(char *options)
301{
302 if (!strcmp(options, "host"))
303 otg_mode_host = 1;
304 else if (!strcmp(options, "device"))
305 otg_mode_host = 0;
306 else
307 pr_info("otg_mode neither \"host\" nor \"device\". "
308 "Defaulting to device\n");
309 return 0;
310}
311__setup("otg_mode=", babbage_otg_mode);
312
b996b583
AK		 313/*
314 * Board specific initialization.
315 */
316static void __init mxc_board_init(void)
317{
231637f5 318 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
f2d36ecb 319 struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
231637f5 320
64f102b6
YS		 321#if defined(CONFIG_CPU_FREQ_IMX)
322 get_cpu_op = mx51_get_cpu_op;
323#endif
b996b583
AK		 324 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
325 ARRAY_SIZE(mx51babbage_pads));
326 mxc_init_imx_uart();
3efee47d 327 babbage_fec_reset();
6bd96f3c 328 imx51_add_fec(NULL);
231637f5 329
f2d36ecb
DN		 330 /* Set the PAD settings for the pwr key. */
331 power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
332 mxc_iomux_v3_setup_pad(&power_key);
333 imx51_add_gpio_keys(&imx_button_data);
334
44505c07
UKK		 335 imx51_add_imx_i2c(0, &babbage_i2c_data);
336 imx51_add_imx_i2c(1, &babbage_i2c_data);
f00b771a
DN		 337 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
338
2ba5a2c0
DN		 339 if (otg_mode_host)
340 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
341 else {
342 initialize_otg_port(NULL);
343 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
344 }
231637f5
DN		 345
346 gpio_usbh1_active();
347 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
348 /* setback USBH1_STP to be function */
349 mxc_iomux_v3_setup_pad(&usbh1stp);
350 babbage_usbhub_reset();
7223066c
SG		 351
352 imx51_add_esdhc(0, NULL);
353 imx51_add_esdhc(1, NULL);
b996b583
AK		 354}
355
356static void __init mx51_babbage_timer_init(void)
357{
82d52a19 358 mx51_clocks_init(32768, 24000000, 22579200, 0);
b996b583
AK		 359}
360
361static struct sys_timer mxc_timer = {
362 .init = mx51_babbage_timer_init,
363};
364
365MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
366 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
e16ddb3a 367 .boot_params = MX51_PHYS_OFFSET + 0x100,
b996b583
AK		 368 .map_io = mx51_map_io,
369 .init_irq = mx51_init_irq,
370 .init_machine = mxc_board_init,
371 .timer = &mxc_timer,
372MACHINE_END
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