[net-next-2.6.git] / arch / arm / mach-mx3 / mach-pcm043.c

/*
 *  Copyright (C) 2009 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>

#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smc911x.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
#include <mach/i2c.h>
#endif
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
#include <mach/ssi.h>

#include "devices.h"

static const struct fb_videomode fb_modedb[] = {
	{
		/* 240x320 @ 60 Hz */
		.name		= "Sharp-LQ035Q7",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "TX090",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 38255,
		.left_margin	= 144,
		.right_margin	= 0,
		.upper_margin	= 7,
		.lower_margin	= 40,
		.hsync_len	= 96,
		.vsync_len	= 1,
		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	},
};

static struct ipu_platform_data mx3_ipu_data = {
	.irq_base = MXC_IPU_IRQ_START,
};

static struct mx3fb_platform_data mx3fb_pdata = {
	.dma_dev	= &mx3_ipu.dev,
	.name		= "Sharp-LQ035Q7",
	.mode		= fb_modedb,
	.num_modes	= ARRAY_SIZE(fb_modedb),
};

static struct physmap_flash_data pcm043_flash_data = {
	.width  = 2,
};

static struct resource pcm043_flash_resource = {
	.start	= 0xa0000000,
	.end	= 0xa1ffffff,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device pcm043_flash = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev	= {
		.platform_data  = &pcm043_flash_data,
	},
	.resource = &pcm043_flash_resource,
	.num_resources = 1,
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
static struct imxi2c_platform_data pcm043_i2c_1_data = {
	.bitrate = 50000,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static struct i2c_board_info pcm043_i2c_devices[] = {
       {
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	}, {
		I2C_BOARD_INFO("pcf8563", 0x51),
	}
};
#endif

static struct platform_device *devices[] __initdata = {
	&pcm043_flash,
	&mxc_fec_device,
	&imx_wdt_device0,
};

static struct pad_desc pcm043_pads[] = {
	/* UART1 */
	MX35_PAD_CTS1__UART1_CTS,
	MX35_PAD_RTS1__UART1_RTS,
	MX35_PAD_TXD1__UART1_TXD_MUX,
	MX35_PAD_RXD1__UART1_RXD_MUX,
	/* UART2 */
	MX35_PAD_CTS2__UART2_CTS,
	MX35_PAD_RTS2__UART2_RTS,
	MX35_PAD_TXD2__UART2_TXD_MUX,
	MX35_PAD_RXD2__UART2_RXD_MUX,
	/* FEC */
	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	MX35_PAD_FEC_COL__FEC_COL,
	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	MX35_PAD_FEC_MDC__FEC_MDC,
	MX35_PAD_FEC_MDIO__FEC_MDIO,
	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	MX35_PAD_FEC_CRS__FEC_CRS,
	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	/* I2C1 */
	MX35_PAD_I2C1_CLK__I2C1_SCL,
	MX35_PAD_I2C1_DAT__I2C1_SDA,
	/* Display */
	MX35_PAD_LD0__IPU_DISPB_DAT_0,
	MX35_PAD_LD1__IPU_DISPB_DAT_1,
	MX35_PAD_LD2__IPU_DISPB_DAT_2,
	MX35_PAD_LD3__IPU_DISPB_DAT_3,
	MX35_PAD_LD4__IPU_DISPB_DAT_4,
	MX35_PAD_LD5__IPU_DISPB_DAT_5,
	MX35_PAD_LD6__IPU_DISPB_DAT_6,
	MX35_PAD_LD7__IPU_DISPB_DAT_7,
	MX35_PAD_LD8__IPU_DISPB_DAT_8,
	MX35_PAD_LD9__IPU_DISPB_DAT_9,
	MX35_PAD_LD10__IPU_DISPB_DAT_10,
	MX35_PAD_LD11__IPU_DISPB_DAT_11,
	MX35_PAD_LD12__IPU_DISPB_DAT_12,
	MX35_PAD_LD13__IPU_DISPB_DAT_13,
	MX35_PAD_LD14__IPU_DISPB_DAT_14,
	MX35_PAD_LD15__IPU_DISPB_DAT_15,
	MX35_PAD_LD16__IPU_DISPB_DAT_16,
	MX35_PAD_LD17__IPU_DISPB_DAT_17,
	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
	/* gpio */
	MX35_PAD_ATA_CS0__GPIO2_6,
	/* USB host */
	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
	/* SSI */
	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
};

#define AC97_GPIO_TXFS	(1 * 32 + 31)
#define AC97_GPIO_TXD	(1 * 32 + 28)
#define AC97_GPIO_RESET	(1 * 32 + 0)

static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	int ret;

	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	if (ret) {
		printk("failed to get GPIO_TXFS: %d\n", ret);
		return;
	}

	mxc_iomux_v3_setup_pad(&txfs_gpio);

	/* warm reset */
	gpio_direction_output(AC97_GPIO_TXFS, 1);
	udelay(2);
	gpio_set_value(AC97_GPIO_TXFS, 0);

	gpio_free(AC97_GPIO_TXFS);
	mxc_iomux_v3_setup_pad(&txfs);
}

static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
	struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
	struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
	int ret;

	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	if (ret)
		goto err1;

	ret = gpio_request(AC97_GPIO_TXD, "SSI");
	if (ret)
		goto err2;

	ret = gpio_request(AC97_GPIO_RESET, "SSI");
	if (ret)
		goto err3;

	mxc_iomux_v3_setup_pad(&txfs_gpio);
	mxc_iomux_v3_setup_pad(&txd_gpio);
	mxc_iomux_v3_setup_pad(&reset_gpio);

	gpio_direction_output(AC97_GPIO_TXFS, 0);
	gpio_direction_output(AC97_GPIO_TXD, 0);

	/* cold reset */
	gpio_direction_output(AC97_GPIO_RESET, 0);
	udelay(10);
	gpio_direction_output(AC97_GPIO_RESET, 1);

	mxc_iomux_v3_setup_pad(&txd);
	mxc_iomux_v3_setup_pad(&txfs);

	gpio_free(AC97_GPIO_RESET);
err3:
	gpio_free(AC97_GPIO_TXD);
err2:
	gpio_free(AC97_GPIO_TXFS);
err1:
	if (ret)
		printk("%s failed with %d\n", __func__, ret);
	mdelay(1);
}

static struct imx_ssi_platform_data pcm043_ssi_pdata = {
	.ac97_reset = pcm043_ac97_cold_reset,
	.ac97_warm_reset = pcm043_ac97_warm_reset,
	.flags = IMX_SSI_USE_AC97,
};

static struct mxc_nand_platform_data pcm037_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
	.portsc	= MXC_EHCI_MODE_UTMI,
	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
};

static struct mxc_usbh_platform_data usbh1_pdata = {
	.portsc	= MXC_EHCI_MODE_SERIAL,
	.flags	= MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
		  MXC_EHCI_IPPUE_DOWN,
};
#endif

static struct fsl_usb2_platform_data otg_device_pdata = {
	.operating_mode = FSL_USB2_DR_DEVICE,
	.phy_mode       = FSL_USB2_PHY_UTMI,
};

static int otg_mode_host;

static int __init pcm043_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = 1;
	else if (!strcmp(options, "device"))
		otg_mode_host = 0;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 0;
}
__setup("otg_mode=", pcm043_otg_mode);

/*
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));

	mxc_audmux_v2_configure_port(3,
			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
			MXC_AUDMUX_V2_PTCR_TFSDIR,
			MXC_AUDMUX_V2_PDCR_RXDSEL(0));

	mxc_audmux_v2_configure_port(0,
			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
			MXC_AUDMUX_V2_PDCR_RXDSEL(3));

	platform_add_devices(devices, ARRAY_SIZE(devices));

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
	mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);

	mxc_register_device(&mxc_uart_device1, &uart_pdata);

#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
	i2c_register_board_info(0, pcm043_i2c_devices,
			ARRAY_SIZE(pcm043_i2c_devices));

	mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
#endif

	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	mxc_register_device(&mx3_fb, &mx3fb_pdata);

#if defined(CONFIG_USB_ULPI)
	if (otg_mode_host) {
		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);

		mxc_register_device(&mxc_otg_host, &otg_pdata);
	}

	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
#endif
	if (!otg_mode_host)
		mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);

}

static void __init pcm043_timer_init(void)
{
	mx35_clocks_init();
}

struct sys_timer pcm043_timer = {
	.init	= pcm043_timer_init,
};

MACHINE_START(PCM043, "Phytec Phycore pcm043")
	/* Maintainer: Pengutronix */
	.phys_io	= MX35_AIPS1_BASE_ADDR,
	.io_pg_offst	= ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx35_map_io,
	.init_irq       = mx35_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &pcm043_timer,
MACHINE_END
Commit	Line	Data
54df5268 SH	1	/*
	2	* Copyright (C) 2009 Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21
	22	#include <linux/platform_device.h>
	23	#include <linux/mtd/physmap.h>
	24	#include <linux/mtd/plat-ram.h>
	25	#include <linux/memory.h>
	26	#include <linux/gpio.h>
	27	#include <linux/smc911x.h>
	28	#include <linux/interrupt.h>
d2831d1f	29	#include <linux/delay.h>
54df5268 SH	30	#include <linux/i2c.h>
54df5268 SH	31	#include <linux/i2c/at24.h>
cb2dc111 SH	32	#include <linux/usb/otg.h>
	33	#include <linux/usb/ulpi.h>
	34	#include <linux/fsl_devices.h>
54df5268 SH	35
	36	#include <asm/mach-types.h>
	37	#include <asm/mach/arch.h>
	38	#include <asm/mach/time.h>
	39	#include <asm/mach/map.h>
	40
	41	#include <mach/hardware.h>
	42	#include <mach/common.h>
	43	#include <mach/imx-uart.h>
	44	#if defined CONFIG_I2C_IMX \|\| defined CONFIG_I2C_IMX_MODULE
	45	#include <mach/i2c.h>
	46	#endif
	47	#include <mach/iomux-mx35.h>
	48	#include <mach/ipu.h>
	49	#include <mach/mx3fb.h>
4f43c2ed	50	#include <mach/mxc_nand.h>
cb2dc111 SH	51	#include <mach/mxc_ehci.h>
cb2dc111 SH	52	#include <mach/ulpi.h>
d2831d1f SH	53	#include <mach/audmux.h>
d2831d1f SH	54	#include <mach/ssi.h>
54df5268 SH	55
	56	#include "devices.h"
	57
	58	static const struct fb_videomode fb_modedb[] = {
	59	{
	60	/* 240x320 @ 60 Hz */
	61	.name = "Sharp-LQ035Q7",
	62	.refresh = 60,
	63	.xres = 240,
	64	.yres = 320,
	65	.pixclock = 185925,
	66	.left_margin = 9,
	67	.right_margin = 16,
	68	.upper_margin = 7,
	69	.lower_margin = 9,
	70	.hsync_len = 1,
	71	.vsync_len = 1,
	72	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_SHARP_MODE \| FB_SYNC_CLK_INVERT \| FB_SYNC_CLK_IDLE_EN,
	73	.vmode = FB_VMODE_NONINTERLACED,
	74	.flag = 0,
	75	}, {
	76	/* 240x320 @ 60 Hz */
	77	.name = "TX090",
	78	.refresh = 60,
	79	.xres = 240,
	80	.yres = 320,
	81	.pixclock = 38255,
	82	.left_margin = 144,
	83	.right_margin = 0,
	84	.upper_margin = 7,
	85	.lower_margin = 40,
	86	.hsync_len = 96,
	87	.vsync_len = 1,
	88	.sync = FB_SYNC_VERT_HIGH_ACT \| FB_SYNC_OE_ACT_HIGH,
	89	.vmode = FB_VMODE_NONINTERLACED,
	90	.flag = 0,
	91	},
	92	};
	93
	94	static struct ipu_platform_data mx3_ipu_data = {
	95	.irq_base = MXC_IPU_IRQ_START,
	96	};
	97
	98	static struct mx3fb_platform_data mx3fb_pdata = {
	99	.dma_dev = &mx3_ipu.dev,
	100	.name = "Sharp-LQ035Q7",
	101	.mode = fb_modedb,
	102	.num_modes = ARRAY_SIZE(fb_modedb),
	103	};
	104
	105	static struct physmap_flash_data pcm043_flash_data = {
	106	.width = 2,
	107	};
	108
	109	static struct resource pcm043_flash_resource = {
	110	.start = 0xa0000000,
	111	.end = 0xa1ffffff,
	112	.flags = IORESOURCE_MEM,
	113	};
	114
	115	static struct platform_device pcm043_flash = {
	116	.name = "physmap-flash",
	117	.id = 0,
	118	.dev = {
119	.platform_data = &pcm043_flash_data,
120	},
121	.resource = &pcm043_flash_resource,
122	.num_resources = 1,
123	};
124
125	static struct imxuart_platform_data uart_pdata = {
126	.flags = IMXUART_HAVE_RTSCTS,
127	};
128
129	#if defined CONFIG_I2C_IMX \|\| defined CONFIG_I2C_IMX_MODULE
130	static struct imxi2c_platform_data pcm043_i2c_1_data = {
131	.bitrate = 50000,
132	};
133
134	static struct at24_platform_data board_eeprom = {
135	.byte_len = 4096,
136	.page_size = 32,
137	.flags = AT24_FLAG_ADDR16,
138	};
139
140	static struct i2c_board_info pcm043_i2c_devices[] = {
141	{
142	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
143	.platform_data = &board_eeprom,
144	}, {
cf87a6e2	145	I2C_BOARD_INFO("pcf8563", 0x51),
54df5268 SH	146	}
	147	};
	148	#endif
	149
	150	static struct platform_device *devices[] __initdata = {
	151	&pcm043_flash,
	152	&mxc_fec_device,
3170ba54	153	&imx_wdt_device0,
54df5268 SH	154	};
	155
	156	static struct pad_desc pcm043_pads[] = {
	157	/* UART1 */
	158	MX35_PAD_CTS1__UART1_CTS,
	159	MX35_PAD_RTS1__UART1_RTS,
	160	MX35_PAD_TXD1__UART1_TXD_MUX,
	161	MX35_PAD_RXD1__UART1_RXD_MUX,
	162	/* UART2 */
	163	MX35_PAD_CTS2__UART2_CTS,
	164	MX35_PAD_RTS2__UART2_RTS,
	165	MX35_PAD_TXD2__UART2_TXD_MUX,
	166	MX35_PAD_RXD2__UART2_RXD_MUX,
	167	/* FEC */
	168	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	169	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	170	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	171	MX35_PAD_FEC_COL__FEC_COL,
	172	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	173	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	174	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	175	MX35_PAD_FEC_MDC__FEC_MDC,
	176	MX35_PAD_FEC_MDIO__FEC_MDIO,
	177	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	178	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	179	MX35_PAD_FEC_CRS__FEC_CRS,
	180	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	181	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	182	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	183	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	184	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	185	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	186	/* I2C1 */
	187	MX35_PAD_I2C1_CLK__I2C1_SCL,
	188	MX35_PAD_I2C1_DAT__I2C1_SDA,
	189	/* Display */
	190	MX35_PAD_LD0__IPU_DISPB_DAT_0,
	191	MX35_PAD_LD1__IPU_DISPB_DAT_1,
	192	MX35_PAD_LD2__IPU_DISPB_DAT_2,
	193	MX35_PAD_LD3__IPU_DISPB_DAT_3,
	194	MX35_PAD_LD4__IPU_DISPB_DAT_4,
	195	MX35_PAD_LD5__IPU_DISPB_DAT_5,
	196	MX35_PAD_LD6__IPU_DISPB_DAT_6,
	197	MX35_PAD_LD7__IPU_DISPB_DAT_7,
	198	MX35_PAD_LD8__IPU_DISPB_DAT_8,
	199	MX35_PAD_LD9__IPU_DISPB_DAT_9,
	200	MX35_PAD_LD10__IPU_DISPB_DAT_10,
	201	MX35_PAD_LD11__IPU_DISPB_DAT_11,
	202	MX35_PAD_LD12__IPU_DISPB_DAT_12,
	203	MX35_PAD_LD13__IPU_DISPB_DAT_13,
	204	MX35_PAD_LD14__IPU_DISPB_DAT_14,
	205	MX35_PAD_LD15__IPU_DISPB_DAT_15,
	206	MX35_PAD_LD16__IPU_DISPB_DAT_16,
	207	MX35_PAD_LD17__IPU_DISPB_DAT_17,
	208	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
	209	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
	210	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
	211	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
	212	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
	213	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
	214	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
8d5c1ed3 LF	215	/* gpio */
8d5c1ed3 LF	216	MX35_PAD_ATA_CS0__GPIO2_6,
cb2dc111 SH	217	/* USB host */
	218	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
	219	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
d2831d1f SH	220	/* SSI */
	221	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
	222	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
	223	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
	224	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
	225	};
	226
	227	#define AC97_GPIO_TXFS (1 * 32 + 31)
	228	#define AC97_GPIO_TXD (1 * 32 + 28)
	229	#define AC97_GPIO_RESET (1 * 32 + 0)
	230
	231	static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
	232	{
	233	struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	234	struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	235	int ret;
	236
	237	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	238	if (ret) {
	239	printk("failed to get GPIO_TXFS: %d\n", ret);
	240	return;
	241	}
	242
	243	mxc_iomux_v3_setup_pad(&txfs_gpio);
	244
	245	/* warm reset */
	246	gpio_direction_output(AC97_GPIO_TXFS, 1);
	247	udelay(2);
	248	gpio_set_value(AC97_GPIO_TXFS, 0);
	249
	250	gpio_free(AC97_GPIO_TXFS);
	251	mxc_iomux_v3_setup_pad(&txfs);
	252	}
	253
	254	static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
	255	{
	256	struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	257	struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	258	struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
	259	struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
	260	struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
	261	int ret;
	262
	263	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	264	if (ret)
	265	goto err1;
	266
	267	ret = gpio_request(AC97_GPIO_TXD, "SSI");
	268	if (ret)
	269	goto err2;
	270
	271	ret = gpio_request(AC97_GPIO_RESET, "SSI");
	272	if (ret)
	273	goto err3;
	274
	275	mxc_iomux_v3_setup_pad(&txfs_gpio);
	276	mxc_iomux_v3_setup_pad(&txd_gpio);
	277	mxc_iomux_v3_setup_pad(&reset_gpio);
	278
	279	gpio_direction_output(AC97_GPIO_TXFS, 0);
	280	gpio_direction_output(AC97_GPIO_TXD, 0);
	281
	282	/* cold reset */
	283	gpio_direction_output(AC97_GPIO_RESET, 0);
284	udelay(10);
285	gpio_direction_output(AC97_GPIO_RESET, 1);
286
287	mxc_iomux_v3_setup_pad(&txd);
288	mxc_iomux_v3_setup_pad(&txfs);
289
290	gpio_free(AC97_GPIO_RESET);
291	err3:
292	gpio_free(AC97_GPIO_TXD);
293	err2:
294	gpio_free(AC97_GPIO_TXFS);
295	err1:
296	if (ret)
297	printk("%s failed with %d\n", __func__, ret);
298	mdelay(1);
299	}
300
301	static struct imx_ssi_platform_data pcm043_ssi_pdata = {
302	.ac97_reset = pcm043_ac97_cold_reset,
303	.ac97_warm_reset = pcm043_ac97_warm_reset,
304	.flags = IMX_SSI_USE_AC97,
54df5268 SH	305	};
54df5268 SH	306
4f43c2ed SH	307	static struct mxc_nand_platform_data pcm037_nand_board_info = {
	308	.width = 1,
	309	.hw_ecc = 1,
	310	};
	311
c18e8fa5	312	#if defined(CONFIG_USB_ULPI)
cb2dc111 SH	313	static struct mxc_usbh_platform_data otg_pdata = {
	314	.portsc = MXC_EHCI_MODE_UTMI,
	315	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
	316	};
	317
	318	static struct mxc_usbh_platform_data usbh1_pdata = {
	319	.portsc = MXC_EHCI_MODE_SERIAL,
	320	.flags = MXC_EHCI_INTERFACE_SINGLE_UNI \| MXC_EHCI_INTERNAL_PHY \|
	321	MXC_EHCI_IPPUE_DOWN,
	322	};
c18e8fa5	323	#endif
cb2dc111 SH	324
	325	static struct fsl_usb2_platform_data otg_device_pdata = {
	326	.operating_mode = FSL_USB2_DR_DEVICE,
	327	.phy_mode = FSL_USB2_PHY_UTMI,
	328	};
	329
	330	static int otg_mode_host;
	331
	332	static int __init pcm043_otg_mode(char *options)
	333	{
	334	if (!strcmp(options, "host"))
	335	otg_mode_host = 1;
	336	else if (!strcmp(options, "device"))
	337	otg_mode_host = 0;
	338	else
	339	pr_info("otg_mode neither \"host\" nor \"device\". "
	340	"Defaulting to device\n");
	341	return 0;
	342	}
	343	__setup("otg_mode=", pcm043_otg_mode);
	344
54df5268 SH	345	/*
	346	* Board specific initialization.
	347	*/
	348	static void __init mxc_board_init(void)
	349	{
	350	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
	351
d2831d1f SH	352	mxc_audmux_v2_configure_port(3,
	353	MXC_AUDMUX_V2_PTCR_SYN \| /* 4wire mode */
	354	MXC_AUDMUX_V2_PTCR_TFSEL(0) \|
	355	MXC_AUDMUX_V2_PTCR_TFSDIR,
	356	MXC_AUDMUX_V2_PDCR_RXDSEL(0));
	357
	358	mxc_audmux_v2_configure_port(0,
	359	MXC_AUDMUX_V2_PTCR_SYN \| /* 4wire mode */
	360	MXC_AUDMUX_V2_PTCR_TCSEL(3) \|
	361	MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
	362	MXC_AUDMUX_V2_PDCR_RXDSEL(3));
	363
54df5268 SH	364	platform_add_devices(devices, ARRAY_SIZE(devices));
	365
	366	mxc_register_device(&mxc_uart_device0, &uart_pdata);
4f43c2ed	367	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
d2831d1f	368	mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
54df5268 SH	369
	370	mxc_register_device(&mxc_uart_device1, &uart_pdata);
	371
	372	#if defined CONFIG_I2C_IMX \|\| defined CONFIG_I2C_IMX_MODULE
	373	i2c_register_board_info(0, pcm043_i2c_devices,
	374	ARRAY_SIZE(pcm043_i2c_devices));
	375
	376	mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
	377	#endif
	378
	379	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	380	mxc_register_device(&mx3_fb, &mx3fb_pdata);
cb2dc111 SH	381
	382	#if defined(CONFIG_USB_ULPI)
	383	if (otg_mode_host) {
	384	otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
	385	USB_OTG_DRV_VBUS \| USB_OTG_DRV_VBUS_EXT);
	386
	387	mxc_register_device(&mxc_otg_host, &otg_pdata);
	388	}
	389
	390	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
	391	#endif
	392	if (!otg_mode_host)
	393	mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
	394
54df5268 SH	395	}
	396
	397	static void __init pcm043_timer_init(void)
	398	{
	399	mx35_clocks_init();
	400	}
	401
	402	struct sys_timer pcm043_timer = {
	403	.init = pcm043_timer_init,
	404	};
	405
	406	MACHINE_START(PCM043, "Phytec Phycore pcm043")
	407	/* Maintainer: Pengutronix */
f568dd7f UKK	408	.phys_io = MX35_AIPS1_BASE_ADDR,
f568dd7f UKK	409	.io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
34101237	410	.boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9	411	.map_io = mx35_map_io,
c5aa0ad0	412	.init_irq = mx35_init_irq,
54df5268 SH	413	.init_machine = mxc_board_init,
	414	.timer = &pcm043_timer,
	415	MACHINE_END
	416