[net-next-2.6.git] / arch / arm / mach-mx3 / mach-mx31lite.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *  Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/memory.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/mtd/physmap.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/page.h>
#include <asm/setup.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/board-mx31lite.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>

#include "devices-imx31.h"
#include "devices.h"

/*
 * This file contains the module-specific initialization routines.
 */

static unsigned int mx31lite_pins[] = {
	/* LAN9117 IRQ pin */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS1__SS1,
	MX31_PIN_CSPI2_SS2__SS2,
};

static const struct mxc_nand_platform_data
mx31lite_nand_board_info __initconst  = {
	.width = 1,
	.hw_ecc = 1,
};

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= MX31_CS4_BASE_ADDR,
		.end		= MX31_CS4_BASE_ADDR + 0x100,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IOMUX_TO_IRQ(MX31_PIN_SFS6),
		.end		= IOMUX_TO_IRQ(MX31_PIN_SFS6),
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * SPI
 *
 * The MC13783 is the only hard-wired SPI device on the module.
 */

static int spi_internal_chipselect[] = {
	MXC_SPI_CS(0),
};

static const struct spi_imx_master spi1_pdata __initconst = {
	.chipselect	= spi_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
};

static struct mc13783_platform_data mc13783_pdata __initdata = {
	.flags  = MC13783_USE_RTC |
		  MC13783_USE_REGULATOR,
};

static struct spi_board_info mc13783_spi_dev __initdata = {
	.modalias       = "mc13783",
	.max_speed_hz   = 1000000,
	.bus_num	= 1,
	.chip_select    = 0,
	.platform_data  = &mc13783_pdata,
	.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
};

/*
 * USB
 */

#if defined(CONFIG_USB_ULPI)
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

static int usbh2_init(struct platform_device *pdev)
{
	int pins[] = {
		MX31_PIN_USBH2_DATA0__USBH2_DATA0,
		MX31_PIN_USBH2_DATA1__USBH2_DATA1,
		MX31_PIN_USBH2_CLK__USBH2_CLK,
		MX31_PIN_USBH2_DIR__USBH2_DIR,
		MX31_PIN_USBH2_NXT__USBH2_NXT,
		MX31_PIN_USBH2_STP__USBH2_STP,
	};

	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");

	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);

	mxc_iomux_set_gpr(MUX_PGP_UH2, true);

	/* chip select */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
				"USBH2_CS");
	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);

	return 0;
}

static struct mxc_usbh_platform_data usbh2_pdata = {
	.init   = usbh2_init,
	.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
	.flags  = MXC_EHCI_POWER_PINS_ENABLED,
};
#endif

/*
 * NOR flash
 */

static struct physmap_flash_data nor_flash_data = {
	.width  = 2,
};

static struct resource nor_flash_resource = {
	.start  = 0xa0000000,
	.end    = 0xa1ffffff,
	.flags  = IORESOURCE_MEM,
};

static struct platform_device physmap_flash_device = {
	.name   = "physmap-flash",
	.id     = 0,
	.dev    = {
		.platform_data  = &nor_flash_data,
	},
	.resource = &nor_flash_resource,
	.num_resources = 1,
};


/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31lite_io_desc[] __initdata = {
	{
		.virtual = MX31_CS4_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length = MX31_CS4_SIZE,
		.type = MT_DEVICE
	}
};

/*
 * Set up static virtual mappings.
 */
void __init mx31lite_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
}

static int mx31lite_baseboard;
core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);

static void __init mxc_board_init(void)
{
	int ret;

	switch (mx31lite_baseboard) {
	case MX31LITE_NOBOARD:
		break;
	case MX31LITE_DB:
		mx31lite_db_init();
		break;
	default:
		printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
				mx31lite_baseboard);
	}

	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
				      "mx31lite");

	/* NOR and NAND flash */
	platform_device_register(&physmap_flash_device);
	imx31_add_mxc_nand(&mx31lite_nand_board_info);

	imx31_add_spi_imx1(&spi1_pdata);
	spi_register_board_info(&mc13783_spi_dev, 1);

#if defined(CONFIG_USB_ULPI)
	/* USB */
	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif

	/* SMSC9117 IRQ pin */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else {
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		platform_device_register(&smsc911x_device);
	}
}

static void __init mx31lite_timer_init(void)
{
	mx31_clocks_init(26000000);
}

struct sys_timer mx31lite_timer = {
	.init	= mx31lite_timer_init,
};

MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io        = MX31_AIPS1_BASE_ADDR,
	.io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31lite_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31lite_timer,
MACHINE_END
Commit	Line	Data
9a4cd7a5 DM	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
84677d11	5	* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
9a4cd7a5 DM	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
9a4cd7a5 DM	16	*/
	17
	18	#include <linux/types.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/memory.h>
3211705f ML	22	#include <linux/platform_device.h>
	23	#include <linux/gpio.h>
	24	#include <linux/smsc911x.h>
84677d11 DM	25	#include <linux/mfd/mc13783.h>
84677d11 DM	26	#include <linux/spi/spi.h>
a050c8e9 DM	27	#include <linux/usb/otg.h>
a050c8e9 DM	28	#include <linux/usb/ulpi.h>
6d3e6601	29	#include <linux/mtd/physmap.h>
9a4cd7a5	30
9a4cd7a5 DM	31	#include <asm/mach-types.h>
9a4cd7a5 DM	32	#include <asm/mach/arch.h>
9e8a30dc	33	#include <asm/mach/time.h>
9a4cd7a5	34	#include <asm/mach/map.h>
9a4cd7a5 DM	35	#include <asm/page.h>
9a4cd7a5 DM	36	#include <asm/setup.h>
84677d11 DM	37
	38	#include <mach/hardware.h>
	39	#include <mach/common.h>
a09e64fb	40	#include <mach/board-mx31lite.h>
a854b8ab	41	#include <mach/iomux-mx3.h>
3211705f	42	#include <mach/irqs.h>
a050c8e9 DM	43	#include <mach/mxc_ehci.h>
a050c8e9 DM	44	#include <mach/ulpi.h>
84677d11	45
a2ceeef5	46	#include "devices-imx31.h"
a854b8ab	47	#include "devices.h"
9a4cd7a5 DM	48
9a4cd7a5 DM	49	/*
b7d91a62	50	* This file contains the module-specific initialization routines.
9a4cd7a5 DM	51	*/
9a4cd7a5 DM	52
a854b8ab	53	static unsigned int mx31lite_pins[] = {
3211705f ML	54	/* LAN9117 IRQ pin */
3211705f ML	55	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
84677d11 DM	56	/* SPI 1 */
	57	MX31_PIN_CSPI2_SCLK__SCLK,
	58	MX31_PIN_CSPI2_MOSI__MOSI,
	59	MX31_PIN_CSPI2_MISO__MISO,
	60	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	61	MX31_PIN_CSPI2_SS0__SS0,
	62	MX31_PIN_CSPI2_SS1__SS1,
	63	MX31_PIN_CSPI2_SS2__SS2,
a854b8ab ML	64	};
a854b8ab ML	65
a2ceeef5 UKK	66	static const struct mxc_nand_platform_data
a2ceeef5 UKK	67	mx31lite_nand_board_info __initconst = {
183c7fff ML	68	.width = 1,
	69	.hw_ecc = 1,
	70	};
	71
3211705f ML	72	static struct smsc911x_platform_config smsc911x_config = {
	73	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	74	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	75	.flags = SMSC911X_USE_16BIT,
	76	};
	77
	78	static struct resource smsc911x_resources[] = {
3f4f54b4	79	{
f568dd7f UKK	80	.start = MX31_CS4_BASE_ADDR,
f568dd7f UKK	81	.end = MX31_CS4_BASE_ADDR + 0x100,
3211705f	82	.flags = IORESOURCE_MEM,
3f4f54b4	83	}, {
3211705f ML	84	.start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
	85	.end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
	86	.flags = IORESOURCE_IRQ,
	87	},
	88	};
	89
	90	static struct platform_device smsc911x_device = {
	91	.name = "smsc911x",
	92	.id = -1,
	93	.num_resources = ARRAY_SIZE(smsc911x_resources),
	94	.resource = smsc911x_resources,
	95	.dev = {
	96	.platform_data = &smsc911x_config,
	97	},
	98	};
	99
84677d11 DM	100	/*
	101	* SPI
	102	*
	103	* The MC13783 is the only hard-wired SPI device on the module.
	104	*/
	105
	106	static int spi_internal_chipselect[] = {
	107	MXC_SPI_CS(0),
	108	};
	109
06606ff1	110	static const struct spi_imx_master spi1_pdata __initconst = {
84677d11 DM	111	.chipselect = spi_internal_chipselect,
	112	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
	113	};
	114
	115	static struct mc13783_platform_data mc13783_pdata __initdata = {
	116	.flags = MC13783_USE_RTC \|
	117	MC13783_USE_REGULATOR,
	118	};
	119
	120	static struct spi_board_info mc13783_spi_dev __initdata = {
	121	.modalias = "mc13783",
	122	.max_speed_hz = 1000000,
	123	.bus_num = 1,
	124	.chip_select = 0,
	125	.platform_data = &mc13783_pdata,
	126	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	127	};
	128
a050c8e9 DM	129	/*
	130	* USB
	131	*/
	132
f9ffaa9c	133	#if defined(CONFIG_USB_ULPI)
a050c8e9 DM	134	#define USB_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \| \
	135	PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	136
	137	static int usbh2_init(struct platform_device *pdev)
	138	{
	139	int pins[] = {
	140	MX31_PIN_USBH2_DATA0__USBH2_DATA0,
	141	MX31_PIN_USBH2_DATA1__USBH2_DATA1,
	142	MX31_PIN_USBH2_CLK__USBH2_CLK,
	143	MX31_PIN_USBH2_DIR__USBH2_DIR,
	144	MX31_PIN_USBH2_NXT__USBH2_NXT,
	145	MX31_PIN_USBH2_STP__USBH2_STP,
	146	};
	147
	148	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
	149
	150	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	151	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	152	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	153	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	154	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	155	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	156	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	157	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	158	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	159	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	160	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	161	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
	162
	163	mxc_iomux_set_gpr(MUX_PGP_UH2, true);
	164
	165	/* chip select */
	166	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
	167	"USBH2_CS");
	168	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	169	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
	170
	171	return 0;
	172	}
	173
	174	static struct mxc_usbh_platform_data usbh2_pdata = {
	175	.init = usbh2_init,
	176	.portsc = MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT,
	177	.flags = MXC_EHCI_POWER_PINS_ENABLED,
	178	};
f9ffaa9c	179	#endif
a050c8e9	180
6d3e6601 DM	181	/*
	182	* NOR flash
	183	*/
	184
	185	static struct physmap_flash_data nor_flash_data = {
	186	.width = 2,
	187	};
	188
	189	static struct resource nor_flash_resource = {
	190	.start = 0xa0000000,
	191	.end = 0xa1ffffff,
	192	.flags = IORESOURCE_MEM,
	193	};
	194
	195	static struct platform_device physmap_flash_device = {
	196	.name = "physmap-flash",
	197	.id = 0,
	198	.dev = {
	199	.platform_data = &nor_flash_data,
	200	},
	201	.resource = &nor_flash_resource,
	202	.num_resources = 1,
	203	};
	204
	205
	206
9a4cd7a5 DM	207	/*
	208	* This structure defines the MX31 memory map.
	209	*/
	210	static struct map_desc mx31lite_io_desc[] __initdata = {
	211	{
f568dd7f UKK	212	.virtual = MX31_CS4_BASE_ADDR_VIRT,
	213	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
	214	.length = MX31_CS4_SIZE,
9a4cd7a5 DM	215	.type = MT_DEVICE
	216	}
	217	};
	218
	219	/*
	220	* Set up static virtual mappings.
	221	*/
	222	void __init mx31lite_map_io(void)
	223	{
cd4a05f9	224	mx31_map_io();
9a4cd7a5 DM	225	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
	226	}
	227
b7d91a62 DM	228	static int mx31lite_baseboard;
	229	core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
	230
9a4cd7a5 DM	231	static void __init mxc_board_init(void)
9a4cd7a5 DM	232	{
4f163eb8 SH	233	int ret;
4f163eb8 SH	234
b7d91a62 DM	235	switch (mx31lite_baseboard) {
	236	case MX31LITE_NOBOARD:
	237	break;
	238	case MX31LITE_DB:
	239	mx31lite_db_init();
	240	break;
	241	default:
	242	printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
	243	mx31lite_baseboard);
	244	}
	245
a854b8ab ML	246	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
	247	"mx31lite");
	248
6d3e6601 DM	249	/* NOR and NAND flash */
6d3e6601 DM	250	platform_device_register(&physmap_flash_device);
a2ceeef5	251	imx31_add_mxc_nand(&mx31lite_nand_board_info);
6d3e6601	252
06606ff1	253	imx31_add_spi_imx1(&spi1_pdata);
84677d11	254	spi_register_board_info(&mc13783_spi_dev, 1);
3211705f	255
f9ffaa9c	256	#if defined(CONFIG_USB_ULPI)
a050c8e9 DM	257	/* USB */
a050c8e9 DM	258	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97	259	ULPI_OTG_DRVVBUS \| ULPI_OTG_DRVVBUS_EXT);
a050c8e9 DM	260
a050c8e9 DM	261	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
f9ffaa9c	262	#endif
a050c8e9	263
3211705f	264	/* SMSC9117 IRQ pin */
4f163eb8 SH	265	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
	266	if (ret)
	267	pr_warning("could not get LAN irq gpio\n");
	268	else {
	269	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	270	platform_device_register(&smsc911x_device);
	271	}
9a4cd7a5 DM	272	}
9a4cd7a5 DM	273
9e8a30dc JB	274	static void __init mx31lite_timer_init(void)
9e8a30dc JB	275	{
30c730f8	276	mx31_clocks_init(26000000);
9e8a30dc JB	277	}
	278
	279	struct sys_timer mx31lite_timer = {
	280	.init = mx31lite_timer_init,
	281	};
	282
b7d91a62	283	MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
9a4cd7a5	284	/* Maintainer: Freescale Semiconductor, Inc. */
f568dd7f	285	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	286	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	287	.boot_params = MX3x_PHYS_OFFSET + 0x100,
9a4cd7a5	288	.map_io = mx31lite_map_io,
c5aa0ad0	289	.init_irq = mx31_init_irq,
9a4cd7a5	290	.init_machine = mxc_board_init,
9e8a30dc	291	.timer = &mx31lite_timer,
9a4cd7a5	292	MACHINE_END