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e3d13ff4 SH |
1 | /* |
2 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
17 | * Boston, MA 02110-1301, USA. | |
18 | */ | |
19 | ||
eb05bbeb | 20 | #include <linux/dma-mapping.h> |
e3d13ff4 SH |
21 | #include <linux/module.h> |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/serial.h> | |
07bd1a6c | 24 | #include <linux/gpio.h> |
a09e64fb | 25 | #include <mach/hardware.h> |
80b02c17 | 26 | #include <mach/irqs.h> |
45001e92 | 27 | #include <mach/common.h> |
a09e64fb | 28 | #include <mach/imx-uart.h> |
9c70e227 | 29 | #include <mach/mx3_camera.h> |
e3d13ff4 | 30 | |
87bbb197 SH |
31 | #include "devices.h" |
32 | ||
e3d13ff4 SH |
33 | static struct resource uart0[] = { |
34 | { | |
35 | .start = UART1_BASE_ADDR, | |
36 | .end = UART1_BASE_ADDR + 0x0B5, | |
37 | .flags = IORESOURCE_MEM, | |
38 | }, { | |
39 | .start = MXC_INT_UART1, | |
40 | .end = MXC_INT_UART1, | |
41 | .flags = IORESOURCE_IRQ, | |
42 | }, | |
43 | }; | |
44 | ||
5cf09421 | 45 | struct platform_device mxc_uart_device0 = { |
e3d13ff4 SH |
46 | .name = "imx-uart", |
47 | .id = 0, | |
48 | .resource = uart0, | |
49 | .num_resources = ARRAY_SIZE(uart0), | |
50 | }; | |
51 | ||
52 | static struct resource uart1[] = { | |
53 | { | |
54 | .start = UART2_BASE_ADDR, | |
55 | .end = UART2_BASE_ADDR + 0x0B5, | |
56 | .flags = IORESOURCE_MEM, | |
57 | }, { | |
58 | .start = MXC_INT_UART2, | |
59 | .end = MXC_INT_UART2, | |
60 | .flags = IORESOURCE_IRQ, | |
61 | }, | |
62 | }; | |
63 | ||
5cf09421 | 64 | struct platform_device mxc_uart_device1 = { |
e3d13ff4 SH |
65 | .name = "imx-uart", |
66 | .id = 1, | |
67 | .resource = uart1, | |
68 | .num_resources = ARRAY_SIZE(uart1), | |
69 | }; | |
70 | ||
71 | static struct resource uart2[] = { | |
72 | { | |
73 | .start = UART3_BASE_ADDR, | |
74 | .end = UART3_BASE_ADDR + 0x0B5, | |
75 | .flags = IORESOURCE_MEM, | |
76 | }, { | |
77 | .start = MXC_INT_UART3, | |
78 | .end = MXC_INT_UART3, | |
79 | .flags = IORESOURCE_IRQ, | |
80 | }, | |
81 | }; | |
82 | ||
5cf09421 | 83 | struct platform_device mxc_uart_device2 = { |
e3d13ff4 SH |
84 | .name = "imx-uart", |
85 | .id = 2, | |
86 | .resource = uart2, | |
87 | .num_resources = ARRAY_SIZE(uart2), | |
88 | }; | |
89 | ||
9536ff33 | 90 | #ifdef CONFIG_ARCH_MX31 |
e3d13ff4 SH |
91 | static struct resource uart3[] = { |
92 | { | |
93 | .start = UART4_BASE_ADDR, | |
94 | .end = UART4_BASE_ADDR + 0x0B5, | |
95 | .flags = IORESOURCE_MEM, | |
96 | }, { | |
97 | .start = MXC_INT_UART4, | |
98 | .end = MXC_INT_UART4, | |
99 | .flags = IORESOURCE_IRQ, | |
100 | }, | |
101 | }; | |
102 | ||
5cf09421 | 103 | struct platform_device mxc_uart_device3 = { |
e3d13ff4 SH |
104 | .name = "imx-uart", |
105 | .id = 3, | |
106 | .resource = uart3, | |
107 | .num_resources = ARRAY_SIZE(uart3), | |
108 | }; | |
109 | ||
110 | static struct resource uart4[] = { | |
111 | { | |
112 | .start = UART5_BASE_ADDR, | |
113 | .end = UART5_BASE_ADDR + 0x0B5, | |
114 | .flags = IORESOURCE_MEM, | |
115 | }, { | |
116 | .start = MXC_INT_UART5, | |
117 | .end = MXC_INT_UART5, | |
118 | .flags = IORESOURCE_IRQ, | |
119 | }, | |
120 | }; | |
121 | ||
5cf09421 | 122 | struct platform_device mxc_uart_device4 = { |
e3d13ff4 SH |
123 | .name = "imx-uart", |
124 | .id = 4, | |
125 | .resource = uart4, | |
126 | .num_resources = ARRAY_SIZE(uart4), | |
127 | }; | |
9536ff33 | 128 | #endif /* CONFIG_ARCH_MX31 */ |
e3d13ff4 | 129 | |
07bd1a6c JB |
130 | /* GPIO port description */ |
131 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
3f4f54b4 | 132 | { |
07bd1a6c JB |
133 | .chip.label = "gpio-0", |
134 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | |
135 | .irq = MXC_INT_GPIO1, | |
9d631b83 | 136 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
3f4f54b4 | 137 | }, { |
07bd1a6c JB |
138 | .chip.label = "gpio-1", |
139 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | |
140 | .irq = MXC_INT_GPIO2, | |
9d631b83 | 141 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
3f4f54b4 | 142 | }, { |
07bd1a6c JB |
143 | .chip.label = "gpio-2", |
144 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | |
145 | .irq = MXC_INT_GPIO3, | |
9d631b83 | 146 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
07bd1a6c JB |
147 | } |
148 | }; | |
149 | ||
9a763bfb | 150 | int __init imx3x_register_gpios(void) |
07bd1a6c JB |
151 | { |
152 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
153 | } | |
a8405929 SH |
154 | |
155 | static struct resource mxc_w1_master_resources[] = { | |
156 | { | |
157 | .start = OWIRE_BASE_ADDR, | |
158 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
159 | .flags = IORESOURCE_MEM, | |
160 | }, | |
161 | }; | |
162 | ||
163 | struct platform_device mxc_w1_master_device = { | |
164 | .name = "mxc_w1", | |
165 | .id = 0, | |
166 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
167 | .resource = mxc_w1_master_resources, | |
168 | }; | |
cb96cf1a | 169 | |
2adc1d65 SH |
170 | #ifdef CONFIG_ARCH_MX31 |
171 | static struct resource mxcsdhc0_resources[] = { | |
172 | { | |
173 | .start = MMC_SDHC1_BASE_ADDR, | |
174 | .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1, | |
175 | .flags = IORESOURCE_MEM, | |
176 | }, { | |
177 | .start = MXC_INT_MMC_SDHC1, | |
178 | .end = MXC_INT_MMC_SDHC1, | |
179 | .flags = IORESOURCE_IRQ, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct resource mxcsdhc1_resources[] = { | |
184 | { | |
185 | .start = MMC_SDHC2_BASE_ADDR, | |
186 | .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1, | |
187 | .flags = IORESOURCE_MEM, | |
188 | }, { | |
189 | .start = MXC_INT_MMC_SDHC2, | |
190 | .end = MXC_INT_MMC_SDHC2, | |
191 | .flags = IORESOURCE_IRQ, | |
192 | }, | |
193 | }; | |
194 | ||
195 | struct platform_device mxcsdhc_device0 = { | |
196 | .name = "mxc-mmc", | |
197 | .id = 0, | |
198 | .num_resources = ARRAY_SIZE(mxcsdhc0_resources), | |
199 | .resource = mxcsdhc0_resources, | |
200 | }; | |
201 | ||
202 | struct platform_device mxcsdhc_device1 = { | |
203 | .name = "mxc-mmc", | |
204 | .id = 1, | |
205 | .num_resources = ARRAY_SIZE(mxcsdhc1_resources), | |
206 | .resource = mxcsdhc1_resources, | |
207 | }; | |
45001e92 ACA |
208 | |
209 | static struct resource rnga_resources[] = { | |
210 | { | |
211 | .start = RNGA_BASE_ADDR, | |
212 | .end = RNGA_BASE_ADDR + 0x28, | |
213 | .flags = IORESOURCE_MEM, | |
214 | }, | |
215 | }; | |
216 | ||
217 | struct platform_device mxc_rnga_device = { | |
218 | .name = "mxc_rnga", | |
219 | .id = -1, | |
220 | .num_resources = 1, | |
221 | .resource = rnga_resources, | |
222 | }; | |
2adc1d65 SH |
223 | #endif /* CONFIG_ARCH_MX31 */ |
224 | ||
ca489f8e VL |
225 | /* i.MX31 Image Processing Unit */ |
226 | ||
227 | /* The resource order is important! */ | |
228 | static struct resource mx3_ipu_rsrc[] = { | |
229 | { | |
230 | .start = IPU_CTRL_BASE_ADDR, | |
231 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | |
232 | .flags = IORESOURCE_MEM, | |
233 | }, { | |
234 | .start = IPU_CTRL_BASE_ADDR + 0x88, | |
235 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | |
236 | .flags = IORESOURCE_MEM, | |
237 | }, { | |
238 | .start = MXC_INT_IPU_SYN, | |
239 | .end = MXC_INT_IPU_SYN, | |
240 | .flags = IORESOURCE_IRQ, | |
241 | }, { | |
242 | .start = MXC_INT_IPU_ERR, | |
243 | .end = MXC_INT_IPU_ERR, | |
244 | .flags = IORESOURCE_IRQ, | |
245 | }, | |
246 | }; | |
247 | ||
248 | struct platform_device mx3_ipu = { | |
249 | .name = "ipu-core", | |
250 | .id = -1, | |
251 | .num_resources = ARRAY_SIZE(mx3_ipu_rsrc), | |
252 | .resource = mx3_ipu_rsrc, | |
253 | }; | |
254 | ||
255 | static struct resource fb_resources[] = { | |
256 | { | |
257 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | |
258 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | |
259 | .flags = IORESOURCE_MEM, | |
260 | }, | |
261 | }; | |
262 | ||
263 | struct platform_device mx3_fb = { | |
264 | .name = "mx3_sdc_fb", | |
265 | .id = -1, | |
266 | .num_resources = ARRAY_SIZE(fb_resources), | |
267 | .resource = fb_resources, | |
268 | .dev = { | |
9c70e227 | 269 | .coherent_dma_mask = DMA_BIT_MASK(32), |
ca489f8e VL |
270 | }, |
271 | }; | |
9536ff33 | 272 | |
9c70e227 VL |
273 | static struct resource camera_resources[] = { |
274 | { | |
275 | .start = IPU_CTRL_BASE_ADDR + 0x60, | |
276 | .end = IPU_CTRL_BASE_ADDR + 0x87, | |
277 | .flags = IORESOURCE_MEM, | |
278 | }, | |
279 | }; | |
280 | ||
281 | struct platform_device mx3_camera = { | |
282 | .name = "mx3-camera", | |
283 | .id = 0, | |
284 | .num_resources = ARRAY_SIZE(camera_resources), | |
285 | .resource = camera_resources, | |
286 | .dev = { | |
287 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
288 | }, | |
289 | }; | |
290 | ||
eb05bbeb GL |
291 | static struct resource otg_resources[] = { |
292 | { | |
7bc07ebc SH |
293 | .start = MX31_OTG_BASE_ADDR, |
294 | .end = MX31_OTG_BASE_ADDR + 0x1ff, | |
eb05bbeb GL |
295 | .flags = IORESOURCE_MEM, |
296 | }, { | |
297 | .start = MXC_INT_USB3, | |
298 | .end = MXC_INT_USB3, | |
299 | .flags = IORESOURCE_IRQ, | |
300 | }, | |
301 | }; | |
302 | ||
303 | static u64 otg_dmamask = DMA_BIT_MASK(32); | |
304 | ||
305 | /* OTG gadget device */ | |
306 | struct platform_device mxc_otg_udc_device = { | |
307 | .name = "fsl-usb2-udc", | |
308 | .id = -1, | |
309 | .dev = { | |
310 | .dma_mask = &otg_dmamask, | |
311 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
312 | }, | |
313 | .resource = otg_resources, | |
314 | .num_resources = ARRAY_SIZE(otg_resources), | |
315 | }; | |
316 | ||
c13a482c DM |
317 | /* OTG host */ |
318 | struct platform_device mxc_otg_host = { | |
319 | .name = "mxc-ehci", | |
320 | .id = 0, | |
321 | .dev = { | |
322 | .coherent_dma_mask = 0xffffffff, | |
323 | .dma_mask = &otg_dmamask, | |
324 | }, | |
325 | .resource = otg_resources, | |
326 | .num_resources = ARRAY_SIZE(otg_resources), | |
327 | }; | |
328 | ||
329 | /* USB host 1 */ | |
330 | ||
331 | static u64 usbh1_dmamask = ~(u32)0; | |
332 | ||
333 | static struct resource mxc_usbh1_resources[] = { | |
334 | { | |
7bc07ebc SH |
335 | .start = MX31_OTG_BASE_ADDR + 0x200, |
336 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | |
c13a482c DM |
337 | .flags = IORESOURCE_MEM, |
338 | }, { | |
339 | .start = MXC_INT_USB1, | |
340 | .end = MXC_INT_USB1, | |
341 | .flags = IORESOURCE_IRQ, | |
342 | }, | |
343 | }; | |
344 | ||
345 | struct platform_device mxc_usbh1 = { | |
346 | .name = "mxc-ehci", | |
347 | .id = 1, | |
348 | .dev = { | |
349 | .coherent_dma_mask = 0xffffffff, | |
350 | .dma_mask = &usbh1_dmamask, | |
351 | }, | |
352 | .resource = mxc_usbh1_resources, | |
353 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | |
354 | }; | |
355 | ||
356 | /* USB host 2 */ | |
357 | static u64 usbh2_dmamask = ~(u32)0; | |
358 | ||
359 | static struct resource mxc_usbh2_resources[] = { | |
360 | { | |
7bc07ebc SH |
361 | .start = MX31_OTG_BASE_ADDR + 0x400, |
362 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | |
c13a482c DM |
363 | .flags = IORESOURCE_MEM, |
364 | }, { | |
365 | .start = MXC_INT_USB2, | |
366 | .end = MXC_INT_USB2, | |
367 | .flags = IORESOURCE_IRQ, | |
368 | }, | |
369 | }; | |
370 | ||
371 | struct platform_device mxc_usbh2 = { | |
372 | .name = "mxc-ehci", | |
373 | .id = 2, | |
374 | .dev = { | |
375 | .coherent_dma_mask = 0xffffffff, | |
376 | .dma_mask = &usbh2_dmamask, | |
377 | }, | |
378 | .resource = mxc_usbh2_resources, | |
379 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | |
380 | }; | |
381 | ||
06606ff1 | 382 | #if defined(CONFIG_ARCH_MX35) |
9536ff33 SH |
383 | static struct resource mxc_fec_resources[] = { |
384 | { | |
385 | .start = MXC_FEC_BASE_ADDR, | |
386 | .end = MXC_FEC_BASE_ADDR + 0xfff, | |
3f4f54b4 | 387 | .flags = IORESOURCE_MEM, |
9536ff33 SH |
388 | }, { |
389 | .start = MXC_INT_FEC, | |
390 | .end = MXC_INT_FEC, | |
3f4f54b4 | 391 | .flags = IORESOURCE_IRQ, |
9536ff33 SH |
392 | }, |
393 | }; | |
394 | ||
395 | struct platform_device mxc_fec_device = { | |
396 | .name = "fec", | |
397 | .id = 0, | |
398 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
399 | .resource = mxc_fec_resources, | |
400 | }; | |
401 | #endif | |
402 | ||
d8d982b1 SH |
403 | static struct resource imx_ssi_resources0[] = { |
404 | { | |
405 | .start = SSI1_BASE_ADDR, | |
406 | .end = SSI1_BASE_ADDR + 0xfff, | |
407 | .flags = IORESOURCE_MEM, | |
408 | }, { | |
409 | .start = MX31_INT_SSI1, | |
410 | .end = MX31_INT_SSI1, | |
411 | .flags = IORESOURCE_IRQ, | |
412 | }, | |
413 | }; | |
414 | ||
415 | static struct resource imx_ssi_resources1[] = { | |
416 | { | |
417 | .start = SSI2_BASE_ADDR, | |
418 | .end = SSI2_BASE_ADDR + 0xfff, | |
419 | .flags = IORESOURCE_MEM | |
420 | }, { | |
421 | .start = MX31_INT_SSI2, | |
422 | .end = MX31_INT_SSI2, | |
423 | .flags = IORESOURCE_IRQ, | |
424 | }, | |
425 | }; | |
426 | ||
427 | struct platform_device imx_ssi_device0 = { | |
428 | .name = "imx-ssi", | |
429 | .id = 0, | |
430 | .num_resources = ARRAY_SIZE(imx_ssi_resources0), | |
431 | .resource = imx_ssi_resources0, | |
432 | }; | |
433 | ||
434 | struct platform_device imx_ssi_device1 = { | |
435 | .name = "imx-ssi", | |
436 | .id = 1, | |
437 | .num_resources = ARRAY_SIZE(imx_ssi_resources1), | |
438 | .resource = imx_ssi_resources1, | |
439 | }; | |
440 | ||
a7dc12ba VZ |
441 | static struct resource imx_wdt_resources[] = { |
442 | { | |
443 | .flags = IORESOURCE_MEM, | |
444 | }, | |
445 | }; | |
446 | ||
447 | struct platform_device imx_wdt_device0 = { | |
6d38c1cf | 448 | .name = "imx2-wdt", |
a7dc12ba VZ |
449 | .id = 0, |
450 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | |
451 | .resource = imx_wdt_resources, | |
452 | }; | |
453 | ||
ded518c6 VZ |
454 | static struct resource imx_rtc_resources[] = { |
455 | { | |
456 | .start = MX31_RTC_BASE_ADDR, | |
457 | .end = MX31_RTC_BASE_ADDR + 0x3fff, | |
458 | .flags = IORESOURCE_MEM, | |
459 | }, | |
460 | { | |
461 | .start = MX31_INT_RTC, | |
462 | .flags = IORESOURCE_IRQ, | |
463 | }, | |
464 | }; | |
465 | ||
466 | struct platform_device imx_rtc_device0 = { | |
467 | .name = "mxc_rtc", | |
468 | .id = -1, | |
469 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | |
470 | .resource = imx_rtc_resources, | |
471 | }; | |
472 | ||
b1e89955 AP |
473 | static struct resource imx_kpp_resources[] = { |
474 | { | |
475 | .start = MX3x_KPP_BASE_ADDR, | |
476 | .end = MX3x_KPP_BASE_ADDR + 0xf, | |
477 | .flags = IORESOURCE_MEM | |
478 | }, { | |
479 | .start = MX3x_INT_KPP, | |
480 | .end = MX3x_INT_KPP, | |
481 | .flags = IORESOURCE_IRQ, | |
482 | }, | |
483 | }; | |
484 | ||
485 | struct platform_device imx_kpp_device = { | |
486 | .name = "imx-keypad", | |
487 | .id = -1, | |
488 | .num_resources = ARRAY_SIZE(imx_kpp_resources), | |
489 | .resource = imx_kpp_resources, | |
490 | }; | |
491 | ||
a7dc12ba | 492 | static int __init mx3_devices_init(void) |
9536ff33 | 493 | { |
a2ceeef5 | 494 | #if defined(CONFIG_ARCH_MX31) |
9536ff33 | 495 | if (cpu_is_mx31()) { |
a7dc12ba VZ |
496 | imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; |
497 | imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; | |
45001e92 | 498 | mxc_register_device(&mxc_rnga_device, NULL); |
9536ff33 | 499 | } |
a2ceeef5 UKK |
500 | #endif |
501 | #if defined(CONFIG_ARCH_MX35) | |
9536ff33 | 502 | if (cpu_is_mx35()) { |
7bc07ebc SH |
503 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
504 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | |
505 | otg_resources[1].start = MXC_INT_USBOTG; | |
506 | otg_resources[1].end = MXC_INT_USBOTG; | |
507 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | |
508 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | |
509 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | |
510 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | |
d8d982b1 SH |
511 | imx_ssi_resources0[1].start = MX35_INT_SSI1; |
512 | imx_ssi_resources0[1].end = MX35_INT_SSI1; | |
513 | imx_ssi_resources1[1].start = MX35_INT_SSI2; | |
514 | imx_ssi_resources1[1].end = MX35_INT_SSI2; | |
a7dc12ba VZ |
515 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; |
516 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | |
9536ff33 | 517 | } |
a2ceeef5 | 518 | #endif |
9536ff33 SH |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
523 | subsys_initcall(mx3_devices_init); |