[net-next-2.6.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx3_camera.h>

#include "devices.h"

static struct resource uart0[] = {
	{
		.start = UART1_BASE_ADDR,
		.end = UART1_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART1,
		.end = MXC_INT_UART1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device0 = {
	.name = "imx-uart",
	.id = 0,
	.resource = uart0,
	.num_resources = ARRAY_SIZE(uart0),
};

static struct resource uart1[] = {
	{
		.start = UART2_BASE_ADDR,
		.end = UART2_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART2,
		.end = MXC_INT_UART2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device1 = {
	.name = "imx-uart",
	.id = 1,
	.resource = uart1,
	.num_resources = ARRAY_SIZE(uart1),
};

static struct resource uart2[] = {
	{
		.start = UART3_BASE_ADDR,
		.end = UART3_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART3,
		.end = MXC_INT_UART3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device2 = {
	.name = "imx-uart",
	.id = 2,
	.resource = uart2,
	.num_resources = ARRAY_SIZE(uart2),
};

#ifdef CONFIG_ARCH_MX31
static struct resource uart3[] = {
	{
		.start = UART4_BASE_ADDR,
		.end = UART4_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART4,
		.end = MXC_INT_UART4,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device3 = {
	.name = "imx-uart",
	.id = 3,
	.resource = uart3,
	.num_resources = ARRAY_SIZE(uart3),
};

static struct resource uart4[] = {
	{
		.start = UART5_BASE_ADDR,
		.end = UART5_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART5,
		.end = MXC_INT_UART5,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device4 = {
	.name = "imx-uart",
	.id = 4,
	.resource = uart4,
	.num_resources = ARRAY_SIZE(uart4),
};
#endif /* CONFIG_ARCH_MX31 */

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init imx3x_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MMC_SDHC1_BASE_ADDR,
		.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC1,
		.end = MXC_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MMC_SDHC2_BASE_ADDR,
		.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC2,
		.end = MXC_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};

static struct resource rnga_resources[] = {
	{
		.start = RNGA_BASE_ADDR,
		.end = RNGA_BASE_ADDR + 0x28,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_rnga_device = {
	.name = "mxc_rnga",
	.id = -1,
	.num_resources = 1,
	.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
       },
};

static struct resource camera_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0x60,
		.end	= IPU_CTRL_BASE_ADDR + 0x87,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_camera = {
	.name		= "mx3-camera",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(camera_resources),
	.resource	= camera_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource otg_resources[] = {
	{
		.start	= MX31_OTG_BASE_ADDR,
		.end	= MX31_OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = ~(u32)0;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x200,
		.end = MX31_OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x400,
		.end = MX31_OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};

#if defined(CONFIG_ARCH_MX35)
/*
 * SPI master controller
 * 3 channels
 */
static struct resource mxc_spi_0_resources[] = {
	{
	       .start = CSPI1_BASE_ADDR,
	       .end = CSPI1_BASE_ADDR + SZ_4K - 1,
	       .flags = IORESOURCE_MEM,
	}, {
	       .start = MXC_INT_CSPI1,
	       .end = MXC_INT_CSPI1,
	       .flags = IORESOURCE_IRQ,
	},
};

static struct resource mxc_spi_1_resources[] = {
	{
		.start = CSPI2_BASE_ADDR,
		.end = CSPI2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI2,
		.end = MXC_INT_CSPI2,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxc_spi_2_resources[] = {
	{
		.start = CSPI3_BASE_ADDR,
		.end = CSPI3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI3,
		.end = MXC_INT_CSPI3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_spi_device0 = {
	.name = "spi_imx",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
	.resource = mxc_spi_0_resources,
};

struct platform_device mxc_spi_device1 = {
	.name = "spi_imx",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
	.resource = mxc_spi_1_resources,
};

struct platform_device mxc_spi_device2 = {
	.name = "spi_imx",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
	.resource = mxc_spi_2_resources,
};

static struct resource mxc_fec_resources[] = {
	{
		.start	= MXC_FEC_BASE_ADDR,
		.end	= MXC_FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource imx_ssi_resources0[] = {
	{
		.start	= SSI1_BASE_ADDR,
		.end	= SSI1_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MX31_INT_SSI1,
		.end	= MX31_INT_SSI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource imx_ssi_resources1[] = {
	{
		.start	= SSI2_BASE_ADDR,
		.end	= SSI2_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MX31_INT_SSI2,
		.end	= MX31_INT_SSI2,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device imx_ssi_device0 = {
	.name = "imx-ssi",
	.id = 0,
	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	.resource = imx_ssi_resources0,
};

struct platform_device imx_ssi_device1 = {
	.name = "imx-ssi",
	.id = 1,
	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	.resource = imx_ssi_resources1,
};

static struct resource imx_wdt_resources[] = {
	{
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device imx_wdt_device0 = {
	.name           = "imx2-wdt",
	.id             = 0,
	.num_resources  = ARRAY_SIZE(imx_wdt_resources),
	.resource       = imx_wdt_resources,
};

static struct resource imx_rtc_resources[] = {
	{
		.start  = MX31_RTC_BASE_ADDR,
		.end    = MX31_RTC_BASE_ADDR + 0x3fff,
		.flags  = IORESOURCE_MEM,
	},
	{
		.start  = MX31_INT_RTC,
		.flags  = IORESOURCE_IRQ,
	},
};

struct platform_device imx_rtc_device0 = {
	.name           = "mxc_rtc",
	.id             = -1,
	.num_resources  = ARRAY_SIZE(imx_rtc_resources),
	.resource       = imx_rtc_resources,
};

static struct resource imx_kpp_resources[] = {
	{
		.start	= MX3x_KPP_BASE_ADDR,
		.end	= MX3x_KPP_BASE_ADDR + 0xf,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MX3x_INT_KPP,
		.end	= MX3x_INT_KPP,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device imx_kpp_device = {
	.name = "imx-keypad",
	.id = -1,
	.num_resources = ARRAY_SIZE(imx_kpp_resources),
	.resource = imx_kpp_resources,
};

static int __init mx3_devices_init(void)
{
#if defined(CONFIG_ARCH_MX31)
	if (cpu_is_mx31()) {
		imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
		imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
		mxc_register_device(&mxc_rnga_device, NULL);
	}
#endif
#if defined(CONFIG_ARCH_MX35)
	if (cpu_is_mx35()) {
		otg_resources[0].start = MX35_OTG_BASE_ADDR;
		otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
		otg_resources[1].start = MXC_INT_USBOTG;
		otg_resources[1].end = MXC_INT_USBOTG;
		mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
		mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
		mxc_usbh1_resources[1].start = MXC_INT_USBHS;
		mxc_usbh1_resources[1].end = MXC_INT_USBHS;
		imx_ssi_resources0[1].start = MX35_INT_SSI1;
		imx_ssi_resources0[1].end = MX35_INT_SSI1;
		imx_ssi_resources1[1].start = MX35_INT_SSI2;
		imx_ssi_resources1[1].end = MX35_INT_SSI2;
		imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
		imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
	}
#endif

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
eb05bbeb	20	#include <linux/dma-mapping.h>
e3d13ff4 SH	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/serial.h>
07bd1a6c	24	#include <linux/gpio.h>
a09e64fb	25	#include <mach/hardware.h>
80b02c17	26	#include <mach/irqs.h>
45001e92	27	#include <mach/common.h>
a09e64fb	28	#include <mach/imx-uart.h>
9c70e227	29	#include <mach/mx3_camera.h>
e3d13ff4	30
87bbb197 SH	31	#include "devices.h"
87bbb197 SH	32
e3d13ff4 SH	33	static struct resource uart0[] = {
	34	{
	35	.start = UART1_BASE_ADDR,
	36	.end = UART1_BASE_ADDR + 0x0B5,
	37	.flags = IORESOURCE_MEM,
	38	}, {
	39	.start = MXC_INT_UART1,
	40	.end = MXC_INT_UART1,
	41	.flags = IORESOURCE_IRQ,
	42	},
	43	};
	44
5cf09421	45	struct platform_device mxc_uart_device0 = {
e3d13ff4 SH	46	.name = "imx-uart",
	47	.id = 0,
	48	.resource = uart0,
	49	.num_resources = ARRAY_SIZE(uart0),
	50	};
	51
	52	static struct resource uart1[] = {
	53	{
	54	.start = UART2_BASE_ADDR,
	55	.end = UART2_BASE_ADDR + 0x0B5,
	56	.flags = IORESOURCE_MEM,
	57	}, {
	58	.start = MXC_INT_UART2,
	59	.end = MXC_INT_UART2,
	60	.flags = IORESOURCE_IRQ,
	61	},
	62	};
	63
5cf09421	64	struct platform_device mxc_uart_device1 = {
e3d13ff4 SH	65	.name = "imx-uart",
	66	.id = 1,
	67	.resource = uart1,
	68	.num_resources = ARRAY_SIZE(uart1),
	69	};
	70
	71	static struct resource uart2[] = {
	72	{
	73	.start = UART3_BASE_ADDR,
	74	.end = UART3_BASE_ADDR + 0x0B5,
	75	.flags = IORESOURCE_MEM,
	76	}, {
	77	.start = MXC_INT_UART3,
	78	.end = MXC_INT_UART3,
	79	.flags = IORESOURCE_IRQ,
	80	},
	81	};
	82
5cf09421	83	struct platform_device mxc_uart_device2 = {
e3d13ff4 SH	84	.name = "imx-uart",
	85	.id = 2,
	86	.resource = uart2,
	87	.num_resources = ARRAY_SIZE(uart2),
	88	};
	89
9536ff33	90	#ifdef CONFIG_ARCH_MX31
e3d13ff4 SH	91	static struct resource uart3[] = {
	92	{
	93	.start = UART4_BASE_ADDR,
	94	.end = UART4_BASE_ADDR + 0x0B5,
	95	.flags = IORESOURCE_MEM,
	96	}, {
	97	.start = MXC_INT_UART4,
	98	.end = MXC_INT_UART4,
	99	.flags = IORESOURCE_IRQ,
	100	},
	101	};
	102
5cf09421	103	struct platform_device mxc_uart_device3 = {
e3d13ff4 SH	104	.name = "imx-uart",
	105	.id = 3,
	106	.resource = uart3,
	107	.num_resources = ARRAY_SIZE(uart3),
	108	};
	109
	110	static struct resource uart4[] = {
	111	{
	112	.start = UART5_BASE_ADDR,
	113	.end = UART5_BASE_ADDR + 0x0B5,
	114	.flags = IORESOURCE_MEM,
	115	}, {
	116	.start = MXC_INT_UART5,
	117	.end = MXC_INT_UART5,
	118	.flags = IORESOURCE_IRQ,
	119	},
	120	};
	121
5cf09421	122	struct platform_device mxc_uart_device4 = {
e3d13ff4 SH	123	.name = "imx-uart",
	124	.id = 4,
	125	.resource = uart4,
	126	.num_resources = ARRAY_SIZE(uart4),
	127	};
9536ff33	128	#endif /* CONFIG_ARCH_MX31 */
e3d13ff4	129
07bd1a6c JB	130	/* GPIO port description */
07bd1a6c JB	131	static struct mxc_gpio_port imx_gpio_ports[] = {
3f4f54b4	132	{
07bd1a6c JB	133	.chip.label = "gpio-0",
	134	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	135	.irq = MXC_INT_GPIO1,
9d631b83	136	.virtual_irq_start = MXC_GPIO_IRQ_START,
3f4f54b4	137	}, {
07bd1a6c JB	138	.chip.label = "gpio-1",
	139	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	140	.irq = MXC_INT_GPIO2,
9d631b83	141	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
3f4f54b4	142	}, {
07bd1a6c JB	143	.chip.label = "gpio-2",
	144	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	145	.irq = MXC_INT_GPIO3,
9d631b83	146	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	147	}
	148	};
	149
9a763bfb	150	int __init imx3x_register_gpios(void)
07bd1a6c JB	151	{
	152	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	153	}
a8405929 SH	154
	155	static struct resource mxc_w1_master_resources[] = {
	156	{
	157	.start = OWIRE_BASE_ADDR,
	158	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	159	.flags = IORESOURCE_MEM,
	160	},
	161	};
	162
	163	struct platform_device mxc_w1_master_device = {
	164	.name = "mxc_w1",
	165	.id = 0,
	166	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	167	.resource = mxc_w1_master_resources,
	168	};
cb96cf1a	169
2adc1d65 SH	170	#ifdef CONFIG_ARCH_MX31
	171	static struct resource mxcsdhc0_resources[] = {
	172	{
	173	.start = MMC_SDHC1_BASE_ADDR,
	174	.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
	175	.flags = IORESOURCE_MEM,
	176	}, {
	177	.start = MXC_INT_MMC_SDHC1,
	178	.end = MXC_INT_MMC_SDHC1,
	179	.flags = IORESOURCE_IRQ,
	180	},
	181	};
	182
	183	static struct resource mxcsdhc1_resources[] = {
	184	{
	185	.start = MMC_SDHC2_BASE_ADDR,
	186	.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
	187	.flags = IORESOURCE_MEM,
	188	}, {
	189	.start = MXC_INT_MMC_SDHC2,
	190	.end = MXC_INT_MMC_SDHC2,
	191	.flags = IORESOURCE_IRQ,
	192	},
	193	};
	194
	195	struct platform_device mxcsdhc_device0 = {
	196	.name = "mxc-mmc",
	197	.id = 0,
	198	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	199	.resource = mxcsdhc0_resources,
	200	};
	201
	202	struct platform_device mxcsdhc_device1 = {
	203	.name = "mxc-mmc",
	204	.id = 1,
	205	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	206	.resource = mxcsdhc1_resources,
	207	};
45001e92 ACA	208
	209	static struct resource rnga_resources[] = {
	210	{
	211	.start = RNGA_BASE_ADDR,
	212	.end = RNGA_BASE_ADDR + 0x28,
	213	.flags = IORESOURCE_MEM,
	214	},
	215	};
	216
	217	struct platform_device mxc_rnga_device = {
	218	.name = "mxc_rnga",
	219	.id = -1,
	220	.num_resources = 1,
	221	.resource = rnga_resources,
	222	};
2adc1d65 SH	223	#endif /* CONFIG_ARCH_MX31 */
2adc1d65 SH	224
ca489f8e VL	225	/* i.MX31 Image Processing Unit */
	226
	227	/* The resource order is important! */
	228	static struct resource mx3_ipu_rsrc[] = {
	229	{
	230	.start = IPU_CTRL_BASE_ADDR,
	231	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	232	.flags = IORESOURCE_MEM,
	233	}, {
	234	.start = IPU_CTRL_BASE_ADDR + 0x88,
	235	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	236	.flags = IORESOURCE_MEM,
	237	}, {
	238	.start = MXC_INT_IPU_SYN,
	239	.end = MXC_INT_IPU_SYN,
	240	.flags = IORESOURCE_IRQ,
	241	}, {
	242	.start = MXC_INT_IPU_ERR,
	243	.end = MXC_INT_IPU_ERR,
	244	.flags = IORESOURCE_IRQ,
	245	},
	246	};
	247
	248	struct platform_device mx3_ipu = {
	249	.name = "ipu-core",
	250	.id = -1,
	251	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	252	.resource = mx3_ipu_rsrc,
	253	};
	254
	255	static struct resource fb_resources[] = {
	256	{
	257	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	258	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	259	.flags = IORESOURCE_MEM,
	260	},
	261	};
	262
	263	struct platform_device mx3_fb = {
	264	.name = "mx3_sdc_fb",
	265	.id = -1,
	266	.num_resources = ARRAY_SIZE(fb_resources),
	267	.resource = fb_resources,
	268	.dev = {
9c70e227	269	.coherent_dma_mask = DMA_BIT_MASK(32),
ca489f8e VL	270	},
ca489f8e VL	271	};
9536ff33	272
9c70e227 VL	273	static struct resource camera_resources[] = {
	274	{
	275	.start = IPU_CTRL_BASE_ADDR + 0x60,
	276	.end = IPU_CTRL_BASE_ADDR + 0x87,
	277	.flags = IORESOURCE_MEM,
	278	},
	279	};
	280
	281	struct platform_device mx3_camera = {
	282	.name = "mx3-camera",
	283	.id = 0,
	284	.num_resources = ARRAY_SIZE(camera_resources),
	285	.resource = camera_resources,
	286	.dev = {
	287	.coherent_dma_mask = DMA_BIT_MASK(32),
	288	},
	289	};
	290
eb05bbeb GL	291	static struct resource otg_resources[] = {
eb05bbeb GL	292	{
7bc07ebc SH	293	.start = MX31_OTG_BASE_ADDR,
7bc07ebc SH	294	.end = MX31_OTG_BASE_ADDR + 0x1ff,
eb05bbeb GL	295	.flags = IORESOURCE_MEM,
	296	}, {
	297	.start = MXC_INT_USB3,
	298	.end = MXC_INT_USB3,
	299	.flags = IORESOURCE_IRQ,
	300	},
	301	};
	302
	303	static u64 otg_dmamask = DMA_BIT_MASK(32);
	304
	305	/* OTG gadget device */
	306	struct platform_device mxc_otg_udc_device = {
	307	.name = "fsl-usb2-udc",
	308	.id = -1,
	309	.dev = {
	310	.dma_mask = &otg_dmamask,
	311	.coherent_dma_mask = DMA_BIT_MASK(32),
	312	},
	313	.resource = otg_resources,
	314	.num_resources = ARRAY_SIZE(otg_resources),
	315	};
	316
c13a482c DM	317	/* OTG host */
	318	struct platform_device mxc_otg_host = {
	319	.name = "mxc-ehci",
	320	.id = 0,
	321	.dev = {
	322	.coherent_dma_mask = 0xffffffff,
	323	.dma_mask = &otg_dmamask,
	324	},
	325	.resource = otg_resources,
	326	.num_resources = ARRAY_SIZE(otg_resources),
	327	};
	328
	329	/* USB host 1 */
	330
	331	static u64 usbh1_dmamask = ~(u32)0;
	332
	333	static struct resource mxc_usbh1_resources[] = {
	334	{
7bc07ebc SH	335	.start = MX31_OTG_BASE_ADDR + 0x200,
7bc07ebc SH	336	.end = MX31_OTG_BASE_ADDR + 0x3ff,
c13a482c DM	337	.flags = IORESOURCE_MEM,
	338	}, {
	339	.start = MXC_INT_USB1,
	340	.end = MXC_INT_USB1,
	341	.flags = IORESOURCE_IRQ,
	342	},
	343	};
	344
	345	struct platform_device mxc_usbh1 = {
	346	.name = "mxc-ehci",
	347	.id = 1,
	348	.dev = {
	349	.coherent_dma_mask = 0xffffffff,
	350	.dma_mask = &usbh1_dmamask,
	351	},
	352	.resource = mxc_usbh1_resources,
	353	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	354	};
	355
	356	/* USB host 2 */
	357	static u64 usbh2_dmamask = ~(u32)0;
	358
	359	static struct resource mxc_usbh2_resources[] = {
	360	{
7bc07ebc SH	361	.start = MX31_OTG_BASE_ADDR + 0x400,
7bc07ebc SH	362	.end = MX31_OTG_BASE_ADDR + 0x5ff,
c13a482c DM	363	.flags = IORESOURCE_MEM,
	364	}, {
	365	.start = MXC_INT_USB2,
	366	.end = MXC_INT_USB2,
	367	.flags = IORESOURCE_IRQ,
	368	},
	369	};
	370
	371	struct platform_device mxc_usbh2 = {
	372	.name = "mxc-ehci",
	373	.id = 2,
	374	.dev = {
	375	.coherent_dma_mask = 0xffffffff,
	376	.dma_mask = &usbh2_dmamask,
	377	},
	378	.resource = mxc_usbh2_resources,
	379	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	380	};
	381
06606ff1	382	#if defined(CONFIG_ARCH_MX35)
d37ba97d SH	383	/*
	384	* SPI master controller
	385	* 3 channels
	386	*/
d9e8b884	387	static struct resource mxc_spi_0_resources[] = {
d37ba97d SH	388	{
	389	.start = CSPI1_BASE_ADDR,
	390	.end = CSPI1_BASE_ADDR + SZ_4K - 1,
	391	.flags = IORESOURCE_MEM,
	392	}, {
	393	.start = MXC_INT_CSPI1,
	394	.end = MXC_INT_CSPI1,
	395	.flags = IORESOURCE_IRQ,
	396	},
	397	};
	398
d9e8b884	399	static struct resource mxc_spi_1_resources[] = {
d37ba97d SH	400	{
	401	.start = CSPI2_BASE_ADDR,
	402	.end = CSPI2_BASE_ADDR + SZ_4K - 1,
	403	.flags = IORESOURCE_MEM,
	404	}, {
	405	.start = MXC_INT_CSPI2,
	406	.end = MXC_INT_CSPI2,
	407	.flags = IORESOURCE_IRQ,
	408	},
	409	};
	410
d9e8b884	411	static struct resource mxc_spi_2_resources[] = {
d37ba97d SH	412	{
	413	.start = CSPI3_BASE_ADDR,
	414	.end = CSPI3_BASE_ADDR + SZ_4K - 1,
	415	.flags = IORESOURCE_MEM,
	416	}, {
	417	.start = MXC_INT_CSPI3,
	418	.end = MXC_INT_CSPI3,
	419	.flags = IORESOURCE_IRQ,
	420	},
	421	};
	422
d9e8b884	423	struct platform_device mxc_spi_device0 = {
d37ba97d SH	424	.name = "spi_imx",
d37ba97d SH	425	.id = 0,
d9e8b884 GL	426	.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
d9e8b884 GL	427	.resource = mxc_spi_0_resources,
d37ba97d SH	428	};
d37ba97d SH	429
d9e8b884	430	struct platform_device mxc_spi_device1 = {
d37ba97d SH	431	.name = "spi_imx",
d37ba97d SH	432	.id = 1,
d9e8b884 GL	433	.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
d9e8b884 GL	434	.resource = mxc_spi_1_resources,
d37ba97d SH	435	};
d37ba97d SH	436
d9e8b884	437	struct platform_device mxc_spi_device2 = {
d37ba97d SH	438	.name = "spi_imx",
d37ba97d SH	439	.id = 2,
d9e8b884 GL	440	.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
d9e8b884 GL	441	.resource = mxc_spi_2_resources,
d37ba97d SH	442	};
d37ba97d SH	443
9536ff33 SH	444	static struct resource mxc_fec_resources[] = {
	445	{
	446	.start = MXC_FEC_BASE_ADDR,
	447	.end = MXC_FEC_BASE_ADDR + 0xfff,
3f4f54b4	448	.flags = IORESOURCE_MEM,
9536ff33 SH	449	}, {
	450	.start = MXC_INT_FEC,
	451	.end = MXC_INT_FEC,
3f4f54b4	452	.flags = IORESOURCE_IRQ,
9536ff33 SH	453	},
	454	};
	455
	456	struct platform_device mxc_fec_device = {
	457	.name = "fec",
	458	.id = 0,
	459	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	460	.resource = mxc_fec_resources,
	461	};
	462	#endif
	463
d8d982b1 SH	464	static struct resource imx_ssi_resources0[] = {
	465	{
	466	.start = SSI1_BASE_ADDR,
	467	.end = SSI1_BASE_ADDR + 0xfff,
	468	.flags = IORESOURCE_MEM,
	469	}, {
	470	.start = MX31_INT_SSI1,
	471	.end = MX31_INT_SSI1,
	472	.flags = IORESOURCE_IRQ,
	473	},
	474	};
	475
	476	static struct resource imx_ssi_resources1[] = {
	477	{
	478	.start = SSI2_BASE_ADDR,
	479	.end = SSI2_BASE_ADDR + 0xfff,
	480	.flags = IORESOURCE_MEM
	481	}, {
	482	.start = MX31_INT_SSI2,
	483	.end = MX31_INT_SSI2,
	484	.flags = IORESOURCE_IRQ,
	485	},
	486	};
	487
	488	struct platform_device imx_ssi_device0 = {
	489	.name = "imx-ssi",
	490	.id = 0,
	491	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	492	.resource = imx_ssi_resources0,
	493	};
	494
	495	struct platform_device imx_ssi_device1 = {
	496	.name = "imx-ssi",
	497	.id = 1,
	498	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	499	.resource = imx_ssi_resources1,
	500	};
	501
a7dc12ba VZ	502	static struct resource imx_wdt_resources[] = {
	503	{
	504	.flags = IORESOURCE_MEM,
	505	},
	506	};
	507
	508	struct platform_device imx_wdt_device0 = {
6d38c1cf	509	.name = "imx2-wdt",
a7dc12ba VZ	510	.id = 0,
	511	.num_resources = ARRAY_SIZE(imx_wdt_resources),
	512	.resource = imx_wdt_resources,
	513	};
	514
ded518c6 VZ	515	static struct resource imx_rtc_resources[] = {
	516	{
	517	.start = MX31_RTC_BASE_ADDR,
	518	.end = MX31_RTC_BASE_ADDR + 0x3fff,
	519	.flags = IORESOURCE_MEM,
	520	},
	521	{
	522	.start = MX31_INT_RTC,
	523	.flags = IORESOURCE_IRQ,
	524	},
	525	};
	526
	527	struct platform_device imx_rtc_device0 = {
	528	.name = "mxc_rtc",
	529	.id = -1,
	530	.num_resources = ARRAY_SIZE(imx_rtc_resources),
	531	.resource = imx_rtc_resources,
	532	};
	533
b1e89955 AP	534	static struct resource imx_kpp_resources[] = {
	535	{
	536	.start = MX3x_KPP_BASE_ADDR,
	537	.end = MX3x_KPP_BASE_ADDR + 0xf,
	538	.flags = IORESOURCE_MEM
	539	}, {
	540	.start = MX3x_INT_KPP,
	541	.end = MX3x_INT_KPP,
	542	.flags = IORESOURCE_IRQ,
	543	},
	544	};
	545
	546	struct platform_device imx_kpp_device = {
	547	.name = "imx-keypad",
	548	.id = -1,
	549	.num_resources = ARRAY_SIZE(imx_kpp_resources),
	550	.resource = imx_kpp_resources,
	551	};
	552
a7dc12ba	553	static int __init mx3_devices_init(void)
9536ff33	554	{
a2ceeef5	555	#if defined(CONFIG_ARCH_MX31)
9536ff33	556	if (cpu_is_mx31()) {
a7dc12ba VZ	557	imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
a7dc12ba VZ	558	imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
45001e92	559	mxc_register_device(&mxc_rnga_device, NULL);
9536ff33	560	}
a2ceeef5 UKK	561	#endif
a2ceeef5 UKK	562	#if defined(CONFIG_ARCH_MX35)
9536ff33	563	if (cpu_is_mx35()) {
7bc07ebc SH	564	otg_resources[0].start = MX35_OTG_BASE_ADDR;
	565	otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
	566	otg_resources[1].start = MXC_INT_USBOTG;
	567	otg_resources[1].end = MXC_INT_USBOTG;
	568	mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
	569	mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
	570	mxc_usbh1_resources[1].start = MXC_INT_USBHS;
	571	mxc_usbh1_resources[1].end = MXC_INT_USBHS;
d8d982b1 SH	572	imx_ssi_resources0[1].start = MX35_INT_SSI1;
	573	imx_ssi_resources0[1].end = MX35_INT_SSI1;
	574	imx_ssi_resources1[1].start = MX35_INT_SSI2;
	575	imx_ssi_resources1[1].end = MX35_INT_SSI2;
a7dc12ba VZ	576	imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
a7dc12ba VZ	577	imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
9536ff33	578	}
a2ceeef5	579	#endif
9536ff33 SH	580
	581	return 0;
	582	}
	583
	584	subsys_initcall(mx3_devices_init);