[net-next-2.6.git] / arch / arm / mach-mx25 / clock.c

/*
 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/clkdev.h>

#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mx25.h>

#define CRM_BASE	MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)

#define CCM_MPCTL	0x00
#define CCM_UPCTL	0x04
#define CCM_CCTL	0x08
#define CCM_CGCR0	0x0C
#define CCM_CGCR1	0x10
#define CCM_CGCR2	0x14
#define CCM_PCDR0	0x18
#define CCM_PCDR1	0x1C
#define CCM_PCDR2	0x20
#define CCM_PCDR3	0x24
#define CCM_RCSR	0x28
#define CCM_CRDR	0x2C
#define CCM_DCVR0	0x30
#define CCM_DCVR1	0x34
#define CCM_DCVR2	0x38
#define CCM_DCVR3	0x3c
#define CCM_LTR0	0x40
#define CCM_LTR1	0x44
#define CCM_LTR2	0x48
#define CCM_LTR3	0x4c

static unsigned long get_rate_mpll(void)
{
	ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);

	return mxc_decode_pll(mpctl, 24000000);
}

static unsigned long get_rate_upll(void)
{
	ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);

	return mxc_decode_pll(mpctl, 24000000);
}

unsigned long get_rate_arm(struct clk *clk)
{
	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
	unsigned long rate = get_rate_mpll();

	if (cctl & (1 << 14))
		rate = (rate * 3) >> 1;

	return rate / ((cctl >> 30) + 1);
}

static unsigned long get_rate_ahb(struct clk *clk)
{
	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);

	return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
}

static unsigned long get_rate_ipg(struct clk *clk)
{
	return get_rate_ahb(NULL) >> 1;
}

static unsigned long get_rate_per(int per)
{
	unsigned long ofs = (per & 0x3) * 8;
	unsigned long reg = per & ~0x3;
	unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
	unsigned long fref;

	if (readl(CRM_BASE + 0x64) & (1 << per))
		fref = get_rate_upll();
	else
		fref = get_rate_ipg(NULL);

	return fref / (val + 1);
}

static unsigned long get_rate_uart(struct clk *clk)
{
	return get_rate_per(15);
}

static unsigned long get_rate_ssi2(struct clk *clk)
{
	return get_rate_per(14);
}

static unsigned long get_rate_ssi1(struct clk *clk)
{
	return get_rate_per(13);
}

static unsigned long get_rate_i2c(struct clk *clk)
{
	return get_rate_per(6);
}

static unsigned long get_rate_nfc(struct clk *clk)
{
	return get_rate_per(8);
}

static unsigned long get_rate_gpt(struct clk *clk)
{
	return get_rate_per(5);
}

static unsigned long get_rate_lcdc(struct clk *clk)
{
	return get_rate_per(7);
}

static unsigned long get_rate_otg(struct clk *clk)
{
	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
	unsigned long rate = get_rate_upll();

	return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
}

static int clk_cgcr_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg |= 1 << clk->enable_shift;
	__raw_writel(reg, clk->enable_reg);

	return 0;
}

static void clk_cgcr_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg &= ~(1 << clk->enable_shift);
	__raw_writel(reg, clk->enable_reg);
}

#define DEFINE_CLOCK(name, i, er, es, gr, sr, s)	\
	static struct clk name = {			\
		.id		= i,			\
		.enable_reg	= CRM_BASE + er,	\
		.enable_shift	= es,			\
		.get_rate	= gr,			\
		.set_rate	= sr,			\
		.enable		= clk_cgcr_enable,	\
		.disable	= clk_cgcr_disable,	\
		.secondary	= s,			\
	}

DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,	 NULL, NULL);
DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,	 NULL, NULL);
DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,	 NULL, &lcdc_ahb_clk);
DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
DEFINE_CLOCK(pwm1_clk,	 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm2_clk,	 0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm3_clk,	 0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm4_clk,	 0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(kpp_clk,	 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(tsc_clk,	 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);

#define _REGISTER_CLOCK(d, n, c)	\
	{				\
		.dev_id = d,		\
		.con_id = n,		\
		.clk = &c,		\
	},

static struct clk_lookup lookups[] = {
	_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
	_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
	_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
	_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
	_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
	_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
	_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
	_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
	_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
	_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
	_REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
	_REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
	_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
	_REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
};

int __init mx25_clocks_init(void)
{
	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	/* Turn off all clocks except the ones we need to survive, namely:
	 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
	 * SCC
	 */
	__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
	__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
	__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);

	/* Clock source for lcdc is upll */
	__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);

	mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);

	return 0;
}
Commit	Line	Data
8c25c36f SH	1	/*
	2	* Copyright (C) 2009 by Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	16	* MA 02110-1301, USA.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/list.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24
	25	#include <asm/clkdev.h>
	26
	27	#include <mach/clock.h>
	28	#include <mach/hardware.h>
	29	#include <mach/common.h>
	30	#include <mach/mx25.h>
	31
	32	#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
	33
	34	#define CCM_MPCTL 0x00
	35	#define CCM_UPCTL 0x04
	36	#define CCM_CCTL 0x08
	37	#define CCM_CGCR0 0x0C
	38	#define CCM_CGCR1 0x10
	39	#define CCM_CGCR2 0x14
	40	#define CCM_PCDR0 0x18
	41	#define CCM_PCDR1 0x1C
	42	#define CCM_PCDR2 0x20
	43	#define CCM_PCDR3 0x24
	44	#define CCM_RCSR 0x28
	45	#define CCM_CRDR 0x2C
	46	#define CCM_DCVR0 0x30
	47	#define CCM_DCVR1 0x34
	48	#define CCM_DCVR2 0x38
	49	#define CCM_DCVR3 0x3c
	50	#define CCM_LTR0 0x40
	51	#define CCM_LTR1 0x44
	52	#define CCM_LTR2 0x48
	53	#define CCM_LTR3 0x4c
	54
	55	static unsigned long get_rate_mpll(void)
	56	{
	57	ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
	58
	59	return mxc_decode_pll(mpctl, 24000000);
	60	}
	61
	62	static unsigned long get_rate_upll(void)
	63	{
	64	ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
65
66	return mxc_decode_pll(mpctl, 24000000);
67	}
68
69	unsigned long get_rate_arm(struct clk *clk)
70	{
71	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
72	unsigned long rate = get_rate_mpll();
73
74	if (cctl & (1 << 14))
75	rate = (rate * 3) >> 1;
76
77	return rate / ((cctl >> 30) + 1);
78	}
79
80	static unsigned long get_rate_ahb(struct clk *clk)
81	{
82	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
83
84	return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
85	}
86
87	static unsigned long get_rate_ipg(struct clk *clk)
88	{
89	return get_rate_ahb(NULL) >> 1;
90	}
91
92	static unsigned long get_rate_per(int per)
93	{
94	unsigned long ofs = (per & 0x3) * 8;
95	unsigned long reg = per & ~0x3;
96	unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
97	unsigned long fref;
98
99	if (readl(CRM_BASE + 0x64) & (1 << per))
100	fref = get_rate_upll();
101	else
102	fref = get_rate_ipg(NULL);
103
104	return fref / (val + 1);
105	}
106
107	static unsigned long get_rate_uart(struct clk *clk)
108	{
109	return get_rate_per(15);
110	}
111
8402ed30 EB	112	static unsigned long get_rate_ssi2(struct clk *clk)
	113	{
	114	return get_rate_per(14);
	115	}
	116
	117	static unsigned long get_rate_ssi1(struct clk *clk)
	118	{
	119	return get_rate_per(13);
	120	}
	121
8c25c36f SH	122	static unsigned long get_rate_i2c(struct clk *clk)
	123	{
	124	return get_rate_per(6);
	125	}
	126
	127	static unsigned long get_rate_nfc(struct clk *clk)
	128	{
	129	return get_rate_per(8);
	130	}
	131
faed4066 BS	132	static unsigned long get_rate_gpt(struct clk *clk)
	133	{
	134	return get_rate_per(5);
	135	}
	136
04a03e5f BS	137	static unsigned long get_rate_lcdc(struct clk *clk)
	138	{
	139	return get_rate_per(7);
	140	}
	141
8c25c36f SH	142	static unsigned long get_rate_otg(struct clk *clk)
8c25c36f SH	143	{
a6e92b49 EB	144	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
	145	unsigned long rate = get_rate_upll();
	146
	147	return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
8c25c36f SH	148	}
	149
	150	static int clk_cgcr_enable(struct clk *clk)
	151	{
	152	u32 reg;
	153
	154	reg = __raw_readl(clk->enable_reg);
	155	reg \|= 1 << clk->enable_shift;
	156	__raw_writel(reg, clk->enable_reg);
	157
	158	return 0;
	159	}
	160
	161	static void clk_cgcr_disable(struct clk *clk)
	162	{
	163	u32 reg;
	164
	165	reg = __raw_readl(clk->enable_reg);
	166	reg &= ~(1 << clk->enable_shift);
	167	__raw_writel(reg, clk->enable_reg);
	168	}
	169
9611a9b6	170	#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
8c25c36f SH	171	static struct clk name = { \
	172	.id = i, \
	173	.enable_reg = CRM_BASE + er, \
	174	.enable_shift = es, \
	175	.get_rate = gr, \
	176	.set_rate = sr, \
	177	.enable = clk_cgcr_enable, \
	178	.disable = clk_cgcr_disable, \
9611a9b6	179	.secondary = s, \
8c25c36f SH	180	}
8c25c36f SH	181
faed4066	182	DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
4cd3f96c	183	DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
8402ed30 EB	184	DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
8402ed30 EB	185	DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
9611a9b6 SH	186	DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
	187	DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
	188	DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
1c574023	189	DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
04a03e5f BS	190	DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
04a03e5f BS	191	DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
4cd3f96c SH	192	DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
	193	DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
	194	DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
	195	DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
	196	DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
9611a9b6 SH	197	DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
	198	DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
	199	DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
	200	DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
	201	DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
	202	DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
	203	DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
	204	DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
	205	DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
1c574023	206	DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
dcbabbc1	207	DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
04a03e5f	208	DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
8402ed30 EB	209	DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
	210	DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
	211	DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
8c25c36f SH	212
	213	#define _REGISTER_CLOCK(d, n, c) \
	214	{ \
	215	.dev_id = d, \
	216	.con_id = n, \
	217	.clk = &c, \
	218	},
	219
	220	static struct clk_lookup lookups[] = {
	221	_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
	222	_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
	223	_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
	224	_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
	225	_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
	226	_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
	227	_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
	228	_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
	229	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
	230	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
	231	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
	232	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
	233	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
	234	_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
	235	_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
	236	_REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
	237	_REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
49535a95	238	_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
8c25c36f SH	239	_REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
	240	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
	241	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
	242	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
a759544f	243	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
dcbabbc1	244	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
04a03e5f	245	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
8402ed30 EB	246	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
	247	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
	248	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
8c25c36f SH	249	};
8c25c36f SH	250
fadc0956	251	int __init mx25_clocks_init(void)
8c25c36f	252	{
0a0300dc	253	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
8c25c36f	254
828df43f BS	255	/* Turn off all clocks except the ones we need to survive, namely:
	256	* EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
	257	* SCC
	258	*/
	259	__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
	260	__raw_writel((0xf << 16) \| (3 << 26), CRM_BASE + CCM_CGCR1);
	261	__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
	262
04a03e5f BS	263	/* Clock source for lcdc is upll */
	264	__raw_writel(__raw_readl(CRM_BASE+0x64) \| (1 << 7), CRM_BASE + 0x64);
	265
8c25c36f SH	266	mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
	267
	268	return 0;
	269	}