[net-next-2.6.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * General Purpose Timer
 * - i.MX1: 2 timer (slighly different register handling)
 * - i.MX21: 3 timer
 * - i.MX27: 6 timer
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	[0] = {
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources
};

static struct resource timer2_resources[] = {
	[0] = {
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	[0] = {
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources
};

static struct resource timer4_resources[] = {
	[0] = {
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources
};

static struct resource timer5_resources[] = {
	[0] = {
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	[0] = {
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	[0] = {
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources
};
#endif

static struct resource mxc_pwm_resources[] = {
	[0] = {
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	[0] = {
			.start = SDHC1_BASE_ADDR,
			.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
			.flags = IORESOURCE_MEM,
			},
	[1] = {
			.start = MXC_INT_SDHC1,
			.end   = MXC_INT_SDHC1,
			.flags = IORESOURCE_IRQ,
			},
	[2] = {
			.start  = DMA_REQ_SDHC1,
			.end    = DMA_REQ_SDHC1,
			.flags  = IORESOURCE_DMA
		},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	[0] = {
			.start = SDHC2_BASE_ADDR,
			.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
			.flags = IORESOURCE_MEM,
			},
	[1] = {
			.start = MXC_INT_SDHC2,
			.end   = MXC_INT_SDHC2,
			.flags = IORESOURCE_IRQ,
			},
	[2] = {
			.start  = DMA_REQ_SDHC2,
			.end    = DMA_REQ_SDHC2,
			.flags  = IORESOURCE_DMA
		},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	},
	[3] = {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	},
	[4] = {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	},
	[5] = {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3	41
fc80a5e3 JB	42	/*
	43	* General Purpose Timer
	44	* - i.MX1: 2 timer (slighly different register handling)
	45	* - i.MX21: 3 timer
	46	* - i.MX27: 6 timer
	47	*/
	48
	49	/* We use gpt0 as system timer, so do not add a device for this one */
	50
	51	static struct resource timer1_resources[] = {
	52	[0] = {
	53	.start = GPT2_BASE_ADDR,
	54	.end = GPT2_BASE_ADDR + 0x17,
	55	.flags = IORESOURCE_MEM
	56	},
	57	[1] = {
	58	.start = MXC_INT_GPT2,
	59	.end = MXC_INT_GPT2,
	60	.flags = IORESOURCE_IRQ,
	61	}
	62	};
	63
	64	struct platform_device mxc_gpt1 = {
	65	.name = "imx_gpt",
	66	.id = 1,
	67	.num_resources = ARRAY_SIZE(timer1_resources),
	68	.resource = timer1_resources
	69	};
	70
	71	static struct resource timer2_resources[] = {
	72	[0] = {
	73	.start = GPT3_BASE_ADDR,
	74	.end = GPT3_BASE_ADDR + 0x17,
	75	.flags = IORESOURCE_MEM
	76	},
	77	[1] = {
	78	.start = MXC_INT_GPT3,
	79	.end = MXC_INT_GPT3,
	80	.flags = IORESOURCE_IRQ,
	81	}
	82	};
	83
	84	struct platform_device mxc_gpt2 = {
	85	.name = "imx_gpt",
	86	.id = 2,
	87	.num_resources = ARRAY_SIZE(timer2_resources),
	88	.resource = timer2_resources
	89	};
	90
	91	#ifdef CONFIG_MACH_MX27
	92	static struct resource timer3_resources[] = {
	93	[0] = {
	94	.start = GPT4_BASE_ADDR,
	95	.end = GPT4_BASE_ADDR + 0x17,
	96	.flags = IORESOURCE_MEM
	97	},
	98	[1] = {
	99	.start = MXC_INT_GPT4,
	100	.end = MXC_INT_GPT4,
	101	.flags = IORESOURCE_IRQ,
	102	}
	103	};
	104
	105	struct platform_device mxc_gpt3 = {
106	.name = "imx_gpt",
107	.id = 3,
108	.num_resources = ARRAY_SIZE(timer3_resources),
109	.resource = timer3_resources
110	};
111
112	static struct resource timer4_resources[] = {
113	[0] = {
114	.start = GPT5_BASE_ADDR,
115	.end = GPT5_BASE_ADDR + 0x17,
116	.flags = IORESOURCE_MEM
117	},
118	[1] = {
119	.start = MXC_INT_GPT5,
120	.end = MXC_INT_GPT5,
121	.flags = IORESOURCE_IRQ,
122	}
123	};
124
125	struct platform_device mxc_gpt4 = {
126	.name = "imx_gpt",
127	.id = 4,
128	.num_resources = ARRAY_SIZE(timer4_resources),
129	.resource = timer4_resources
130	};
131
132	static struct resource timer5_resources[] = {
133	[0] = {
134	.start = GPT6_BASE_ADDR,
135	.end = GPT6_BASE_ADDR + 0x17,
136	.flags = IORESOURCE_MEM
137	},
138	[1] = {
139	.start = MXC_INT_GPT6,
140	.end = MXC_INT_GPT6,
141	.flags = IORESOURCE_IRQ,
142	}
143	};
144
145	struct platform_device mxc_gpt5 = {
146	.name = "imx_gpt",
147	.id = 5,
148	.num_resources = ARRAY_SIZE(timer5_resources),
149	.resource = timer5_resources
150	};
151	#endif
152
153	/*
154	* Watchdog:
155	* - i.MX1
156	* - i.MX21
157	* - i.MX27
158	*/
159	static struct resource mxc_wdt_resources[] = {
160	{
161	.start = WDOG_BASE_ADDR,
162	.end = WDOG_BASE_ADDR + 0x30,
163	.flags = IORESOURCE_MEM,
164	},
165	};
166
167	struct platform_device mxc_wdt = {
168	.name = "mxc_wdt",
169	.id = 0,
170	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
171	.resource = mxc_wdt_resources,
172	};
173
3d89baa7 SH	174	static struct resource mxc_w1_master_resources[] = {
	175	{
	176	.start = OWIRE_BASE_ADDR,
	177	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	178	.flags = IORESOURCE_MEM,
	179	},
	180	};
	181
	182	struct platform_device mxc_w1_master_device = {
	183	.name = "mxc_w1",
	184	.id = 0,
	185	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	186	.resource = mxc_w1_master_resources,
	187	};
	188
02870978 SH	189	static struct resource mxc_nand_resources[] = {
	190	{
	191	.start = NFC_BASE_ADDR,
	192	.end = NFC_BASE_ADDR + 0xfff,
	193	.flags = IORESOURCE_MEM
	194	}, {
	195	.start = MXC_INT_NANDFC,
	196	.end = MXC_INT_NANDFC,
	197	.flags = IORESOURCE_IRQ
	198	},
	199	};
	200
	201	struct platform_device mxc_nand_device = {
	202	.name = "mxc_nand",
	203	.id = 0,
	204	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	205	.resource = mxc_nand_resources,
	206	};
	207
e4813551 HS	208	/*
	209	* lcdc:
	210	* - i.MX1: the basic controller
	211	* - i.MX21: to be checked
	212	* - i.MX27: like i.MX1, with slightly variations
	213	*/
	214	static struct resource mxc_fb[] = {
	215	{
	216	.start = LCDC_BASE_ADDR,
	217	.end = LCDC_BASE_ADDR + 0xFFF,
	218	.flags = IORESOURCE_MEM,
	219	},
	220	{
	221	.start = MXC_INT_LCDC,
	222	.end = MXC_INT_LCDC,
	223	.flags = IORESOURCE_IRQ,
	224	}
	225	};
	226
	227	/* mxc lcd driver */
	228	struct platform_device mxc_fb_device = {
	229	.name = "imx-fb",
	230	.id = 0,
	231	.num_resources = ARRAY_SIZE(mxc_fb),
	232	.resource = mxc_fb,
	233	.dev = {
	234	.coherent_dma_mask = 0xFFFFFFFF,
	235	},
	236	};
	237
879fea1b SH	238	#ifdef CONFIG_MACH_MX27
	239	static struct resource mxc_fec_resources[] = {
	240	{
	241	.start = FEC_BASE_ADDR,
	242	.end = FEC_BASE_ADDR + 0xfff,
	243	.flags = IORESOURCE_MEM
	244	}, {
	245	.start = MXC_INT_FEC,
	246	.end = MXC_INT_FEC,
	247	.flags = IORESOURCE_IRQ
	248	},
	249	};
	250
	251	struct platform_device mxc_fec_device = {
	252	.name = "fec",
	253	.id = 0,
	254	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	255	.resource = mxc_fec_resources,
	256	};
e4813551 HS	257	#endif
e4813551 HS	258
c5d4dbff SH	259	static struct resource mxc_i2c_1_resources[] = {
	260	[0] = {
	261	.start = I2C_BASE_ADDR,
	262	.end = I2C_BASE_ADDR + 0x0fff,
	263	.flags = IORESOURCE_MEM
	264	},
	265	[1] = {
	266	.start = MXC_INT_I2C,
	267	.end = MXC_INT_I2C,
	268	.flags = IORESOURCE_IRQ
	269	}
	270	};
	271
	272	struct platform_device mxc_i2c_device0 = {
	273	.name = "imx-i2c",
	274	.id = 0,
	275	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	276	.resource = mxc_i2c_1_resources
	277	};
	278
	279	#ifdef CONFIG_MACH_MX27
	280	static struct resource mxc_i2c_2_resources[] = {
	281	[0] = {
	282	.start = I2C2_BASE_ADDR,
	283	.end = I2C2_BASE_ADDR + 0x0fff,
	284	.flags = IORESOURCE_MEM
	285	},
	286	[1] = {
	287	.start = MXC_INT_I2C2,
	288	.end = MXC_INT_I2C2,
	289	.flags = IORESOURCE_IRQ
	290	}
	291	};
	292
	293	struct platform_device mxc_i2c_device1 = {
	294	.name = "imx-i2c",
	295	.id = 1,
	296	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	297	.resource = mxc_i2c_2_resources
	298	};
	299	#endif
	300
824b16e6 SH	301	static struct resource mxc_pwm_resources[] = {
	302	[0] = {
	303	.start = PWM_BASE_ADDR,
	304	.end = PWM_BASE_ADDR + 0x0fff,
	305	.flags = IORESOURCE_MEM
	306	},
	307	[1] = {
	308	.start = MXC_INT_PWM,
	309	.end = MXC_INT_PWM,
	310	.flags = IORESOURCE_IRQ,
	311	}
	312	};
	313
	314	struct platform_device mxc_pwm_device = {
	315	.name = "mxc_pwm",
	316	.id = 0,
	317	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	318	.resource = mxc_pwm_resources
	319	};
	320
1a02be0e SH	321	/*
	322	* Resource definition for the MXC SDHC
	323	*/
	324	static struct resource mxc_sdhc1_resources[] = {
	325	[0] = {
	326	.start = SDHC1_BASE_ADDR,
	327	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	328	.flags = IORESOURCE_MEM,
	329	},
	330	[1] = {
	331	.start = MXC_INT_SDHC1,
	332	.end = MXC_INT_SDHC1,
	333	.flags = IORESOURCE_IRQ,
	334	},
	335	[2] = {
	336	.start = DMA_REQ_SDHC1,
	337	.end = DMA_REQ_SDHC1,
	338	.flags = IORESOURCE_DMA
	339	},
	340	};
	341
	342	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	343
	344	struct platform_device mxc_sdhc_device0 = {
	345	.name = "mxc-mmc",
	346	.id = 0,
	347	.dev = {
	348	.dma_mask = &mxc_sdhc1_dmamask,
	349	.coherent_dma_mask = 0xffffffff,
	350	},
	351	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	352	.resource = mxc_sdhc1_resources,
	353	};
	354
	355	static struct resource mxc_sdhc2_resources[] = {
	356	[0] = {
	357	.start = SDHC2_BASE_ADDR,
	358	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	359	.flags = IORESOURCE_MEM,
	360	},
	361	[1] = {
	362	.start = MXC_INT_SDHC2,
	363	.end = MXC_INT_SDHC2,
	364	.flags = IORESOURCE_IRQ,
	365	},
	366	[2] = {
	367	.start = DMA_REQ_SDHC2,
	368	.end = DMA_REQ_SDHC2,
	369	.flags = IORESOURCE_DMA
	370	},
	371	};
	372
	373	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	374
	375	struct platform_device mxc_sdhc_device1 = {
	376	.name = "mxc-mmc",
	377	.id = 1,
	378	.dev = {
	379	.dma_mask = &mxc_sdhc2_dmamask,
	380	.coherent_dma_mask = 0xffffffff,
	381	},
	382	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	383	.resource = mxc_sdhc2_resources,
	384	};
385
fc80a5e3 JB	386	/* GPIO port description */
	387	static struct mxc_gpio_port imx_gpio_ports[] = {
	388	[0] = {
	389	.chip.label = "gpio-0",
	390	.irq = MXC_INT_GPIO,
058b7a6f	391	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	392	.virtual_irq_start = MXC_GPIO_IRQ_START,
fc80a5e3 JB	393	},
	394	[1] = {
	395	.chip.label = "gpio-1",
058b7a6f	396	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	397	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
fc80a5e3 JB	398	},
	399	[2] = {
	400	.chip.label = "gpio-2",
058b7a6f	401	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	402	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
fc80a5e3 JB	403	},
	404	[3] = {
	405	.chip.label = "gpio-3",
058b7a6f	406	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	407	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
fc80a5e3 JB	408	},
	409	[4] = {
	410	.chip.label = "gpio-4",
058b7a6f	411	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	412	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
fc80a5e3 JB	413	},
	414	[5] = {
	415	.chip.label = "gpio-5",
058b7a6f	416	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	417	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	418	}
	419	};
	420
	421	int __init mxc_register_gpios(void)
	422	{
	423	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	424	}