[net-next-2.6.git] / arch / arm / mach-msm / devices-msm7x00.c

/* linux/arch/arm/mach-msm/devices.c
 *
 * Copyright (C) 2008 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>

#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include "devices.h"

#include <asm/mach/flash.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>


#include "clock.h"
#include <mach/mmc.h>

static struct resource resources_uart1[] = {
	{
		.start	= INT_UART1,
		.end	= INT_UART1,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= MSM_UART1_PHYS,
		.end	= MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct resource resources_uart2[] = {
	{
		.start	= INT_UART2,
		.end	= INT_UART2,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= MSM_UART2_PHYS,
		.end	= MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct resource resources_uart3[] = {
	{
		.start	= INT_UART3,
		.end	= INT_UART3,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= MSM_UART3_PHYS,
		.end	= MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device msm_device_uart1 = {
	.name	= "msm_serial",
	.id	= 0,
	.num_resources	= ARRAY_SIZE(resources_uart1),
	.resource	= resources_uart1,
};

struct platform_device msm_device_uart2 = {
	.name	= "msm_serial",
	.id	= 1,
	.num_resources	= ARRAY_SIZE(resources_uart2),
	.resource	= resources_uart2,
};

struct platform_device msm_device_uart3 = {
	.name	= "msm_serial",
	.id	= 2,
	.num_resources	= ARRAY_SIZE(resources_uart3),
	.resource	= resources_uart3,
};

static struct resource resources_i2c[] = {
	{
		.start	= MSM_I2C_PHYS,
		.end	= MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_PWB_I2C,
		.end	= INT_PWB_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device msm_device_i2c = {
	.name		= "msm_i2c",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(resources_i2c),
	.resource	= resources_i2c,
};

static struct resource resources_hsusb[] = {
	{
		.start	= MSM_HSUSB_PHYS,
		.end	= MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_USB_HS,
		.end	= INT_USB_HS,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device msm_device_hsusb = {
	.name		= "msm_hsusb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(resources_hsusb),
	.resource	= resources_hsusb,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

struct flash_platform_data msm_nand_data = {
	.parts		= NULL,
	.nr_parts	= 0,
};

static struct resource resources_nand[] = {
	[0] = {
		.start	= 7,
		.end	= 7,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device msm_device_nand = {
	.name		= "msm_nand",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(resources_nand),
	.resource	= resources_nand,
	.dev		= {
		.platform_data	= &msm_nand_data,
	},
};

struct platform_device msm_device_smd = {
	.name	= "msm_smd",
	.id	= -1,
};

static struct resource resources_sdc1[] = {
	{
		.start	= MSM_SDC1_PHYS,
		.end	= MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_SDC1_0,
		.end	= INT_SDC1_0,
		.flags	= IORESOURCE_IRQ,
		.name	= "cmd_irq",
	},
	{
		.start	= INT_SDC1_1,
		.end	= INT_SDC1_1,
		.flags	= IORESOURCE_IRQ,
		.name	= "pio_irq",
	},
	{
		.flags	= IORESOURCE_IRQ | IORESOURCE_DISABLED,
		.name	= "status_irq"
	},
	{
		.start	= 8,
		.end	= 8,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource resources_sdc2[] = {
	{
		.start	= MSM_SDC2_PHYS,
		.end	= MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_SDC2_0,
		.end	= INT_SDC2_0,
		.flags	= IORESOURCE_IRQ,
		.name	= "cmd_irq",
	},
		{
		.start	= INT_SDC2_1,
		.end	= INT_SDC2_1,
		.flags	= IORESOURCE_IRQ,
		.name	= "pio_irq",
	},
	{
		.flags	= IORESOURCE_IRQ | IORESOURCE_DISABLED,
		.name	= "status_irq"
	},
	{
		.start	= 8,
		.end	= 8,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource resources_sdc3[] = {
	{
		.start	= MSM_SDC3_PHYS,
		.end	= MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_SDC3_0,
		.end	= INT_SDC3_0,
		.flags	= IORESOURCE_IRQ,
		.name	= "cmd_irq",
	},
		{
		.start	= INT_SDC3_1,
		.end	= INT_SDC3_1,
		.flags	= IORESOURCE_IRQ,
		.name	= "pio_irq",
	},
	{
		.flags	= IORESOURCE_IRQ | IORESOURCE_DISABLED,
		.name	= "status_irq"
	},
	{
		.start	= 8,
		.end	= 8,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource resources_sdc4[] = {
	{
		.start	= MSM_SDC4_PHYS,
		.end	= MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_SDC4_0,
		.end	= INT_SDC4_0,
		.flags	= IORESOURCE_IRQ,
		.name	= "cmd_irq",
	},
		{
		.start	= INT_SDC4_1,
		.end	= INT_SDC4_1,
		.flags	= IORESOURCE_IRQ,
		.name	= "pio_irq",
	},
	{
		.flags	= IORESOURCE_IRQ | IORESOURCE_DISABLED,
		.name	= "status_irq"
	},
	{
		.start	= 8,
		.end	= 8,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device msm_device_sdc1 = {
	.name		= "msm_sdcc",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(resources_sdc1),
	.resource	= resources_sdc1,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

struct platform_device msm_device_sdc2 = {
	.name		= "msm_sdcc",
	.id		= 2,
	.num_resources	= ARRAY_SIZE(resources_sdc2),
	.resource	= resources_sdc2,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

struct platform_device msm_device_sdc3 = {
	.name		= "msm_sdcc",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(resources_sdc3),
	.resource	= resources_sdc3,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

struct platform_device msm_device_sdc4 = {
	.name		= "msm_sdcc",
	.id		= 4,
	.num_resources	= ARRAY_SIZE(resources_sdc4),
	.resource	= resources_sdc4,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

static struct platform_device *msm_sdcc_devices[] __initdata = {
	&msm_device_sdc1,
	&msm_device_sdc2,
	&msm_device_sdc3,
	&msm_device_sdc4,
};

int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat,
			unsigned int stat_irq, unsigned long stat_irq_flags)
{
	struct platform_device	*pdev;
	struct resource *res;

	if (controller < 1 || controller > 4)
		return -EINVAL;

	pdev = msm_sdcc_devices[controller-1];
	pdev->dev.platform_data = plat;

	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
	if (!res)
		return -EINVAL;
	else if (stat_irq) {
		res->start = res->end = stat_irq;
		res->flags &= ~IORESOURCE_DISABLED;
		res->flags |= stat_irq_flags;
	}

	return platform_device_register(pdev);
}

struct clk msm_clocks_7x01a[] = {
	CLK_PCOM("adm_clk",	ADM_CLK,	NULL, 0),
	CLK_PCOM("adsp_clk",	ADSP_CLK,	NULL, 0),
	CLK_PCOM("ebi1_clk",	EBI1_CLK,	NULL, 0),
	CLK_PCOM("ebi2_clk",	EBI2_CLK,	NULL, 0),
	CLK_PCOM("ecodec_clk",	ECODEC_CLK,	NULL, 0),
	CLK_PCOM("emdh_clk",	EMDH_CLK,	NULL, OFF),
	CLK_PCOM("gp_clk",		GP_CLK,		NULL, 0),
	CLK_PCOM("grp_clk",	GRP_3D_CLK,	NULL, OFF),
	CLK_PCOM("i2c_clk",	I2C_CLK,	&msm_device_i2c.dev, 0),
	CLK_PCOM("icodec_rx_clk",	ICODEC_RX_CLK,	NULL, 0),
	CLK_PCOM("icodec_tx_clk",	ICODEC_TX_CLK,	NULL, 0),
	CLK_PCOM("imem_clk",	IMEM_CLK,	NULL, OFF),
	CLK_PCOM("mdc_clk",	MDC_CLK,	NULL, 0),
	CLK_PCOM("mdp_clk",	MDP_CLK,	NULL, OFF),
	CLK_PCOM("pbus_clk",	PBUS_CLK,	NULL, 0),
	CLK_PCOM("pcm_clk",	PCM_CLK,	NULL, 0),
	CLK_PCOM("pmdh_clk",	PMDH_CLK,	NULL, OFF ),
	CLK_PCOM("sdac_clk",	SDAC_CLK,	NULL, OFF),
	CLK_PCOM("sdc_clk",	SDC1_CLK,	&msm_device_sdc1.dev, OFF),
	CLK_PCOM("sdc_pclk",	SDC1_P_CLK,	&msm_device_sdc1.dev, OFF),
	CLK_PCOM("sdc_clk",	SDC2_CLK,	&msm_device_sdc2.dev, OFF),
	CLK_PCOM("sdc_pclk",	SDC2_P_CLK,	&msm_device_sdc2.dev, OFF),
	CLK_PCOM("sdc_clk",	SDC3_CLK,	&msm_device_sdc3.dev, OFF),
	CLK_PCOM("sdc_pclk",	SDC3_P_CLK,	&msm_device_sdc3.dev, OFF),
	CLK_PCOM("sdc_clk",	SDC4_CLK,	&msm_device_sdc4.dev, OFF),
	CLK_PCOM("sdc_pclk",	SDC4_P_CLK,	&msm_device_sdc4.dev, OFF),
	CLK_PCOM("tsif_clk",	TSIF_CLK,	NULL, 0),
	CLK_PCOM("tsif_ref_clk",	TSIF_REF_CLK,	NULL, 0),
	CLK_PCOM("tv_dac_clk",	TV_DAC_CLK,	NULL, 0),
	CLK_PCOM("tv_enc_clk",	TV_ENC_CLK,	NULL, 0),
	CLK_PCOM("uart_clk",	UART1_CLK,	&msm_device_uart1.dev, OFF),
	CLK_PCOM("uart_clk",	UART2_CLK,	&msm_device_uart2.dev, 0),
	CLK_PCOM("uart_clk",	UART3_CLK,	&msm_device_uart3.dev, OFF),
	CLK_PCOM("uart1dm_clk",	UART1DM_CLK,	NULL, OFF),
	CLK_PCOM("uart2dm_clk",	UART2DM_CLK,	NULL, 0),
	CLK_PCOM("usb_hs_clk",	USB_HS_CLK,	&msm_device_hsusb.dev, OFF),
	CLK_PCOM("usb_hs_pclk",	USB_HS_P_CLK,	&msm_device_hsusb.dev, OFF),
	CLK_PCOM("usb_otg_clk",	USB_OTG_CLK,	NULL, 0),
	CLK_PCOM("vdc_clk",	VDC_CLK,	NULL, OFF ),
	CLK_PCOM("vfe_clk",	VFE_CLK,	NULL, OFF),
	CLK_PCOM("vfe_mdc_clk",	VFE_MDC_CLK,	NULL, OFF),
};

unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
Commit	Line	Data
bcc0f6af BS	1	/* linux/arch/arm/mach-msm/devices.c
	2	*
	3	* Copyright (C) 2008 Google, Inc.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/platform_device.h>
	18
80b02c17	19	#include <mach/irqs.h>
bcc0f6af BS	20	#include <mach/msm_iomap.h>
	21	#include "devices.h"
	22
	23	#include <asm/mach/flash.h>
	24	#include <linux/mtd/nand.h>
	25	#include <linux/mtd/partitions.h>
	26
5e96da5d DW	27
5e96da5d DW	28	#include "clock.h"
5d4f77ff SM	29	#include <mach/mmc.h>
5d4f77ff SM	30
bcc0f6af BS	31	static struct resource resources_uart1[] = {
	32	{
	33	.start = INT_UART1,
	34	.end = INT_UART1,
	35	.flags = IORESOURCE_IRQ,
	36	},
	37	{
	38	.start = MSM_UART1_PHYS,
	39	.end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
	40	.flags = IORESOURCE_MEM,
	41	},
	42	};
	43
	44	static struct resource resources_uart2[] = {
	45	{
	46	.start = INT_UART2,
	47	.end = INT_UART2,
	48	.flags = IORESOURCE_IRQ,
	49	},
	50	{
	51	.start = MSM_UART2_PHYS,
	52	.end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
	53	.flags = IORESOURCE_MEM,
	54	},
	55	};
	56
	57	static struct resource resources_uart3[] = {
	58	{
	59	.start = INT_UART3,
	60	.end = INT_UART3,
	61	.flags = IORESOURCE_IRQ,
	62	},
	63	{
	64	.start = MSM_UART3_PHYS,
	65	.end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
	66	.flags = IORESOURCE_MEM,
	67	},
	68	};
	69
	70	struct platform_device msm_device_uart1 = {
	71	.name = "msm_serial",
	72	.id = 0,
	73	.num_resources = ARRAY_SIZE(resources_uart1),
	74	.resource = resources_uart1,
	75	};
	76
	77	struct platform_device msm_device_uart2 = {
	78	.name = "msm_serial",
	79	.id = 1,
	80	.num_resources = ARRAY_SIZE(resources_uart2),
	81	.resource = resources_uart2,
	82	};
	83
	84	struct platform_device msm_device_uart3 = {
	85	.name = "msm_serial",
	86	.id = 2,
	87	.num_resources = ARRAY_SIZE(resources_uart3),
	88	.resource = resources_uart3,
	89	};
	90
	91	static struct resource resources_i2c[] = {
	92	{
	93	.start = MSM_I2C_PHYS,
	94	.end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
95	.flags = IORESOURCE_MEM,
96	},
97	{
98	.start = INT_PWB_I2C,
99	.end = INT_PWB_I2C,
100	.flags = IORESOURCE_IRQ,
101	},
102	};
103
104	struct platform_device msm_device_i2c = {
105	.name = "msm_i2c",
106	.id = 0,
107	.num_resources = ARRAY_SIZE(resources_i2c),
108	.resource = resources_i2c,
109	};
110
111	static struct resource resources_hsusb[] = {
112	{
113	.start = MSM_HSUSB_PHYS,
114	.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
115	.flags = IORESOURCE_MEM,
116	},
117	{
118	.start = INT_USB_HS,
119	.end = INT_USB_HS,
120	.flags = IORESOURCE_IRQ,
121	},
122	};
123
124	struct platform_device msm_device_hsusb = {
125	.name = "msm_hsusb",
126	.id = -1,
127	.num_resources = ARRAY_SIZE(resources_hsusb),
128	.resource = resources_hsusb,
129	.dev = {
130	.coherent_dma_mask = 0xffffffff,
131	},
132	};
133
134	struct flash_platform_data msm_nand_data = {
135	.parts = NULL,
136	.nr_parts = 0,
137	};
138
139	static struct resource resources_nand[] = {
140	[0] = {
141	.start = 7,
142	.end = 7,
143	.flags = IORESOURCE_DMA,
144	},
145	};
146
147	struct platform_device msm_device_nand = {
148	.name = "msm_nand",
149	.id = -1,
150	.num_resources = ARRAY_SIZE(resources_nand),
151	.resource = resources_nand,
152	.dev = {
153	.platform_data = &msm_nand_data,
154	},
155	};
156
157	struct platform_device msm_device_smd = {
158	.name = "msm_smd",
159	.id = -1,
160	};
161
162	static struct resource resources_sdc1[] = {
163	{
164	.start = MSM_SDC1_PHYS,
165	.end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
166	.flags = IORESOURCE_MEM,
167	},
168	{
169	.start = INT_SDC1_0,
830d843b DZ	170	.end = INT_SDC1_0,
	171	.flags = IORESOURCE_IRQ,
	172	.name = "cmd_irq",
	173	},
	174	{
	175	.start = INT_SDC1_1,
bcc0f6af BS	176	.end = INT_SDC1_1,
bcc0f6af BS	177	.flags = IORESOURCE_IRQ,
830d843b DZ	178	.name = "pio_irq",
	179	},
	180	{
	181	.flags = IORESOURCE_IRQ \| IORESOURCE_DISABLED,
	182	.name = "status_irq"
bcc0f6af BS	183	},
	184	{
	185	.start = 8,
	186	.end = 8,
	187	.flags = IORESOURCE_DMA,
	188	},
	189	};
	190
	191	static struct resource resources_sdc2[] = {
	192	{
	193	.start = MSM_SDC2_PHYS,
	194	.end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
	195	.flags = IORESOURCE_MEM,
	196	},
	197	{
	198	.start = INT_SDC2_0,
830d843b DZ	199	.end = INT_SDC2_0,
	200	.flags = IORESOURCE_IRQ,
	201	.name = "cmd_irq",
	202	},
	203	{
	204	.start = INT_SDC2_1,
bcc0f6af BS	205	.end = INT_SDC2_1,
bcc0f6af BS	206	.flags = IORESOURCE_IRQ,
830d843b DZ	207	.name = "pio_irq",
	208	},
	209	{
	210	.flags = IORESOURCE_IRQ \| IORESOURCE_DISABLED,
	211	.name = "status_irq"
bcc0f6af BS	212	},
	213	{
	214	.start = 8,
	215	.end = 8,
	216	.flags = IORESOURCE_DMA,
	217	},
	218	};
	219
	220	static struct resource resources_sdc3[] = {
	221	{
	222	.start = MSM_SDC3_PHYS,
	223	.end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
	224	.flags = IORESOURCE_MEM,
	225	},
	226	{
	227	.start = INT_SDC3_0,
830d843b DZ	228	.end = INT_SDC3_0,
	229	.flags = IORESOURCE_IRQ,
	230	.name = "cmd_irq",
	231	},
	232	{
	233	.start = INT_SDC3_1,
bcc0f6af BS	234	.end = INT_SDC3_1,
bcc0f6af BS	235	.flags = IORESOURCE_IRQ,
830d843b DZ	236	.name = "pio_irq",
	237	},
	238	{
	239	.flags = IORESOURCE_IRQ \| IORESOURCE_DISABLED,
	240	.name = "status_irq"
bcc0f6af BS	241	},
	242	{
	243	.start = 8,
	244	.end = 8,
	245	.flags = IORESOURCE_DMA,
	246	},
	247	};
	248
	249	static struct resource resources_sdc4[] = {
	250	{
	251	.start = MSM_SDC4_PHYS,
	252	.end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
	253	.flags = IORESOURCE_MEM,
	254	},
	255	{
	256	.start = INT_SDC4_0,
830d843b DZ	257	.end = INT_SDC4_0,
	258	.flags = IORESOURCE_IRQ,
	259	.name = "cmd_irq",
	260	},
	261	{
	262	.start = INT_SDC4_1,
bcc0f6af BS	263	.end = INT_SDC4_1,
bcc0f6af BS	264	.flags = IORESOURCE_IRQ,
830d843b DZ	265	.name = "pio_irq",
	266	},
	267	{
	268	.flags = IORESOURCE_IRQ \| IORESOURCE_DISABLED,
	269	.name = "status_irq"
bcc0f6af BS	270	},
	271	{
	272	.start = 8,
	273	.end = 8,
	274	.flags = IORESOURCE_DMA,
	275	},
	276	};
	277
	278	struct platform_device msm_device_sdc1 = {
	279	.name = "msm_sdcc",
	280	.id = 1,
	281	.num_resources = ARRAY_SIZE(resources_sdc1),
	282	.resource = resources_sdc1,
	283	.dev = {
	284	.coherent_dma_mask = 0xffffffff,
	285	},
	286	};
	287
	288	struct platform_device msm_device_sdc2 = {
	289	.name = "msm_sdcc",
	290	.id = 2,
	291	.num_resources = ARRAY_SIZE(resources_sdc2),
	292	.resource = resources_sdc2,
	293	.dev = {
	294	.coherent_dma_mask = 0xffffffff,
	295	},
	296	};
	297
	298	struct platform_device msm_device_sdc3 = {
	299	.name = "msm_sdcc",
	300	.id = 3,
	301	.num_resources = ARRAY_SIZE(resources_sdc3),
	302	.resource = resources_sdc3,
	303	.dev = {
	304	.coherent_dma_mask = 0xffffffff,
	305	},
	306	};
	307
	308	struct platform_device msm_device_sdc4 = {
	309	.name = "msm_sdcc",
	310	.id = 4,
	311	.num_resources = ARRAY_SIZE(resources_sdc4),
	312	.resource = resources_sdc4,
	313	.dev = {
	314	.coherent_dma_mask = 0xffffffff,
	315	},
	316	};
5d4f77ff SM	317
	318	static struct platform_device *msm_sdcc_devices[] __initdata = {
	319	&msm_device_sdc1,
	320	&msm_device_sdc2,
	321	&msm_device_sdc3,
	322	&msm_device_sdc4,
	323	};
	324
830d843b DZ	325	int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat,
830d843b DZ	326	unsigned int stat_irq, unsigned long stat_irq_flags)
5d4f77ff SM	327	{
5d4f77ff SM	328	struct platform_device *pdev;
830d843b	329	struct resource *res;
5d4f77ff SM	330
	331	if (controller < 1 \|\| controller > 4)
	332	return -EINVAL;
	333
	334	pdev = msm_sdcc_devices[controller-1];
	335	pdev->dev.platform_data = plat;
830d843b DZ	336
	337	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
	338	if (!res)
	339	return -EINVAL;
	340	else if (stat_irq) {
	341	res->start = res->end = stat_irq;
	342	res->flags &= ~IORESOURCE_DISABLED;
	343	res->flags \|= stat_irq_flags;
	344	}
	345
5d4f77ff SM	346	return platform_device_register(pdev);
	347	}
	348
5e96da5d DW	349	struct clk msm_clocks_7x01a[] = {
	350	CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
	351	CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
	352	CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
	353	CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
	354	CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
	355	CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF),
	356	CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
	357	CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF),
	358	CLK_PCOM("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0),
	359	CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
	360	CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
	361	CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
	362	CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
	363	CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
	364	CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0),
	365	CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
	366	CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ),
	367	CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
	368	CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
	369	CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
	370	CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
	371	CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF),
	372	CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
	373	CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF),
	374	CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
	375	CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF),
	376	CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
	377	CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
	378	CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
	379	CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
	380	CLK_PCOM("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF),
	381	CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0),
	382	CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF),
	383	CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF),
	384	CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0),
	385	CLK_PCOM("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF),
	386	CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, &msm_device_hsusb.dev, OFF),
	387	CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
	388	CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ),
	389	CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
	390	CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
	391	};
	392
	393	unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);