git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 651c74c7 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-kirkwood/include/mach/kirkwood.h |
| 651c74c7 SB |
3 | * |
| 4 | * Generic definitions for Marvell Kirkwood SoC flavors: | |
| 5 | * 88F6180, 88F6192 and 88F6281. | |
| 6 | * | |
| 7 | * This file is licensed under the terms of the GNU General Public | |
| 8 | * License version 2. This program is licensed "as is" without any | |
| 9 | * warranty of any kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ASM_ARCH_KIRKWOOD_H | |
| 13 | #define __ASM_ARCH_KIRKWOOD_H | |
| 14 | ||
| 15 | /* | |
| 16 | * Marvell Kirkwood address maps. | |
| 17 | * | |
| 18 | * phys | |
| ffd58bd2 SB |
19 | * e0000000 PCIe #0 Memory space |
| 20 | * e8000000 PCIe #1 Memory space | |
| 651c74c7 | 21 | * f1000000 on-chip peripheral registers |
| ffd58bd2 SB |
22 | * f2000000 PCIe #0 I/O space |
| 23 | * f3000000 PCIe #1 I/O space | |
| 24 | * f4000000 NAND controller address window | |
| 25 | * f5000000 Security Accelerator SRAM | |
| 651c74c7 SB |
26 | * |
| 27 | * virt phys size | |
| ffd58bd2 SB |
28 | * fed00000 f1000000 1M on-chip peripheral registers |
| 29 | * fee00000 f2000000 1M PCIe #0 I/O space | |
| 30 | * fef00000 f3000000 1M PCIe #1 I/O space | |
| 651c74c7 SB |
31 | */ |
| 32 | ||
| ffd58bd2 | 33 | #define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000 |
| c1191b0e NP |
34 | #define KIRKWOOD_SRAM_SIZE SZ_2K |
| 35 | ||
| ffd58bd2 | 36 | #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000 |
| fc63b723 | 37 | #define KIRKWOOD_NAND_MEM_SIZE SZ_1K |
| 651c74c7 | 38 | |
| ffd58bd2 SB |
39 | #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 |
| 40 | #define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 | |
| e4ff1c39 | 41 | #define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 |
| ffd58bd2 SB |
42 | #define KIRKWOOD_PCIE1_IO_SIZE SZ_1M |
| 43 | ||
| 651c74c7 | 44 | #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 |
| ffd58bd2 | 45 | #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 |
| 651c74c7 SB |
46 | #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 |
| 47 | #define KIRKWOOD_PCIE_IO_SIZE SZ_1M | |
| 48 | ||
| 49 | #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 | |
| ffd58bd2 | 50 | #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 |
| 651c74c7 SB |
51 | #define KIRKWOOD_REGS_SIZE SZ_1M |
| 52 | ||
| 53 | #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 | |
| a1897fa6 | 54 | #define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 |
| 651c74c7 SB |
55 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M |
| 56 | ||
| ffd58bd2 SB |
57 | #define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000 |
| 58 | #define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000 | |
| 59 | #define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M | |
| 60 | ||
| 651c74c7 SB |
61 | /* |
| 62 | * Register Map | |
| 63 | */ | |
| 64 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) | |
| 65 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) | |
| e50b6bef | 66 | #define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) |
| 651c74c7 SB |
67 | |
| 68 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) | |
| 69 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) | |
| 70 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) | |
| 71 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | |
| 72 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | |
| 73 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | |
| 6574e001 | 74 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) |
| 651c74c7 SB |
75 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 76 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | |
| 77 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | |
| 78 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | |
| 79 | ||
| fdd8b079 NP |
80 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) |
| 81 | ||
| ae5c8c83 NP |
82 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) |
| 83 | ||
| 651c74c7 | 84 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) |
| e8b2b7ba RK |
85 | #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) |
| 86 | #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) | |
| ffd58bd2 SB |
87 | #define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) |
| 88 | #define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) | |
| 89 | #define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) | |
| 651c74c7 SB |
90 | |
| 91 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) | |
| 92 | ||
| 09c0ed2e SB |
93 | #define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) |
| 94 | #define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) | |
| 95 | #define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) | |
| 96 | #define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) | |
| 97 | #define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) | |
| 98 | #define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) | |
| 99 | #define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) | |
| 100 | #define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) | |
| 101 | ||
| 651c74c7 SB |
102 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) |
| 103 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) | |
| 104 | ||
| 105 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | |
| e8b2b7ba RK |
106 | #define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) |
| 107 | #define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) | |
| 108 | #define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) | |
| 109 | #define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) | |
| 110 | #define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) | |
| 651c74c7 | 111 | |
| 8235ee00 NP |
112 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) |
| 113 | ||
| 49106c72 | 114 | #define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) |
| 115 | #define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) | |
| 116 | ||
| fdd8b079 NP |
117 | /* |
| 118 | * Supported devices and revisions. | |
| 119 | */ | |
| 120 | #define MV88F6281_DEV_ID 0x6281 | |
| 121 | #define MV88F6281_REV_Z0 0 | |
| 122 | #define MV88F6281_REV_A0 2 | |
| aec1bad3 | 123 | #define MV88F6281_REV_A1 3 |
| fdd8b079 NP |
124 | |
| 125 | #define MV88F6192_DEV_ID 0x6192 | |
| 126 | #define MV88F6192_REV_Z0 0 | |
| 127 | #define MV88F6192_REV_A0 2 | |
| 1c2003a1 | 128 | #define MV88F6192_REV_A1 3 |
| fdd8b079 NP |
129 | |
| 130 | #define MV88F6180_DEV_ID 0x6180 | |
| 131 | #define MV88F6180_REV_A0 2 | |
| 1c2003a1 | 132 | #define MV88F6180_REV_A1 3 |
| 651c74c7 | 133 | |
| 1e4d2d3d SB |
134 | #define MV88F6282_DEV_ID 0x6282 |
| 135 | #define MV88F6282_REV_A0 0 | |
| 651c74c7 | 136 | #endif |