[net-next-2.6.git] / arch / arm / mach-ixp2000 / ixdp2x01.c

/*
 * arch/arm/mach-ixp2000/ixdp2x01.c
 *
 * Code common to Intel IXDP2401 and IXDP2801 platforms
 *
 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright (C) 2002-2003 Intel Corp.
 * Copyright (C) 2003-2004 MontaVista Software, Inc.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/io.h>

#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>

#include <asm/mach/pci.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>

/*************************************************************************
 * IXDP2x01 IRQ Handling
 *************************************************************************/
static void ixdp2x01_irq_mask(unsigned int irq)
{
	ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
				IXP2000_BOARD_IRQ_MASK(irq));
}

static void ixdp2x01_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
				IXP2000_BOARD_IRQ_MASK(irq));
}

static u32 valid_irq_mask;

static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	u32 ex_interrupt;
	int i;

	desc->chip->mask(irq);

	ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;

	if (!ex_interrupt) {
		printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
		return;
	}

	for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
		if (ex_interrupt & (1 << i)) {
			int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
			generic_handle_irq(cpld_irq);
		}
	}

	desc->chip->unmask(irq);
}

static struct irq_chip ixdp2x01_irq_chip = {
	.mask	= ixdp2x01_irq_mask,
	.ack	= ixdp2x01_irq_mask,
	.unmask	= ixdp2x01_irq_unmask
};

/*
 * We only do anything if we are the master NPU on the board.
 * The slave NPU only has the ethernet chip going directly to
 * the PCIB interrupt input.
 */
void __init ixdp2x01_init_irq(void)
{
	int irq = 0;

	/* initialize chip specific interrupts */
	ixp2000_init_irq();

	if (machine_is_ixdp2401())
		valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
	else
		valid_irq_mask = IXDP2801_VALID_IRQ_MASK;

	/* Mask all interrupts from CPLD, disable simulation */
	ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
	ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);

	for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
		if (irq & valid_irq_mask) {
			set_irq_chip(irq, &ixdp2x01_irq_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, IRQF_VALID);
		} else {
			set_irq_flags(irq, 0);
		}
	}

	/* Hook into PCI interrupts */
	set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
}


/*************************************************************************
 * IXDP2x01 memory map
 *************************************************************************/
static struct map_desc ixdp2x01_io_desc __initdata = {
	.virtual	= IXDP2X01_VIRT_CPLD_BASE, 
	.pfn		= __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
	.length		= IXDP2X01_CPLD_REGION_SIZE,
	.type		= MT_DEVICE
};

static void __init ixdp2x01_map_io(void)
{
	ixp2000_map_io();
	iotable_init(&ixdp2x01_io_desc, 1);
}


/*************************************************************************
 * IXDP2x01 serial ports
 *************************************************************************/
static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
	{
		.mapbase	= (unsigned long)IXDP2X01_UART1_PHYS_BASE,
		.membase	= (char *)IXDP2X01_UART1_VIRT_BASE,
		.irq		= IRQ_IXDP2X01_UART1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM32,
		.regshift	= 2,
		.uartclk	= IXDP2X01_UART_CLK,
	},
	{ }
};

static struct resource ixdp2x01_uart_resource1 = {
	.start		= IXDP2X01_UART1_PHYS_BASE,
	.end		= IXDP2X01_UART1_PHYS_BASE + 0xffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp2x01_serial_device1 = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM1,
	.dev		= {
		.platform_data		= ixdp2x01_serial_port1,
	},
	.num_resources	= 1,
	.resource	= &ixdp2x01_uart_resource1,
};

static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
	{
		.mapbase	= (unsigned long)IXDP2X01_UART2_PHYS_BASE,
		.membase	= (char *)IXDP2X01_UART2_VIRT_BASE,
		.irq		= IRQ_IXDP2X01_UART2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM32,
		.regshift	= 2,
		.uartclk	= IXDP2X01_UART_CLK,
	}, 
	{ }
};

static struct resource ixdp2x01_uart_resource2 = {
	.start		= IXDP2X01_UART2_PHYS_BASE,
	.end		= IXDP2X01_UART2_PHYS_BASE + 0xffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp2x01_serial_device2 = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM2,
	.dev		= {
		.platform_data		= ixdp2x01_serial_port2,
	},
	.num_resources	= 1,
	.resource	= &ixdp2x01_uart_resource2,
};

static void ixdp2x01_uart_init(void)
{
	platform_device_register(&ixdp2x01_serial_device1);
	platform_device_register(&ixdp2x01_serial_device2);
}


/*************************************************************************
 * IXDP2x01 timer tick configuration
 *************************************************************************/
static unsigned int ixdp2x01_clock;

static int __init ixdp2x01_clock_setup(char *str)
{
	ixdp2x01_clock = simple_strtoul(str, NULL, 10);

	return 1;
}

__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);

static void __init ixdp2x01_timer_init(void)
{
	if (!ixdp2x01_clock)
		ixdp2x01_clock = 50000000;

	ixp2000_init_time(ixdp2x01_clock);
}

static struct sys_timer ixdp2x01_timer = {
	.init		= ixdp2x01_timer_init,
	.offset		= ixp2000_gettimeoffset,
};

/*************************************************************************
 * IXDP2x01 PCI
 *************************************************************************/
void __init ixdp2x01_pci_preinit(void)
{
	ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
	ixp2000_pci_preinit();
	pcibios_setup("firmware");
}

#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))

static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	u8 bus = dev->bus->number;
	u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
	struct pci_bus *tmp_bus = dev->bus;

	/* Primary bus, no interrupts here */
	if (bus == 0) {
		return -1;
	}

	/* Lookup first leaf in bus tree */
	while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
		tmp_bus = tmp_bus->parent;
	}

	/* Select between known bridges */
	switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
	/* Device is located after first MB bridge */
	case 0x0008:
		if (tmp_bus == dev->bus) {
			/* Device is located directly after first MB bridge */
			switch (devpin) {
			case DEVPIN(1, 1):	/* Onboard 82546 ch 0 */
				if (machine_is_ixdp2401())
					return IRQ_IXDP2401_INTA_82546;
				return -1;
			case DEVPIN(1, 2):	/* Onboard 82546 ch 1 */
				if (machine_is_ixdp2401())
					return IRQ_IXDP2401_INTB_82546;
				return -1;
			case DEVPIN(0, 1):	/* PMC INTA# */
				return IRQ_IXDP2X01_SPCI_PMC_INTA;
			case DEVPIN(0, 2):	/* PMC INTB# */
				return IRQ_IXDP2X01_SPCI_PMC_INTB;
			case DEVPIN(0, 3):	/* PMC INTC# */
				return IRQ_IXDP2X01_SPCI_PMC_INTC;
			case DEVPIN(0, 4):	/* PMC INTD# */
				return IRQ_IXDP2X01_SPCI_PMC_INTD;
			}
		}
		break;
	case 0x0010:
		if (tmp_bus == dev->bus) {
			/* Device is located directly after second MB bridge */
			/* Secondary bus of second bridge */
			switch (devpin) {
			case DEVPIN(0, 1):	/* DB#0 */
				return IRQ_IXDP2X01_SPCI_DB_0;
			case DEVPIN(1, 1):	/* DB#1 */
				return IRQ_IXDP2X01_SPCI_DB_1;
			}
		} else {
			/* Device is located indirectly after second MB bridge */
			/* Not supported now */
		}
		break;
	}

	return -1;
}


static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
{
	sys->mem_offset = 0xe0000000;

	if (machine_is_ixdp2801() || machine_is_ixdp28x5())
		sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);

	return ixp2000_pci_setup(nr, sys);
}

struct hw_pci ixdp2x01_pci __initdata = {
	.nr_controllers	= 1,
	.setup		= ixdp2x01_pci_setup,
	.preinit	= ixdp2x01_pci_preinit,
	.scan		= ixp2000_pci_scan_bus,
	.map_irq	= ixdp2x01_pci_map_irq,
};

int __init ixdp2x01_pci_init(void)
{
	if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
		machine_is_ixdp28x5())
		pci_common_init(&ixdp2x01_pci);

	return 0;
}

subsys_initcall(ixdp2x01_pci_init);

/*************************************************************************
 * IXDP2x01 Machine Initialization
 *************************************************************************/
static struct flash_platform_data ixdp2x01_flash_platform_data = {
	.map_name	= "cfi_probe",
	.width		= 1,
};

static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
{
	ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
		((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
	return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
}

static struct ixp2000_flash_data ixdp2x01_flash_data = {
	.platform_data	= &ixdp2x01_flash_platform_data,
	.bank_setup	= ixdp2x01_flash_bank_setup
};

static struct resource ixdp2x01_flash_resource = {
	.start		= 0xc4000000,
	.end		= 0xc4000000 + 0x01ffffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp2x01_flash = {
	.name		= "IXP2000-Flash",
	.id		= 0,
	.dev		= {
		.platform_data = &ixdp2x01_flash_data,
	},
	.num_resources	= 1,
	.resource	= &ixdp2x01_flash_resource,
};

static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
	.sda_pin	= IXDP2X01_GPIO_SDA,
	.scl_pin	= IXDP2X01_GPIO_SCL,
};

static struct platform_device ixdp2x01_i2c_controller = {
	.name		= "IXP2000-I2C",
	.id		= 0,
	.dev		= {
		.platform_data = &ixdp2x01_i2c_gpio_pins,
	},
	.num_resources	= 0
};

static struct platform_device *ixdp2x01_devices[] __initdata = {
	&ixdp2x01_flash,
	&ixdp2x01_i2c_controller
};

static void __init ixdp2x01_init_machine(void)
{
	ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
		(IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
	
	ixdp2x01_flash_data.nr_banks =
		((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);

	platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
	ixp2000_uart_init();
	ixdp2x01_uart_init();
}


#ifdef CONFIG_ARCH_IXDP2401
MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP2000_UART_PHYS_BASE,
	.io_pg_offst	= ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= ixdp2x01_map_io,
	.init_irq	= ixdp2x01_init_irq,
	.timer		= &ixdp2x01_timer,
	.init_machine	= ixdp2x01_init_machine,
MACHINE_END
#endif

#ifdef CONFIG_ARCH_IXDP2801
MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP2000_UART_PHYS_BASE,
	.io_pg_offst	= ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= ixdp2x01_map_io,
	.init_irq	= ixdp2x01_init_irq,
	.timer		= &ixdp2x01_timer,
	.init_machine	= ixdp2x01_init_machine,
MACHINE_END

/*
 * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
 * changed the machine ID in the bootloader
 */
MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP2000_UART_PHYS_BASE,
	.io_pg_offst	= ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= ixdp2x01_map_io,
	.init_irq	= ixdp2x01_init_irq,
	.timer		= &ixdp2x01_timer,
	.init_machine	= ixdp2x01_init_machine,
MACHINE_END
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp2000/ixdp2x01.c
	3	*
	4	* Code common to Intel IXDP2401 and IXDP2801 platforms
	5	*
	6	* Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
	7	* Maintainer: Deepak Saxena <dsaxena@plexity.net>
	8	*
	9	* Copyright (C) 2002-2003 Intel Corp.
	10	* Copyright (C) 2003-2004 MontaVista Software, Inc.
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*/
	17
1da177e4 LT	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/mm.h>
	21	#include <linux/sched.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/bitops.h>
	24	#include <linux/pci.h>
	25	#include <linux/ioport.h>
1da177e4 LT	26	#include <linux/delay.h>
	27	#include <linux/serial.h>
	28	#include <linux/tty.h>
	29	#include <linux/serial_core.h>
d052d1be	30	#include <linux/platform_device.h>
104c7b03	31	#include <linux/serial_8250.h>
fced80c7	32	#include <linux/io.h>
1da177e4	33
1da177e4 LT	34	#include <asm/irq.h>
	35	#include <asm/pgtable.h>
	36	#include <asm/page.h>
	37	#include <asm/system.h>
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/mach-types.h>
	40
	41	#include <asm/mach/pci.h>
	42	#include <asm/mach/map.h>
	43	#include <asm/mach/irq.h>
	44	#include <asm/mach/time.h>
	45	#include <asm/mach/arch.h>
	46	#include <asm/mach/flash.h>
	47
	48	/*************************************************************************
	49	* IXDP2x01 IRQ Handling
	50	*************************************************************************/
	51	static void ixdp2x01_irq_mask(unsigned int irq)
	52	{
e9b72e43	53	ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
1da177e4 LT	54	IXP2000_BOARD_IRQ_MASK(irq));
	55	}
	56
	57	static void ixdp2x01_irq_unmask(unsigned int irq)
	58	{
	59	ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
	60	IXP2000_BOARD_IRQ_MASK(irq));
	61	}
	62
	63	static u32 valid_irq_mask;
	64
10dd5ce2	65	static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	66	{
	67	u32 ex_interrupt;
	68	int i;
	69
	70	desc->chip->mask(irq);
	71
	72	ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
	73
	74	if (!ex_interrupt) {
	75	printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
	76	return;
	77	}
	78
	79	for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
	80	if (ex_interrupt & (1 << i)) {
1da177e4	81	int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
d8aa0251	82	generic_handle_irq(cpld_irq);
1da177e4 LT	83	}
	84	}
	85
	86	desc->chip->unmask(irq);
	87	}
	88
10dd5ce2	89	static struct irq_chip ixdp2x01_irq_chip = {
1da177e4 LT	90	.mask = ixdp2x01_irq_mask,
	91	.ack = ixdp2x01_irq_mask,
	92	.unmask = ixdp2x01_irq_unmask
	93	};
	94
	95	/*
	96	* We only do anything if we are the master NPU on the board.
	97	* The slave NPU only has the ethernet chip going directly to
	98	* the PCIB interrupt input.
	99	*/
	100	void __init ixdp2x01_init_irq(void)
	101	{
	102	int irq = 0;
	103
	104	/* initialize chip specific interrupts */
	105	ixp2000_init_irq();
	106
	107	if (machine_is_ixdp2401())
	108	valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
	109	else
	110	valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
	111
	112	/* Mask all interrupts from CPLD, disable simulation */
	113	ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
e9b72e43	114	ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
1da177e4 LT	115
	116	for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
	117	if (irq & valid_irq_mask) {
	118	set_irq_chip(irq, &ixdp2x01_irq_chip);
10dd5ce2	119	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	120	set_irq_flags(irq, IRQF_VALID);
	121	} else {
	122	set_irq_flags(irq, 0);
	123	}
	124	}
	125
	126	/* Hook into PCI interrupts */
64ffae8a	127	set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
1da177e4 LT	128	}
	129
	130
	131	/*************************************************************************
104c7b03	132	* IXDP2x01 memory map
1da177e4 LT	133	*************************************************************************/
	134	static struct map_desc ixdp2x01_io_desc __initdata = {
	135	.virtual = IXDP2X01_VIRT_CPLD_BASE,
db0d087e	136	.pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
1da177e4 LT	137	.length = IXDP2X01_CPLD_REGION_SIZE,
	138	.type = MT_DEVICE
	139	};
	140
104c7b03 LB	141	static void __init ixdp2x01_map_io(void)
	142	{
	143	ixp2000_map_io();
	144	iotable_init(&ixdp2x01_io_desc, 1);
	145	}
	146
	147
	148	/*************************************************************************
	149	* IXDP2x01 serial ports
	150	*************************************************************************/
	151	static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
1da177e4	152	{
1da177e4	153	.mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
104c7b03	154	.membase = (char *)IXDP2X01_UART1_VIRT_BASE,
1da177e4	155	.irq = IRQ_IXDP2X01_UART1,
104c7b03	156	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	157	.iotype = UPIO_MEM32,
	158	.regshift = 2,
	159	.uartclk = IXDP2X01_UART_CLK,
104c7b03 LB	160	},
	161	{ }
	162	};
	163
	164	static struct resource ixdp2x01_uart_resource1 = {
	165	.start = IXDP2X01_UART1_PHYS_BASE,
	166	.end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
	167	.flags = IORESOURCE_MEM,
	168	};
	169
	170	static struct platform_device ixdp2x01_serial_device1 = {
	171	.name = "serial8250",
	172	.id = PLAT8250_DEV_PLATFORM1,
	173	.dev = {
	174	.platform_data = ixdp2x01_serial_port1,
	175	},
	176	.num_resources = 1,
	177	.resource = &ixdp2x01_uart_resource1,
	178	};
	179
	180	static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
	181	{
1da177e4	182	.mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
104c7b03	183	.membase = (char *)IXDP2X01_UART2_VIRT_BASE,
1da177e4	184	.irq = IRQ_IXDP2X01_UART2,
104c7b03	185	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	186	.iotype = UPIO_MEM32,
	187	.regshift = 2,
	188	.uartclk = IXDP2X01_UART_CLK,
1da177e4	189	},
104c7b03	190	{ }
1da177e4 LT	191	};
1da177e4 LT	192
104c7b03 LB	193	static struct resource ixdp2x01_uart_resource2 = {
	194	.start = IXDP2X01_UART2_PHYS_BASE,
	195	.end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
	196	.flags = IORESOURCE_MEM,
	197	};
1da177e4	198
104c7b03 LB	199	static struct platform_device ixdp2x01_serial_device2 = {
	200	.name = "serial8250",
	201	.id = PLAT8250_DEV_PLATFORM2,
	202	.dev = {
	203	.platform_data = ixdp2x01_serial_port2,
	204	},
	205	.num_resources = 1,
	206	.resource = &ixdp2x01_uart_resource2,
	207	};
1da177e4	208
104c7b03 LB	209	static void ixdp2x01_uart_init(void)
	210	{
	211	platform_device_register(&ixdp2x01_serial_device1);
	212	platform_device_register(&ixdp2x01_serial_device2);
1da177e4 LT	213	}
	214
	215
	216	/*************************************************************************
	217	* IXDP2x01 timer tick configuration
	218	*************************************************************************/
	219	static unsigned int ixdp2x01_clock;
	220
	221	static int __init ixdp2x01_clock_setup(char *str)
	222	{
	223	ixdp2x01_clock = simple_strtoul(str, NULL, 10);
	224
	225	return 1;
	226	}
	227
	228	__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
	229
	230	static void __init ixdp2x01_timer_init(void)
	231	{
	232	if (!ixdp2x01_clock)
	233	ixdp2x01_clock = 50000000;
	234
	235	ixp2000_init_time(ixdp2x01_clock);
	236	}
	237
	238	static struct sys_timer ixdp2x01_timer = {
	239	.init = ixdp2x01_timer_init,
	240	.offset = ixp2000_gettimeoffset,
	241	};
	242
	243	/*************************************************************************
	244	* IXDP2x01 PCI
	245	*************************************************************************/
	246	void __init ixdp2x01_pci_preinit(void)
	247	{
	248	ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
	249	ixp2000_pci_preinit();
f8e5b284	250	pcibios_setup("firmware");
1da177e4 LT	251	}
	252
	253	#define DEVPIN(dev, pin) ((pin) \| ((dev) << 3))
	254
	255	static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	256	{
	257	u8 bus = dev->bus->number;
	258	u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
	259	struct pci_bus *tmp_bus = dev->bus;
	260
	261	/* Primary bus, no interrupts here */
	262	if (bus == 0) {
	263	return -1;
	264	}
	265
	266	/* Lookup first leaf in bus tree */
	267	while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
	268	tmp_bus = tmp_bus->parent;
	269	}
	270
	271	/* Select between known bridges */
	272	switch (tmp_bus->self->devfn \| (tmp_bus->self->bus->number << 8)) {
	273	/* Device is located after first MB bridge */
	274	case 0x0008:
	275	if (tmp_bus == dev->bus) {
6cbdc8c5	276	/* Device is located directly after first MB bridge */
1da177e4 LT	277	switch (devpin) {
	278	case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
	279	if (machine_is_ixdp2401())
	280	return IRQ_IXDP2401_INTA_82546;
	281	return -1;
	282	case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
	283	if (machine_is_ixdp2401())
	284	return IRQ_IXDP2401_INTB_82546;
	285	return -1;
	286	case DEVPIN(0, 1): /* PMC INTA# */
	287	return IRQ_IXDP2X01_SPCI_PMC_INTA;
	288	case DEVPIN(0, 2): /* PMC INTB# */
	289	return IRQ_IXDP2X01_SPCI_PMC_INTB;
	290	case DEVPIN(0, 3): /* PMC INTC# */
	291	return IRQ_IXDP2X01_SPCI_PMC_INTC;
	292	case DEVPIN(0, 4): /* PMC INTD# */
	293	return IRQ_IXDP2X01_SPCI_PMC_INTD;
	294	}
	295	}
	296	break;
	297	case 0x0010:
	298	if (tmp_bus == dev->bus) {
6cbdc8c5	299	/* Device is located directly after second MB bridge */
1da177e4 LT	300	/* Secondary bus of second bridge */
	301	switch (devpin) {
	302	case DEVPIN(0, 1): /* DB#0 */
	303	return IRQ_IXDP2X01_SPCI_DB_0;
	304	case DEVPIN(1, 1): /* DB#1 */
	305	return IRQ_IXDP2X01_SPCI_DB_1;
	306	}
	307	} else {
	308	/* Device is located indirectly after second MB bridge */
	309	/* Not supported now */
	310	}
	311	break;
	312	}
	313
	314	return -1;
	315	}
	316
	317
	318	static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
	319	{
	320	sys->mem_offset = 0xe0000000;
	321
0328ad23	322	if (machine_is_ixdp2801() \|\| machine_is_ixdp28x5())
1da177e4 LT	323	sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
	324
	325	return ixp2000_pci_setup(nr, sys);
	326	}
	327
	328	struct hw_pci ixdp2x01_pci __initdata = {
	329	.nr_controllers = 1,
	330	.setup = ixdp2x01_pci_setup,
	331	.preinit = ixdp2x01_pci_preinit,
	332	.scan = ixp2000_pci_scan_bus,
	333	.map_irq = ixdp2x01_pci_map_irq,
	334	};
	335
	336	int __init ixdp2x01_pci_init(void)
	337	{
0328ad23 DS	338	if (machine_is_ixdp2401() \|\| machine_is_ixdp2801() \|\|\
0328ad23 DS	339	machine_is_ixdp28x5())
1b394013 LB	340	pci_common_init(&ixdp2x01_pci);
1b394013 LB	341
1da177e4 LT	342	return 0;
	343	}
	344
	345	subsys_initcall(ixdp2x01_pci_init);
	346
	347	/*************************************************************************
6cbdc8c5	348	* IXDP2x01 Machine Initialization
1da177e4 LT	349	*************************************************************************/
	350	static struct flash_platform_data ixdp2x01_flash_platform_data = {
	351	.map_name = "cfi_probe",
	352	.width = 1,
	353	};
	354
	355	static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
	356	{
e9b72e43	357	ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
1da177e4 LT	358	((ofs >> IXDP2X01_FLASH_WINDOW_BITS) \| IXDP2X01_CPLD_FLASH_INTERN));
	359	return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
	360	}
	361
	362	static struct ixp2000_flash_data ixdp2x01_flash_data = {
	363	.platform_data = &ixdp2x01_flash_platform_data,
	364	.bank_setup = ixdp2x01_flash_bank_setup
	365	};
	366
	367	static struct resource ixdp2x01_flash_resource = {
	368	.start = 0xc4000000,
	369	.end = 0xc4000000 + 0x01ffffff,
	370	.flags = IORESOURCE_MEM,
	371	};
	372
	373	static struct platform_device ixdp2x01_flash = {
	374	.name = "IXP2000-Flash",
	375	.id = 0,
	376	.dev = {
	377	.platform_data = &ixdp2x01_flash_data,
	378	},
	379	.num_resources = 1,
	380	.resource = &ixdp2x01_flash_resource,
	381	};
	382
	383	static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
	384	.sda_pin = IXDP2X01_GPIO_SDA,
	385	.scl_pin = IXDP2X01_GPIO_SCL,
	386	};
	387
	388	static struct platform_device ixdp2x01_i2c_controller = {
	389	.name = "IXP2000-I2C",
	390	.id = 0,
	391	.dev = {
	392	.platform_data = &ixdp2x01_i2c_gpio_pins,
	393	},
	394	.num_resources = 0
	395	};
	396
	397	static struct platform_device *ixdp2x01_devices[] __initdata = {
	398	&ixdp2x01_flash,
	399	&ixdp2x01_i2c_controller
	400	};
	401
	402	static void __init ixdp2x01_init_machine(void)
	403	{
e9b72e43	404	ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
1da177e4 LT	405	(IXDP2X01_CPLD_FLASH_BANK_MASK \| IXDP2X01_CPLD_FLASH_INTERN));
	406
	407	ixdp2x01_flash_data.nr_banks =
	408	((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
	409
	410	platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
28187f2c	411	ixp2000_uart_init();
104c7b03	412	ixdp2x01_uart_init();
1da177e4 LT	413	}
	414
	415
	416	#ifdef CONFIG_ARCH_IXDP2401
	417	MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
e9dea0c6	418	/* Maintainer: MontaVista Software, Inc. */
e9dea0c6 RK	419	.phys_io = IXP2000_UART_PHYS_BASE,
	420	.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	421	.boot_params = 0x00000100,
	422	.map_io = ixdp2x01_map_io,
	423	.init_irq = ixdp2x01_init_irq,
1da177e4	424	.timer = &ixdp2x01_timer,
e9dea0c6	425	.init_machine = ixdp2x01_init_machine,
1da177e4 LT	426	MACHINE_END
	427	#endif
	428
	429	#ifdef CONFIG_ARCH_IXDP2801
	430	MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
e9dea0c6	431	/* Maintainer: MontaVista Software, Inc. */
e9dea0c6 RK	432	.phys_io = IXP2000_UART_PHYS_BASE,
	433	.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	434	.boot_params = 0x00000100,
	435	.map_io = ixdp2x01_map_io,
	436	.init_irq = ixdp2x01_init_irq,
1da177e4	437	.timer = &ixdp2x01_timer,
e9dea0c6	438	.init_machine = ixdp2x01_init_machine,
1da177e4	439	MACHINE_END
0328ad23 DS	440
	441	/*
	442	* IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
	443	* changed the machine ID in the bootloader
	444	*/
	445	MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
	446	/* Maintainer: MontaVista Software, Inc. */
	447	.phys_io = IXP2000_UART_PHYS_BASE,
	448	.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	449	.boot_params = 0x00000100,
	450	.map_io = ixdp2x01_map_io,
	451	.init_irq = ixdp2x01_init_irq,
	452	.timer = &ixdp2x01_timer,
	453	.init_machine = ixdp2x01_init_machine,
	454	MACHINE_END
1da177e4 LT	455	#endif
	456
	457