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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h |
1da177e4 LT |
3 | * |
4 | * Chipset register definitions for IXP2400/2800 based systems. | |
5 | * | |
6 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | |
7 | * | |
8 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
9 | * | |
10 | * Copyright (C) 2002 Intel Corp. | |
11 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #ifndef _IXP2000_REGS_H_ | |
19 | #define _IXP2000_REGS_H_ | |
20 | ||
67603be4 LB |
21 | /* |
22 | * IXP2000 linux memory map: | |
23 | * | |
24 | * virt phys size | |
25 | * fb000000 db000000 16M PCI CFG1 | |
26 | * fc000000 da000000 16M PCI CFG0 | |
27 | * fd000000 d8000000 16M PCI I/O | |
28 | * fe[0-7]00000 8M per-platform mappings | |
dd29c727 LB |
29 | * fe900000 80000000 1M SRAM #0 (first MB) |
30 | * fea00000 cb400000 1M SCRATCH ring get/put | |
67603be4 LB |
31 | * feb00000 c8000000 1M MSF |
32 | * fec00000 df000000 1M PCI CSRs | |
33 | * fed00000 de000000 1M PCI CREG | |
34 | * fee00000 d6000000 1M INTCTL | |
35 | * fef00000 c0000000 1M CAP | |
36 | */ | |
37 | ||
1da177e4 LT |
38 | /* |
39 | * Static I/O regions. | |
40 | * | |
41 | * Most of the registers are clumped in 4K regions spread throughout | |
42 | * the 0xc0000000 -> 0xc0100000 address range, but we just map in | |
43 | * the whole range using a single 1 MB section instead of small | |
44 | * 4K pages. This has two advantages for us: | |
45 | * | |
46 | * 1) We use only one TLB entry for large number of on-chip I/O devices. | |
47 | * | |
48 | * 2) We can easily set the Section attributes to XCB=101 on the IXP2400 | |
49 | * as required per erratum #66. We accomplish this by using a | |
50 | * new MT_IXP2000_DEVICE memory type with the bits set as required. | |
51 | * | |
52 | * CAP stands for CSR Access Proxy. | |
53 | * | |
54 | * If you change the virtual address of this mapping, please propagate | |
55 | * the change to arch/arm/kernel/debug.S, which hardcodes the virtual | |
56 | * address of the UART located in this region. | |
57 | */ | |
58 | ||
59 | #define IXP2000_CAP_PHYS_BASE 0xc0000000 | |
60 | #define IXP2000_CAP_VIRT_BASE 0xfef00000 | |
61 | #define IXP2000_CAP_SIZE 0x00100000 | |
62 | ||
63 | /* | |
d01e8897 | 64 | * Addresses for specific on-chip peripherals. |
1da177e4 LT |
65 | */ |
66 | #define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 | |
67 | #define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 | |
68 | #define IXP2000_UART_PHYS_BASE 0xc0030000 | |
69 | #define IXP2000_UART_VIRT_BASE 0xfef30000 | |
70 | #define IXP2000_TIMER_VIRT_BASE 0xfef20000 | |
d01e8897 LB |
71 | #define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 |
72 | #define IXP2000_GPIO_VIRT_BASE 0xfef10000 | |
1da177e4 LT |
73 | |
74 | /* | |
75 | * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual | |
76 | * addresses of the INTCTL and PCI_CSR mappings are hardcoded in | |
77 | * entry-macro.S, so if you ever change these please propagate | |
78 | * the change. | |
79 | */ | |
80 | #define IXP2000_INTCTL_PHYS_BASE 0xd6000000 | |
81 | #define IXP2000_INTCTL_VIRT_BASE 0xfee00000 | |
82 | #define IXP2000_INTCTL_SIZE 0x00100000 | |
83 | ||
84 | #define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 | |
85 | #define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 | |
86 | #define IXP2000_PCI_CREG_SIZE 0x00100000 | |
87 | ||
88 | #define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 | |
89 | #define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 | |
90 | #define IXP2000_PCI_CSR_SIZE 0x00100000 | |
91 | ||
baaf7ed1 LB |
92 | #define IXP2000_MSF_PHYS_BASE 0xc8000000 |
93 | #define IXP2000_MSF_VIRT_BASE 0xfeb00000 | |
94 | #define IXP2000_MSF_SIZE 0x00100000 | |
95 | ||
dd29c727 LB |
96 | #define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 |
97 | #define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 | |
98 | #define IXP2000_SCRATCH_RING_SIZE 0x00100000 | |
99 | ||
100 | #define IXP2000_SRAM0_PHYS_BASE 0x80000000 | |
101 | #define IXP2000_SRAM0_VIRT_BASE 0xfe900000 | |
102 | #define IXP2000_SRAM0_SIZE 0x00100000 | |
103 | ||
1da177e4 LT |
104 | #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 |
105 | #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 | |
106 | #define IXP2000_PCI_IO_SIZE 0x01000000 | |
107 | ||
108 | #define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 | |
109 | #define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 | |
110 | #define IXP2000_PCI_CFG0_SIZE 0x01000000 | |
111 | ||
112 | #define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 | |
113 | #define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 | |
114 | #define IXP2000_PCI_CFG1_SIZE 0x01000000 | |
115 | ||
116 | /* | |
117 | * Timers | |
118 | */ | |
119 | #define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) | |
120 | /* Timer control */ | |
121 | #define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) | |
122 | #define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) | |
123 | #define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) | |
124 | #define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) | |
125 | /* Store initial value */ | |
126 | #define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) | |
127 | #define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) | |
128 | #define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) | |
129 | #define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) | |
130 | /* Read current value */ | |
131 | #define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) | |
132 | #define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) | |
133 | #define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) | |
134 | #define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) | |
135 | /* Clear associated timer interrupt */ | |
136 | #define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) | |
137 | #define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) | |
138 | #define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) | |
139 | #define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) | |
140 | /* Timer watchdog enable for T4 */ | |
141 | #define IXP2000_TWDE IXP2000_TIMER_REG(0x40) | |
142 | ||
143 | #define WDT_ENABLE 0x00000001 | |
144 | #define TIMER_DIVIDER_256 0x00000008 | |
145 | #define TIMER_ENABLE 0x00000080 | |
146 | #define IRQ_MASK_TIMER1 (1 << 4) | |
147 | ||
148 | /* | |
149 | * Interrupt controller registers | |
150 | */ | |
151 | #define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) | |
152 | #define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) | |
153 | #define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) | |
154 | #define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) | |
155 | #define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) | |
156 | #define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) | |
157 | #define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) | |
158 | #define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) | |
159 | #define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) | |
160 | #define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) | |
161 | #define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) | |
162 | #define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) | |
163 | #define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) | |
164 | #define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) | |
165 | #define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) | |
166 | #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) | |
167 | #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) | |
168 | #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) | |
7a94283a LB |
169 | #define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) |
170 | #define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) | |
171 | #define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) | |
172 | #define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) | |
173 | #define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) | |
174 | #define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) | |
175 | #define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) | |
176 | #define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) | |
1da177e4 LT |
177 | #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) |
178 | #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) | |
179 | #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) | |
180 | #define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) | |
181 | #define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) | |
182 | #define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) | |
183 | #define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) | |
184 | #define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) | |
185 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) | |
186 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) | |
187 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) | |
188 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) | |
189 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) | |
190 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) | |
191 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) | |
192 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) | |
193 | ||
194 | /* | |
195 | * Mask of valid IRQs in the 32-bit IRQ register. We use | |
196 | * this to mark certain IRQs as being invalid. | |
197 | */ | |
198 | #define IXP2000_VALID_IRQ_MASK 0x0f0fffff | |
199 | ||
200 | /* | |
201 | * PCI config register access from core | |
202 | */ | |
203 | #define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) | |
204 | #define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) | |
205 | #define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) | |
206 | #define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) | |
207 | #define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) | |
208 | ||
209 | /* | |
210 | * PCI CSRs | |
211 | */ | |
212 | #define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) | |
213 | ||
214 | /* | |
215 | * PCI outbound interrupts | |
216 | */ | |
217 | #define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) | |
218 | #define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) | |
219 | /* | |
220 | * PCI communications | |
221 | */ | |
222 | #define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) | |
223 | #define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) | |
224 | #define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) | |
225 | #define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) | |
226 | #define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) | |
227 | #define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) | |
228 | #define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) | |
229 | #define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) | |
230 | ||
231 | /* | |
232 | * DMA engines | |
233 | */ | |
234 | #define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) | |
235 | #define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) | |
236 | #define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) | |
237 | #define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) | |
238 | #define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) | |
239 | #define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) | |
240 | #define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) | |
241 | #define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) | |
242 | #define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) | |
243 | #define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) | |
244 | #define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) | |
245 | #define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) | |
246 | #define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) | |
247 | #define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) | |
248 | #define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) | |
249 | #define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) | |
250 | #define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) | |
251 | #define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) | |
252 | #define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) | |
253 | /* | |
254 | * Size masks for BARs | |
255 | */ | |
256 | #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) | |
257 | #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) | |
258 | /* | |
259 | * Control and uEngine related | |
260 | */ | |
261 | #define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) | |
262 | #define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) | |
263 | #define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) | |
264 | #define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) | |
265 | #define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) | |
266 | #define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) | |
267 | /* | |
268 | * Inbound PCI interrupt control | |
269 | */ | |
270 | #define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) | |
271 | #define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) | |
272 | ||
273 | #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ | |
fa87cedd | 274 | #define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ |
1da177e4 LT |
275 | #define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ |
276 | ||
277 | /* These are from the IRQ register in the PCI ISR register */ | |
278 | #define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ | |
279 | #define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ | |
280 | #define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ | |
281 | #define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ | |
321ab6a5 | 282 | #define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ |
1da177e4 LT |
283 | |
284 | #define IXP2000_PCI_RST_REL (1 << 2) | |
285 | #define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) | |
286 | #define CFG_PCI_BOOT_HOST (1 << 2) | |
287 | #define CFG_BOOT_PROM (1 << 1) | |
288 | ||
289 | /* | |
290 | * SlowPort CSRs | |
291 | * | |
292 | * The slowport is used to access things like flash, SONET framer control | |
293 | * ports, slave microprocessors, CPLDs, and others of chip memory mapped | |
294 | * peripherals. | |
295 | */ | |
296 | #define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) | |
297 | ||
298 | #define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) | |
299 | #define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) | |
300 | #define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) | |
301 | #define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) | |
302 | #define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) | |
303 | #define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) | |
304 | #define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) | |
305 | #define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) | |
306 | #define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) | |
307 | #define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) | |
308 | #define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) | |
309 | ||
310 | /* | |
311 | * CCR values. | |
312 | * The CCR configures the clock division for the slowport interface. | |
313 | */ | |
314 | #define SLOWPORT_CCR_DIV_1 0x00 | |
315 | #define SLOWPORT_CCR_DIV_2 0x01 | |
316 | #define SLOWPORT_CCR_DIV_4 0x02 | |
317 | #define SLOWPORT_CCR_DIV_6 0x03 | |
318 | #define SLOWPORT_CCR_DIV_8 0x04 | |
319 | #define SLOWPORT_CCR_DIV_10 0x05 | |
320 | #define SLOWPORT_CCR_DIV_12 0x06 | |
321 | #define SLOWPORT_CCR_DIV_14 0x07 | |
322 | #define SLOWPORT_CCR_DIV_16 0x08 | |
323 | #define SLOWPORT_CCR_DIV_18 0x09 | |
324 | #define SLOWPORT_CCR_DIV_20 0x0a | |
325 | #define SLOWPORT_CCR_DIV_22 0x0b | |
326 | #define SLOWPORT_CCR_DIV_24 0x0c | |
327 | #define SLOWPORT_CCR_DIV_26 0x0d | |
328 | #define SLOWPORT_CCR_DIV_28 0x0e | |
329 | #define SLOWPORT_CCR_DIV_30 0x0f | |
330 | ||
331 | /* | |
332 | * PCR values. PCR configure the mode of the interface. | |
333 | */ | |
334 | #define SLOWPORT_MODE_FLASH 0x00 | |
335 | #define SLOWPORT_MODE_LUCENT 0x01 | |
336 | #define SLOWPORT_MODE_PMC_SIERRA 0x02 | |
337 | #define SLOWPORT_MODE_INTEL_UP 0x03 | |
338 | #define SLOWPORT_MODE_MOTOROLA_UP 0x04 | |
339 | ||
340 | /* | |
341 | * ADC values. Defines data and address bus widths. | |
342 | */ | |
343 | #define SLOWPORT_ADDR_WIDTH_8 0x00 | |
344 | #define SLOWPORT_ADDR_WIDTH_16 0x01 | |
345 | #define SLOWPORT_ADDR_WIDTH_24 0x02 | |
346 | #define SLOWPORT_ADDR_WIDTH_32 0x03 | |
347 | #define SLOWPORT_DATA_WIDTH_8 0x00 | |
348 | #define SLOWPORT_DATA_WIDTH_16 0x10 | |
349 | #define SLOWPORT_DATA_WIDTH_24 0x20 | |
350 | #define SLOWPORT_DATA_WIDTH_32 0x30 | |
351 | ||
352 | /* | |
353 | * Masks and shifts for various fields in the WTC and RTC registers. | |
354 | */ | |
355 | #define SLOWPORT_WRTC_MASK_HD 0x0003 | |
a04f2d9d LB |
356 | #define SLOWPORT_WRTC_MASK_PW 0x003c |
357 | #define SLOWPORT_WRTC_MASK_SU 0x03c0 | |
1da177e4 LT |
358 | |
359 | #define SLOWPORT_WRTC_SHIFT_HD 0x00 | |
360 | #define SLOWPORT_WRTC_SHIFT_SU 0x02 | |
361 | #define SLOWPORT_WRTC_SHFIT_PW 0x06 | |
362 | ||
363 | ||
364 | /* | |
365 | * GPIO registers & GPIO interface. | |
366 | */ | |
367 | #define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) | |
368 | #define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) | |
369 | #define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) | |
370 | #define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) | |
371 | #define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) | |
372 | #define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) | |
373 | #define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) | |
374 | #define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) | |
375 | #define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) | |
376 | #define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) | |
377 | #define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) | |
378 | #define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) | |
379 | #define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) | |
380 | #define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) | |
381 | #define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) | |
382 | #define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) | |
383 | #define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) | |
384 | #define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) | |
385 | ||
386 | /* | |
387 | * "Global" registers...whatever that's supposed to mean. | |
388 | */ | |
389 | #define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) | |
390 | #define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) | |
391 | ||
1da177e4 LT |
392 | #define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 |
393 | #define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 | |
394 | #define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 | |
395 | #define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 | |
396 | #define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 | |
397 | #define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 | |
398 | #define IXP2000_MAJ_REV_MASK 0x000000F0 | |
399 | #define IXP2000_MIN_REV_MASK 0x0000000F | |
400 | #define IXP2000_PROD_ID_MASK 0xFFFFFFFF | |
401 | ||
e4fe1981 | 402 | #define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) |
1da177e4 LT |
403 | #define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) |
404 | #define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) | |
405 | #define IXP2000_RESET0 GLOBAL_REG(0x0c) | |
406 | #define IXP2000_RESET1 GLOBAL_REG(0x10) | |
407 | #define IXP2000_CCR GLOBAL_REG(0x14) | |
408 | #define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) | |
409 | ||
410 | #define RSTALL (1 << 16) | |
411 | #define WDT_RESET_ENABLE 0x01000000 | |
412 | ||
413 | ||
3b90c9c3 LB |
414 | /* |
415 | * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF | |
416 | * units, but the registers that differ between the two don't overlap, | |
417 | * so we can have one register list for both. | |
418 | */ | |
419 | #define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) | |
420 | #define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) | |
421 | #define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) | |
422 | #define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) | |
423 | #define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) | |
424 | #define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) | |
425 | #define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) | |
426 | #define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) | |
427 | #define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) | |
428 | #define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) | |
429 | #define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) | |
430 | #define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) | |
431 | #define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) | |
432 | #define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) | |
433 | #define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) | |
434 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) | |
435 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) | |
436 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) | |
437 | #define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) | |
438 | #define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) | |
439 | #define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) | |
440 | #define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) | |
441 | #define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) | |
442 | #define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) | |
443 | #define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) | |
444 | #define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) | |
445 | #define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) | |
446 | #define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) | |
447 | #define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) | |
448 | #define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) | |
449 | #define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) | |
450 | #define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) | |
451 | #define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) | |
452 | #define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) | |
453 | #define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) | |
454 | #define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) | |
455 | ||
456 | ||
1da177e4 | 457 | #endif /* _IXP2000_H_ */ |