[net-next-2.6.git] / arch / arm / mach-imx / mach-mx21ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * Memory-mapped I/O on MX21ADS base board
 */
#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
#define MX21ADS_MMIO_SIZE        SZ_16M

#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
		(MX21ADS_MMIO_BASE_ADDR + (offset))

#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)

/* MX21ADS_IO_REG bit definitions */
#define MX21ADS_IO_SD_WP        0x0001 /* read */
#define MX21ADS_IO_TP6          0x0001 /* write */
#define MX21ADS_IO_SW_SEL       0x0002 /* read */
#define MX21ADS_IO_TP7          0x0002 /* write */
#define MX21ADS_IO_RESET_E_UART 0x0004
#define MX21ADS_IO_RESET_BASE   0x0008
#define MX21ADS_IO_CSI_CTL2     0x0010
#define MX21ADS_IO_CSI_CTL1     0x0020
#define MX21ADS_IO_CSI_CTL0     0x0040
#define MX21ADS_IO_UART1_EN     0x0080
#define MX21ADS_IO_UART4_EN     0x0100
#define MX21ADS_IO_LCDON        0x0200
#define MX21ADS_IO_IRDA_EN      0x0400
#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
#define MX21ADS_IO_IRDA_MD0_B   0x1000
#define MX21ADS_IO_IRDA_MD1     0x2000
#define MX21ADS_IO_LED4_ON      0x4000
#define MX21ADS_IO_LED3_ON      0x8000

static unsigned int mx21ads_pins[] = {

	/* CS8900A */
	(GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),

	/* UART1 */
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS,

	/* UART3 (IrDA) - only TXD and RXD */
	PE8_PF_UART3_TXD,
	PE9_PF_UART3_RXD,

	/* UART4 */
	PB26_AF_UART4_RTS,
	PB28_AF_UART4_TXD,
	PB29_AF_UART4_CTS,
	PB31_AF_UART4_RXD,

	/* LCDC */
	PA5_PF_LSCLK,
	PA6_PF_LD0,
	PA7_PF_LD1,
	PA8_PF_LD2,
	PA9_PF_LD3,
	PA10_PF_LD4,
	PA11_PF_LD5,
	PA12_PF_LD6,
	PA13_PF_LD7,
	PA14_PF_LD8,
	PA15_PF_LD9,
	PA16_PF_LD10,
	PA17_PF_LD11,
	PA18_PF_LD12,
	PA19_PF_LD13,
	PA20_PF_LD14,
	PA21_PF_LD15,
	PA22_PF_LD16,
	PA24_PF_REV,     /* Sharp panel dedicated signal */
	PA25_PF_CLS,     /* Sharp panel dedicated signal */
	PA26_PF_PS,      /* Sharp panel dedicated signal */
	PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
	PA28_PF_HSYNC,
	PA29_PF_VSYNC,
	PA30_PF_CONTRAST,
	PA31_PF_OE_ACD,

	/* MMC/SDHC */
	PE18_PF_SD1_D0,
	PE19_PF_SD1_D1,
	PE20_PF_SD1_D2,
	PE21_PF_SD1_D3,
	PE22_PF_SD1_CMD,
	PE23_PF_SD1_CLK,

	/* NFC */
	PF0_PF_NRFB,
	PF1_PF_NFCE,
	PF2_PF_NFWP,
	PF3_PF_NFCLE,
	PF4_PF_NFALE,
	PF5_PF_NFRE,
	PF6_PF_NFWE,
	PF7_PF_NFIO0,
	PF8_PF_NFIO1,
	PF9_PF_NFIO2,
	PF10_PF_NFIO3,
	PF11_PF_NFIO4,
	PF12_PF_NFIO5,
	PF13_PF_NFIO6,
	PF14_PF_NFIO7,
};

/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
static struct physmap_flash_data mx21ads_flash_data = {
	.width = 4,
};

static struct resource mx21ads_flash_resource = {
	.start = MX21_CS0_BASE_ADDR,
	.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device mx21ads_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &mx21ads_flash_data,
	},
	.num_resources = 1,
	.resource = &mx21ads_flash_resource,
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static struct imxuart_platform_data uart_norts_pdata = {
};


static int mx21ads_fb_init(struct platform_device *pdev)
{
	u16 tmp;

	tmp = __raw_readw(MX21ADS_IO_REG);
	tmp |= MX21ADS_IO_LCDON;
	__raw_writew(tmp, MX21ADS_IO_REG);
	return 0;
}

static void mx21ads_fb_exit(struct platform_device *pdev)
{
	u16 tmp;

	tmp = __raw_readw(MX21ADS_IO_REG);
	tmp &= ~MX21ADS_IO_LCDON;
	__raw_writew(tmp, MX21ADS_IO_REG);
}

/*
 * Connected is a portrait Sharp-QVGA display
 * of type: LQ035Q7DB02
 */
static struct imx_fb_videomode mx21ads_modes[] = {
	{
		.mode = {
			.name		= "Sharp-LQ035Q7",
			.refresh	= 60,
			.xres		= 240,
			.yres		= 320,
			.pixclock	= 188679, /* in ps (5.3MHz) */
			.hsync_len	= 2,
			.left_margin	= 6,
			.right_margin	= 16,
			.vsync_len	= 1,
			.upper_margin	= 8,
			.lower_margin	= 10,
		},
		.pcr		= 0xfb108bc7,
		.bpp		= 16,
	},
};

static struct imx_fb_platform_data mx21ads_fb_data = {
	.mode = mx21ads_modes,
	.num_modes = ARRAY_SIZE(mx21ads_modes),

	.pwmr		= 0x00a903ff,
	.lscr1		= 0x00120300,
	.dmacr		= 0x00020008,

	.init = mx21ads_fb_init,
	.exit = mx21ads_fb_exit,
};

static int mx21ads_sdhc_get_ro(struct device *dev)
{
	return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
}

static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
	void *data)
{
	int ret;

	ret = request_irq(IRQ_GPIOD(25), detect_irq,
		IRQF_TRIGGER_FALLING, "mmc-detect", data);
	if (ret)
		goto out;
	return 0;
out:
	return ret;
}

static void mx21ads_sdhc_exit(struct device *dev, void *data)
{
	free_irq(IRQ_GPIOD(25), data);
}

static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
	.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
	.get_ro = mx21ads_sdhc_get_ro,
	.init = mx21ads_sdhc_init,
	.exit = mx21ads_sdhc_exit,
};

static struct mxc_nand_platform_data mx21ads_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

static struct map_desc mx21ads_io_desc[] __initdata = {
	/*
	 * Memory-mapped I/O on MX21ADS Base board:
	 *   - CS8900A Ethernet controller
	 *   - ST16C2552CJ UART
	 *   - CPU and Base board version
	 *   - Base board I/O register
	 */
	{
		.virtual = MX21ADS_MMIO_BASE_ADDR,
		.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
		.length = MX21ADS_MMIO_SIZE,
		.type = MT_DEVICE,
	},
};

static void __init mx21ads_map_io(void)
{
	mx21_map_io();
	iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
}

static struct platform_device *platform_devices[] __initdata = {
	&mx21ads_nor_mtd_device,
};

static void __init mx21ads_board_init(void)
{
	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
			"mx21ads");

	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

static void __init mx21ads_timer_init(void)
{
	mx21_clocks_init(32768, 26000000);
}

static struct sys_timer mx21ads_timer = {
	.init	= mx21ads_timer_init,
};

MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
	/* maintainer: Freescale Semiconductor, Inc. */
	.phys_io        = MX21_AIPI_BASE_ADDR,
	.io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = MX21_PHYS_OFFSET + 0x100,
	.map_io         = mx21ads_map_io,
	.init_irq       = mx21_init_irq,
	.init_machine   = mx21ads_board_init,
	.timer          = &mx21ads_timer,
MACHINE_END
Commit	Line	Data
6b91edde IC	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#include <linux/platform_device.h>
	22	#include <linux/mtd/mtd.h>
	23	#include <linux/mtd/physmap.h>
	24	#include <linux/gpio.h>
	25	#include <mach/common.h>
	26	#include <mach/hardware.h>
	27	#include <asm/mach-types.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/time.h>
	30	#include <asm/mach/map.h>
	31	#include <mach/imx-uart.h>
	32	#include <mach/imxfb.h>
e835d88e	33	#include <mach/iomux-mx21.h>
6b91edde IC	34	#include <mach/mxc_nand.h>
6b91edde IC	35	#include <mach/mmc.h>
6b91edde IC	36
	37	#include "devices.h"
	38
d393d43f UKK	39	/*
	40	* Memory-mapped I/O on MX21ADS base board
	41	*/
	42	#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
	43	#define MX21ADS_MMIO_SIZE SZ_16M
	44
	45	#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
	46	(MX21ADS_MMIO_BASE_ADDR + (offset))
	47
	48	#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
	49	#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
	50	#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
	51	#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
	52	#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
	53
	54	/* MX21ADS_IO_REG bit definitions */
	55	#define MX21ADS_IO_SD_WP 0x0001 /* read */
	56	#define MX21ADS_IO_TP6 0x0001 /* write */
	57	#define MX21ADS_IO_SW_SEL 0x0002 /* read */
	58	#define MX21ADS_IO_TP7 0x0002 /* write */
	59	#define MX21ADS_IO_RESET_E_UART 0x0004
	60	#define MX21ADS_IO_RESET_BASE 0x0008
	61	#define MX21ADS_IO_CSI_CTL2 0x0010
	62	#define MX21ADS_IO_CSI_CTL1 0x0020
	63	#define MX21ADS_IO_CSI_CTL0 0x0040
	64	#define MX21ADS_IO_UART1_EN 0x0080
	65	#define MX21ADS_IO_UART4_EN 0x0100
	66	#define MX21ADS_IO_LCDON 0x0200
	67	#define MX21ADS_IO_IRDA_EN 0x0400
	68	#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
	69	#define MX21ADS_IO_IRDA_MD0_B 0x1000
	70	#define MX21ADS_IO_IRDA_MD1 0x2000
	71	#define MX21ADS_IO_LED4_ON 0x4000
	72	#define MX21ADS_IO_LED3_ON 0x8000
	73
6b91edde IC	74	static unsigned int mx21ads_pins[] = {
	75
	76	/* CS8900A */
	77	(GPIO_PORTE \| GPIO_GPIO \| GPIO_IN \| 11),
	78
	79	/* UART1 */
	80	PE12_PF_UART1_TXD,
	81	PE13_PF_UART1_RXD,
	82	PE14_PF_UART1_CTS,
	83	PE15_PF_UART1_RTS,
	84
	85	/* UART3 (IrDA) - only TXD and RXD */
	86	PE8_PF_UART3_TXD,
	87	PE9_PF_UART3_RXD,
	88
	89	/* UART4 */
	90	PB26_AF_UART4_RTS,
	91	PB28_AF_UART4_TXD,
	92	PB29_AF_UART4_CTS,
	93	PB31_AF_UART4_RXD,
	94
	95	/* LCDC */
	96	PA5_PF_LSCLK,
	97	PA6_PF_LD0,
	98	PA7_PF_LD1,
	99	PA8_PF_LD2,
	100	PA9_PF_LD3,
	101	PA10_PF_LD4,
	102	PA11_PF_LD5,
	103	PA12_PF_LD6,
	104	PA13_PF_LD7,
	105	PA14_PF_LD8,
	106	PA15_PF_LD9,
	107	PA16_PF_LD10,
	108	PA17_PF_LD11,
	109	PA18_PF_LD12,
	110	PA19_PF_LD13,
	111	PA20_PF_LD14,
	112	PA21_PF_LD15,
	113	PA22_PF_LD16,
	114	PA24_PF_REV, /* Sharp panel dedicated signal */
	115	PA25_PF_CLS, /* Sharp panel dedicated signal */
	116	PA26_PF_PS, /* Sharp panel dedicated signal */
	117	PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
	118	PA28_PF_HSYNC,
	119	PA29_PF_VSYNC,
	120	PA30_PF_CONTRAST,
	121	PA31_PF_OE_ACD,
	122
	123	/* MMC/SDHC */
	124	PE18_PF_SD1_D0,
	125	PE19_PF_SD1_D1,
	126	PE20_PF_SD1_D2,
	127	PE21_PF_SD1_D3,
	128	PE22_PF_SD1_CMD,
	129	PE23_PF_SD1_CLK,
	130
	131	/* NFC */
	132	PF0_PF_NRFB,
	133	PF1_PF_NFCE,
	134	PF2_PF_NFWP,
	135	PF3_PF_NFCLE,
	136	PF4_PF_NFALE,
	137	PF5_PF_NFRE,
138	PF6_PF_NFWE,
139	PF7_PF_NFIO0,
140	PF8_PF_NFIO1,
141	PF9_PF_NFIO2,
142	PF10_PF_NFIO3,
143	PF11_PF_NFIO4,
144	PF12_PF_NFIO5,
145	PF13_PF_NFIO6,
146	PF14_PF_NFIO7,
147	};
148
149	/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
150	static struct physmap_flash_data mx21ads_flash_data = {
151	.width = 4,
152	};
153
154	static struct resource mx21ads_flash_resource = {
3f35d1f5 UKK	155	.start = MX21_CS0_BASE_ADDR,
3f35d1f5 UKK	156	.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
6b91edde IC	157	.flags = IORESOURCE_MEM,
	158	};
	159
	160	static struct platform_device mx21ads_nor_mtd_device = {
	161	.name = "physmap-flash",
	162	.id = 0,
	163	.dev = {
	164	.platform_data = &mx21ads_flash_data,
	165	},
	166	.num_resources = 1,
	167	.resource = &mx21ads_flash_resource,
	168	};
	169
	170	static struct imxuart_platform_data uart_pdata = {
	171	.flags = IMXUART_HAVE_RTSCTS,
	172	};
	173
	174	static struct imxuart_platform_data uart_norts_pdata = {
	175	};
	176
	177
	178	static int mx21ads_fb_init(struct platform_device *pdev)
	179	{
	180	u16 tmp;
	181
	182	tmp = __raw_readw(MX21ADS_IO_REG);
	183	tmp \|= MX21ADS_IO_LCDON;
	184	__raw_writew(tmp, MX21ADS_IO_REG);
	185	return 0;
	186	}
	187
	188	static void mx21ads_fb_exit(struct platform_device *pdev)
	189	{
	190	u16 tmp;
	191
	192	tmp = __raw_readw(MX21ADS_IO_REG);
	193	tmp &= ~MX21ADS_IO_LCDON;
	194	__raw_writew(tmp, MX21ADS_IO_REG);
	195	}
	196
	197	/*
	198	* Connected is a portrait Sharp-QVGA display
	199	* of type: LQ035Q7DB02
	200	*/
c35d3a41 SH	201	static struct imx_fb_videomode mx21ads_modes[] = {
	202	{
	203	.mode = {
	204	.name = "Sharp-LQ035Q7",
	205	.refresh = 60,
	206	.xres = 240,
	207	.yres = 320,
	208	.pixclock = 188679, /* in ps (5.3MHz) */
	209	.hsync_len = 2,
	210	.left_margin = 6,
	211	.right_margin = 16,
	212	.vsync_len = 1,
	213	.upper_margin = 8,
	214	.lower_margin = 10,
	215	},
	216	.pcr = 0xfb108bc7,
	217	.bpp = 16,
	218	},
	219	};
	220
6b91edde	221	static struct imx_fb_platform_data mx21ads_fb_data = {
c35d3a41 SH	222	.mode = mx21ads_modes,
	223	.num_modes = ARRAY_SIZE(mx21ads_modes),
	224
	225	.pwmr = 0x00a903ff,
	226	.lscr1 = 0x00120300,
	227	.dmacr = 0x00020008,
6b91edde IC	228
	229	.init = mx21ads_fb_init,
	230	.exit = mx21ads_fb_exit,
	231	};
	232
	233	static int mx21ads_sdhc_get_ro(struct device *dev)
	234	{
	235	return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
	236	}
	237
	238	static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
	239	void *data)
	240	{
	241	int ret;
	242
	243	ret = request_irq(IRQ_GPIOD(25), detect_irq,
	244	IRQF_TRIGGER_FALLING, "mmc-detect", data);
	245	if (ret)
	246	goto out;
	247	return 0;
	248	out:
	249	return ret;
	250	}
	251
	252	static void mx21ads_sdhc_exit(struct device dev, void data)
	253	{
	254	free_irq(IRQ_GPIOD(25), data);
	255	}
	256
	257	static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
	258	.ocr_avail = MMC_VDD_29_30 \| MMC_VDD_30_31, /* 3.0V */
	259	.get_ro = mx21ads_sdhc_get_ro,
	260	.init = mx21ads_sdhc_init,
	261	.exit = mx21ads_sdhc_exit,
	262	};
	263
	264	static struct mxc_nand_platform_data mx21ads_nand_board_info = {
	265	.width = 1,
	266	.hw_ecc = 1,
	267	};
	268
	269	static struct map_desc mx21ads_io_desc[] __initdata = {
	270	/*
	271	* Memory-mapped I/O on MX21ADS Base board:
	272	* - CS8900A Ethernet controller
	273	* - ST16C2552CJ UART
	274	* - CPU and Base board version
	275	* - Base board I/O register
	276	*/
	277	{
	278	.virtual = MX21ADS_MMIO_BASE_ADDR,
3f35d1f5	279	.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
6b91edde IC	280	.length = MX21ADS_MMIO_SIZE,
	281	.type = MT_DEVICE,
	282	},
	283	};
	284
	285	static void __init mx21ads_map_io(void)
	286	{
	287	mx21_map_io();
	288	iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
	289	}
	290
	291	static struct platform_device *platform_devices[] __initdata = {
	292	&mx21ads_nor_mtd_device,
	293	};
	294
	295	static void __init mx21ads_board_init(void)
	296	{
	297	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
	298	"mx21ads");
	299
551823e7 UKK	300	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
	301	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
	302	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
6b91edde IC	303	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
6b91edde IC	304	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
3636a145	305	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
6b91edde IC	306
	307	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	308	}
	309
	310	static void __init mx21ads_timer_init(void)
	311	{
	312	mx21_clocks_init(32768, 26000000);
	313	}
	314
	315	static struct sys_timer mx21ads_timer = {
	316	.init = mx21ads_timer_init,
	317	};
	318
	319	MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
	320	/* maintainer: Freescale Semiconductor, Inc. */
3f35d1f5 UKK	321	.phys_io = MX21_AIPI_BASE_ADDR,
3f35d1f5 UKK	322	.io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
34101237	323	.boot_params = MX21_PHYS_OFFSET + 0x100,
6b91edde	324	.map_io = mx21ads_map_io,
c5aa0ad0	325	.init_irq = mx21_init_irq,
6b91edde IC	326	.init_machine = mx21ads_board_init,
	327	.timer = &mx21ads_timer,
	328	MACHINE_END