[net-next-2.6.git] / arch / arm / mach-ep93xx / clock.c

/*
 * arch/arm/mach-ep93xx/clock.c
 * Clock control for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>

#include <asm/clkdev.h>
#include <asm/div64.h>


struct clk {
	struct clk	*parent;
	unsigned long	rate;
	int		users;
	int		sw_locked;
	void __iomem	*enable_reg;
	u32		enable_mask;

	unsigned long	(*get_rate)(struct clk *clk);
	int		(*set_rate)(struct clk *clk, unsigned long rate);
};


static unsigned long get_uart_rate(struct clk *clk);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
static int set_div_rate(struct clk *clk, unsigned long rate);
static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);

static struct clk clk_xtali = {
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_uart1 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U1EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart2 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U2EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart3 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U3EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_pll1 = {
	.parent		= &clk_xtali,
};
static struct clk clk_f = {
	.parent		= &clk_pll1,
};
static struct clk clk_h = {
	.parent		= &clk_pll1,
};
static struct clk clk_p = {
	.parent		= &clk_pll1,
};
static struct clk clk_pll2 = {
	.parent		= &clk_xtali,
};
static struct clk clk_usb_host = {
	.parent		= &clk_pll2,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_USH_EN,
};
static struct clk clk_keypad = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_KEYTCHCLKDIV,
	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	.set_rate	= set_keytchclk_rate,
};
static struct clk clk_spi = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_pwm = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};

static struct clk clk_video = {
	.sw_locked	= 1,
	.enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
	.enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

static struct clk clk_i2s_mclk = {
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

static struct clk clk_i2s_sclk = {
	.sw_locked	= 1,
	.parent		= &clk_i2s_mclk,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
	.set_rate	= set_i2s_sclk_rate,
};

static struct clk clk_i2s_lrclk = {
	.sw_locked	= 1,
	.parent		= &clk_i2s_sclk,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
	.set_rate	= set_i2s_lrclk_rate,
};

/* DMA Clocks */
static struct clk clk_m2p0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P0,
};
static struct clk clk_m2p1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P1,
};
static struct clk clk_m2p2 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P2,
};
static struct clk clk_m2p3 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P3,
};
static struct clk clk_m2p4 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P4,
};
static struct clk clk_m2p5 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P5,
};
static struct clk clk_m2p6 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P6,
};
static struct clk clk_m2p7 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P7,
};
static struct clk clk_m2p8 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P8,
};
static struct clk clk_m2p9 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P9,
};
static struct clk clk_m2m0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M0,
};
static struct clk clk_m2m1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M1,
};

#define INIT_CK(dev,con,ck)					\
	{ .dev_id = dev, .con_id = con, .clk = ck }

static struct clk_lookup clocks[] = {
	INIT_CK(NULL,			"xtali",	&clk_xtali),
	INIT_CK("apb:uart1",		NULL,		&clk_uart1),
	INIT_CK("apb:uart2",		NULL,		&clk_uart2),
	INIT_CK("apb:uart3",		NULL,		&clk_uart3),
	INIT_CK(NULL,			"pll1",		&clk_pll1),
	INIT_CK(NULL,			"fclk",		&clk_f),
	INIT_CK(NULL,			"hclk",		&clk_h),
	INIT_CK(NULL,			"apb_pclk",	&clk_p),
	INIT_CK(NULL,			"pll2",		&clk_pll2),
	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
	INIT_CK("ep93xx-spi.0",		NULL,		&clk_spi),
	INIT_CK("ep93xx-i2s",		"mclk",		&clk_i2s_mclk),
	INIT_CK("ep93xx-i2s",		"sclk",		&clk_i2s_sclk),
	INIT_CK("ep93xx-i2s",		"lrclk",	&clk_i2s_lrclk),
	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
	INIT_CK(NULL,			"m2p2",		&clk_m2p2),
	INIT_CK(NULL,			"m2p3",		&clk_m2p3),
	INIT_CK(NULL,			"m2p4",		&clk_m2p4),
	INIT_CK(NULL,			"m2p5",		&clk_m2p5),
	INIT_CK(NULL,			"m2p6",		&clk_m2p6),
	INIT_CK(NULL,			"m2p7",		&clk_m2p7),
	INIT_CK(NULL,			"m2p8",		&clk_m2p8),
	INIT_CK(NULL,			"m2p9",		&clk_m2p9),
	INIT_CK(NULL,			"m2m0",		&clk_m2m0),
	INIT_CK(NULL,			"m2m1",		&clk_m2m1),
};

static DEFINE_SPINLOCK(clk_lock);

static void __clk_enable(struct clk *clk)
{
	if (!clk->users++) {
		if (clk->parent)
			__clk_enable(clk->parent);

		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v |= clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}
	}
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return -EINVAL;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	if (!--clk->users) {
		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v &= ~clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}

		if (clk->parent)
			__clk_disable(clk->parent);
	}
}

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

static unsigned long get_uart_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 value;

	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
		return rate;
	else
		return rate / 2;
}

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk->get_rate)
		return clk->get_rate(clk);

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
{
	u32 val;
	u32 div_bit;

	val = __raw_readl(clk->enable_reg);

	/*
	 * The Key Matrix and ADC clocks are configured using the same
	 * System Controller register.  The clock used will be either
	 * 1/4 or 1/16 the external clock rate depending on the
	 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	 * bit being set or cleared.
	 */
	div_bit = clk->enable_mask >> 15;

	if (rate == EP93XX_KEYTCHCLK_DIV4)
		val |= div_bit;
	else if (rate == EP93XX_KEYTCHCLK_DIV16)
		val &= ~div_bit;
	else
		return -EINVAL;

	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	clk->rate = rate;
	return 0;
}

static int calc_clk_div(struct clk *clk, unsigned long rate,
			int *psel, int *esel, int *pdiv, int *div)
{
	struct clk *mclk;
	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
	int i, found = 0, __div = 0, __pdiv = 0;

	/* Don't exceed the maximum rate */
	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
		       clk_xtali.rate / 4);
	rate = min(rate, max_rate);

	/*
	 * Try the two pll's and the external clock
	 * Because the valid predividers are 2, 2.5 and 3, we multiply
	 * all the clocks by 2 to avoid floating point math.
	 *
	 * This is based on the algorithm in the ep93xx raster guide:
	 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	 *
	 */
	for (i = 0; i < 3; i++) {
		if (i == 0)
			mclk = &clk_xtali;
		else if (i == 1)
			mclk = &clk_pll1;
		else
			mclk = &clk_pll2;
		mclk_rate = mclk->rate * 2;

		/* Try each predivider value */
		for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
			__div = mclk_rate / (rate * __pdiv);
			if (__div < 2 || __div > 127)
				continue;

			actual_rate = mclk_rate / (__pdiv * __div);

			if (!found || abs(actual_rate - rate) < rate_err) {
				*pdiv = __pdiv - 3;
				*div = __div;
				*psel = (i == 2);
				*esel = (i != 0);
				clk->parent = mclk;
				clk->rate = actual_rate;
				rate_err = abs(actual_rate - rate);
				found = 1;
			}
		}
	}

	if (!found)
		return -EINVAL;

	return 0;
}

static int set_div_rate(struct clk *clk, unsigned long rate)
{
	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
	u32 val;

	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	if (err)
		return err;

	/* Clear the esel, psel, pdiv and div bits */
	val = __raw_readl(clk->enable_reg);
	val &= ~0x7fff;

	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
		(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
		(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	return 0;
}

static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned val = __raw_readl(clk->enable_reg);

	if (rate == clk_i2s_mclk.rate / 2)
		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
					     clk->enable_reg);
	else if (rate == clk_i2s_mclk.rate / 4)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
					     clk->enable_reg);
	else
		return -EINVAL;

	clk_i2s_sclk.rate = rate;
	return 0;
}

static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned val = __raw_readl(clk->enable_reg) & 
		~EP93XX_I2SCLKDIV_LRDIV_MASK;
	
	if (rate == clk_i2s_sclk.rate / 32)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
					     clk->enable_reg);
	else if (rate == clk_i2s_sclk.rate / 64)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
					     clk->enable_reg);
	else if (rate == clk_i2s_sclk.rate / 128)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
					     clk->enable_reg);
	else
		return -EINVAL;

	clk_i2s_lrclk.rate = rate;
	return 0;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	if (clk->set_rate)
		return clk->set_rate(clk, rate);

	return -EINVAL;
}
EXPORT_SYMBOL(clk_set_rate);


static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
static char pclk_divisors[] = { 1, 2, 4, 8 };

/*
 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;

	rate = clk_xtali.rate;
	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
		rate >>= 1;

	return (unsigned long)rate;
}

static void __init ep93xx_dma_clock_init(void)
{
	clk_m2p0.rate = clk_h.rate;
	clk_m2p1.rate = clk_h.rate;
	clk_m2p2.rate = clk_h.rate;
	clk_m2p3.rate = clk_h.rate;
	clk_m2p4.rate = clk_h.rate;
	clk_m2p5.rate = clk_h.rate;
	clk_m2p6.rate = clk_h.rate;
	clk_m2p7.rate = clk_h.rate;
	clk_m2p8.rate = clk_h.rate;
	clk_m2p9.rate = clk_h.rate;
	clk_m2m0.rate = clk_h.rate;
	clk_m2m1.rate = clk_h.rate;
}

static int __init ep93xx_clock_init(void)
{
	u32 value;

	/* Determine the bootloader configured pll1 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
		clk_pll1.rate = clk_xtali.rate;
	else
		clk_pll1.rate = calc_pll_rate(value);

	/* Initialize the pll1 derived clocks */
	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
	ep93xx_dma_clock_init();

	/* Determine the bootloader configured pll2 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
		clk_pll2.rate = clk_xtali.rate;
	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
		clk_pll2.rate = calc_pll_rate(value);
	else
		clk_pll2.rate = 0;

	/* Initialize the pll2 derived clocks */
	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);

	/*
	 * EP93xx SSP clock rate was doubled in version E2. For more information
	 * see:
	 *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	 */
	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
		clk_spi.rate /= 2;

	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
		clk_f.rate / 1000000, clk_h.rate / 1000000,
		clk_p.rate / 1000000);

	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
	return 0;
}
postcore_initcall(ep93xx_clock_init);
Commit	Line	Data
1d81eedb LB	1	/*
	2	* arch/arm/mach-ep93xx/clock.c
	3	* Clock control for Cirrus EP93xx chips.
	4	*
	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or (at
	10	* your option) any later version.
	11	*/
	12
99acbb90 HS	13	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
99acbb90 HS	14
1d81eedb LB	15	#include <linux/kernel.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
51dd249e	18	#include <linux/module.h>
1d81eedb	19	#include <linux/string.h>
fced80c7	20	#include <linux/io.h>
ebd00c08 HS	21	#include <linux/spinlock.h>
	22
	23	#include <mach/hardware.h>
ae696fd5 RK	24
ae696fd5 RK	25	#include <asm/clkdev.h>
1d81eedb	26	#include <asm/div64.h>
1d81eedb	27
ff05c033	28
1d81eedb	29	struct clk {
ebd00c08	30	struct clk *parent;
1d81eedb LB	31	unsigned long rate;
1d81eedb LB	32	int users;
ff05c033	33	int sw_locked;
c3e3badd	34	void __iomem *enable_reg;
1d81eedb	35	u32 enable_mask;
ff05c033 HS	36
ff05c033 HS	37	unsigned long (get_rate)(struct clk clk);
701fac82	38	int (set_rate)(struct clk clk, unsigned long rate);
1d81eedb LB	39	};
1d81eedb LB	40
ff05c033 HS	41
	42	static unsigned long get_uart_rate(struct clk *clk);
	43
701fac82	44	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
c6012189	45	static int set_div_rate(struct clk *clk, unsigned long rate);
ed67ea82 RM	46	static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
ed67ea82 RM	47	static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
ebd00c08 HS	48
	49	static struct clk clk_xtali = {
	50	.rate = EP93XX_EXT_CLK_RATE,
	51	};
ff05c033	52	static struct clk clk_uart1 = {
ebd00c08	53	.parent = &clk_xtali,
ff05c033	54	.sw_locked = 1,
02239f0a HS	55	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	56	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
ff05c033 HS	57	.get_rate = get_uart_rate,
	58	};
	59	static struct clk clk_uart2 = {
ebd00c08	60	.parent = &clk_xtali,
ff05c033	61	.sw_locked = 1,
02239f0a HS	62	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	63	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
ff05c033 HS	64	.get_rate = get_uart_rate,
	65	};
	66	static struct clk clk_uart3 = {
ebd00c08	67	.parent = &clk_xtali,
ff05c033	68	.sw_locked = 1,
02239f0a HS	69	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	70	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
ff05c033	71	.get_rate = get_uart_rate,
ed519ded	72	};
ebd00c08 HS	73	static struct clk clk_pll1 = {
	74	.parent = &clk_xtali,
	75	};
	76	static struct clk clk_f = {
	77	.parent = &clk_pll1,
	78	};
	79	static struct clk clk_h = {
	80	.parent = &clk_pll1,
	81	};
	82	static struct clk clk_p = {
	83	.parent = &clk_pll1,
	84	};
	85	static struct clk clk_pll2 = {
	86	.parent = &clk_xtali,
	87	};
1d81eedb	88	static struct clk clk_usb_host = {
ebd00c08	89	.parent = &clk_pll2,
40702432 HS	90	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	91	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
1d81eedb	92	};
701fac82	93	static struct clk clk_keypad = {
ebd00c08	94	.parent = &clk_xtali,
701fac82 HS	95	.sw_locked = 1,
	96	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
	97	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	98	.set_rate = set_keytchclk_rate,
	99	};
4fec9978 MW	100	static struct clk clk_spi = {
	101	.parent = &clk_xtali,
	102	.rate = EP93XX_EXT_CLK_RATE,
	103	};
ef12379f	104	static struct clk clk_pwm = {
ebd00c08	105	.parent = &clk_xtali,
ef12379f HS	106	.rate = EP93XX_EXT_CLK_RATE,
ef12379f HS	107	};
1d81eedb	108
c6012189 RM	109	static struct clk clk_video = {
	110	.sw_locked = 1,
	111	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
	112	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	113	.set_rate = set_div_rate,
	114	};
	115
ed67ea82 RM	116	static struct clk clk_i2s_mclk = {
	117	.sw_locked = 1,
	118	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	119	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	120	.set_rate = set_div_rate,
	121	};
	122
	123	static struct clk clk_i2s_sclk = {
	124	.sw_locked = 1,
	125	.parent = &clk_i2s_mclk,
	126	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	127	.enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
	128	.set_rate = set_i2s_sclk_rate,
	129	};
	130
	131	static struct clk clk_i2s_lrclk = {
	132	.sw_locked = 1,
	133	.parent = &clk_i2s_sclk,
	134	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	135	.enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
	136	.set_rate = set_i2s_lrclk_rate,
	137	};
	138
1c8daabe RM	139	/* DMA Clocks */
1c8daabe RM	140	static struct clk clk_m2p0 = {
ebd00c08	141	.parent = &clk_h,
40702432 HS	142	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	143	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
1c8daabe RM	144	};
1c8daabe RM	145	static struct clk clk_m2p1 = {
ebd00c08	146	.parent = &clk_h,
40702432 HS	147	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	148	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
1c8daabe RM	149	};
1c8daabe RM	150	static struct clk clk_m2p2 = {
ebd00c08	151	.parent = &clk_h,
40702432 HS	152	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	153	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
1c8daabe RM	154	};
1c8daabe RM	155	static struct clk clk_m2p3 = {
ebd00c08	156	.parent = &clk_h,
40702432 HS	157	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	158	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
1c8daabe RM	159	};
1c8daabe RM	160	static struct clk clk_m2p4 = {
ebd00c08	161	.parent = &clk_h,
40702432 HS	162	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	163	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
1c8daabe RM	164	};
1c8daabe RM	165	static struct clk clk_m2p5 = {
ebd00c08	166	.parent = &clk_h,
40702432 HS	167	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	168	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
1c8daabe RM	169	};
1c8daabe RM	170	static struct clk clk_m2p6 = {
ebd00c08	171	.parent = &clk_h,
40702432 HS	172	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	173	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
1c8daabe RM	174	};
1c8daabe RM	175	static struct clk clk_m2p7 = {
ebd00c08	176	.parent = &clk_h,
40702432 HS	177	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	178	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
1c8daabe RM	179	};
1c8daabe RM	180	static struct clk clk_m2p8 = {
ebd00c08	181	.parent = &clk_h,
40702432 HS	182	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	183	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
1c8daabe RM	184	};
1c8daabe RM	185	static struct clk clk_m2p9 = {
ebd00c08	186	.parent = &clk_h,
40702432 HS	187	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	188	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
1c8daabe RM	189	};
1c8daabe RM	190	static struct clk clk_m2m0 = {
ebd00c08	191	.parent = &clk_h,
40702432 HS	192	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	193	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
1c8daabe RM	194	};
1c8daabe RM	195	static struct clk clk_m2m1 = {
ebd00c08	196	.parent = &clk_h,
40702432 HS	197	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	198	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
1c8daabe RM	199	};
1c8daabe RM	200
ae696fd5 RK	201	#define INIT_CK(dev,con,ck) \
	202	{ .dev_id = dev, .con_id = con, .clk = ck }
	203
	204	static struct clk_lookup clocks[] = {
ebd00c08	205	INIT_CK(NULL, "xtali", &clk_xtali),
701fac82 HS	206	INIT_CK("apb:uart1", NULL, &clk_uart1),
	207	INIT_CK("apb:uart2", NULL, &clk_uart2),
	208	INIT_CK("apb:uart3", NULL, &clk_uart3),
	209	INIT_CK(NULL, "pll1", &clk_pll1),
	210	INIT_CK(NULL, "fclk", &clk_f),
	211	INIT_CK(NULL, "hclk", &clk_h),
3126c7bc	212	INIT_CK(NULL, "apb_pclk", &clk_p),
701fac82 HS	213	INIT_CK(NULL, "pll2", &clk_pll2),
	214	INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
	215	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
c6012189	216	INIT_CK("ep93xx-fb", NULL, &clk_video),
4fec9978	217	INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
ed67ea82 RM	218	INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk),
	219	INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk),
	220	INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk),
ef12379f	221	INIT_CK(NULL, "pwm_clk", &clk_pwm),
701fac82 HS	222	INIT_CK(NULL, "m2p0", &clk_m2p0),
	223	INIT_CK(NULL, "m2p1", &clk_m2p1),
	224	INIT_CK(NULL, "m2p2", &clk_m2p2),
	225	INIT_CK(NULL, "m2p3", &clk_m2p3),
	226	INIT_CK(NULL, "m2p4", &clk_m2p4),
	227	INIT_CK(NULL, "m2p5", &clk_m2p5),
	228	INIT_CK(NULL, "m2p6", &clk_m2p6),
	229	INIT_CK(NULL, "m2p7", &clk_m2p7),
	230	INIT_CK(NULL, "m2p8", &clk_m2p8),
	231	INIT_CK(NULL, "m2p9", &clk_m2p9),
	232	INIT_CK(NULL, "m2m0", &clk_m2m0),
	233	INIT_CK(NULL, "m2m1", &clk_m2m1),
1d81eedb LB	234	};
1d81eedb LB	235
ebd00c08 HS	236	static DEFINE_SPINLOCK(clk_lock);
	237
	238	static void __clk_enable(struct clk *clk)
	239	{
	240	if (!clk->users++) {
	241	if (clk->parent)
	242	__clk_enable(clk->parent);
	243
	244	if (clk->enable_reg) {
	245	u32 v;
	246
	247	v = __raw_readl(clk->enable_reg);
	248	v \|= clk->enable_mask;
	249	if (clk->sw_locked)
	250	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	251	else
	252	__raw_writel(v, clk->enable_reg);
	253	}
	254	}
	255	}
1d81eedb LB	256
	257	int clk_enable(struct clk *clk)
	258	{
ebd00c08	259	unsigned long flags;
1d81eedb	260
ebd00c08 HS	261	if (!clk)
	262	return -EINVAL;
	263
	264	spin_lock_irqsave(&clk_lock, flags);
	265	__clk_enable(clk);
	266	spin_unlock_irqrestore(&clk_lock, flags);
1d81eedb LB	267
	268	return 0;
	269	}
0c5d5b70	270	EXPORT_SYMBOL(clk_enable);
1d81eedb	271
ebd00c08	272	static void __clk_disable(struct clk *clk)
1d81eedb	273	{
ebd00c08 HS	274	if (!--clk->users) {
	275	if (clk->enable_reg) {
	276	u32 v;
	277
	278	v = __raw_readl(clk->enable_reg);
	279	v &= ~clk->enable_mask;
	280	if (clk->sw_locked)
	281	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	282	else
	283	__raw_writel(v, clk->enable_reg);
	284	}
1d81eedb	285
ebd00c08 HS	286	if (clk->parent)
ebd00c08 HS	287	__clk_disable(clk->parent);
1d81eedb LB	288	}
1d81eedb LB	289	}
ebd00c08 HS	290
	291	void clk_disable(struct clk *clk)
	292	{
	293	unsigned long flags;
	294
	295	if (!clk)
	296	return;
	297
	298	spin_lock_irqsave(&clk_lock, flags);
	299	__clk_disable(clk);
	300	spin_unlock_irqrestore(&clk_lock, flags);
	301	}
0c5d5b70	302	EXPORT_SYMBOL(clk_disable);
1d81eedb	303
ff05c033 HS	304	static unsigned long get_uart_rate(struct clk *clk)
ff05c033 HS	305	{
ebd00c08	306	unsigned long rate = clk_get_rate(clk->parent);
ff05c033 HS	307	u32 value;
ff05c033 HS	308
ca8cbc83 MK	309	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
ca8cbc83 MK	310	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
ebd00c08	311	return rate;
ff05c033	312	else
ebd00c08	313	return rate / 2;
ff05c033 HS	314	}
ff05c033 HS	315
1d81eedb LB	316	unsigned long clk_get_rate(struct clk *clk)
1d81eedb LB	317	{
ff05c033 HS	318	if (clk->get_rate)
	319	return clk->get_rate(clk);
	320
1d81eedb LB	321	return clk->rate;
1d81eedb LB	322	}
0c5d5b70	323	EXPORT_SYMBOL(clk_get_rate);
1d81eedb	324
701fac82 HS	325	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
	326	{
	327	u32 val;
	328	u32 div_bit;
	329
	330	val = __raw_readl(clk->enable_reg);
	331
	332	/*
	333	* The Key Matrix and ADC clocks are configured using the same
	334	* System Controller register. The clock used will be either
	335	* 1/4 or 1/16 the external clock rate depending on the
	336	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	337	* bit being set or cleared.
	338	*/
	339	div_bit = clk->enable_mask >> 15;
	340
	341	if (rate == EP93XX_KEYTCHCLK_DIV4)
	342	val \|= div_bit;
	343	else if (rate == EP93XX_KEYTCHCLK_DIV16)
	344	val &= ~div_bit;
	345	else
	346	return -EINVAL;
	347
	348	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	349	clk->rate = rate;
	350	return 0;
	351	}
	352
ebd00c08 HS	353	static int calc_clk_div(struct clk *clk, unsigned long rate,
ebd00c08 HS	354	int psel, int esel, int pdiv, int div)
c6012189	355	{
ebd00c08 HS	356	struct clk *mclk;
ebd00c08 HS	357	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
c6012189 RM	358	int i, found = 0, __div = 0, __pdiv = 0;
	359
	360	/* Don't exceed the maximum rate */
	361	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
ebd00c08	362	clk_xtali.rate / 4);
c6012189 RM	363	rate = min(rate, max_rate);
	364
	365	/*
	366	* Try the two pll's and the external clock
	367	* Because the valid predividers are 2, 2.5 and 3, we multiply
	368	* all the clocks by 2 to avoid floating point math.
	369	*
	370	* This is based on the algorithm in the ep93xx raster guide:
	371	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	372	*
	373	*/
	374	for (i = 0; i < 3; i++) {
	375	if (i == 0)
ebd00c08	376	mclk = &clk_xtali;
c6012189	377	else if (i == 1)
ebd00c08 HS	378	mclk = &clk_pll1;
	379	else
	380	mclk = &clk_pll2;
	381	mclk_rate = mclk->rate * 2;
c6012189 RM	382
	383	/* Try each predivider value */
	384	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
	385	__div = mclk_rate / (rate * __pdiv);
	386	if (__div < 2 \|\| __div > 127)
	387	continue;
	388
	389	actual_rate = mclk_rate / (__pdiv * __div);
	390
	391	if (!found \|\| abs(actual_rate - rate) < rate_err) {
	392	*pdiv = __pdiv - 3;
	393	*div = __div;
	394	*psel = (i == 2);
	395	*esel = (i != 0);
ebd00c08 HS	396	clk->parent = mclk;
ebd00c08 HS	397	clk->rate = actual_rate;
c6012189 RM	398	rate_err = abs(actual_rate - rate);
	399	found = 1;
	400	}
	401	}
	402	}
	403
	404	if (!found)
ebd00c08	405	return -EINVAL;
c6012189	406
ebd00c08	407	return 0;
c6012189 RM	408	}
	409
	410	static int set_div_rate(struct clk *clk, unsigned long rate)
	411	{
ebd00c08	412	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
c6012189 RM	413	u32 val;
c6012189 RM	414
ebd00c08 HS	415	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	416	if (err)
	417	return err;
c6012189 RM	418
	419	/* Clear the esel, psel, pdiv and div bits */
	420	val = __raw_readl(clk->enable_reg);
	421	val &= ~0x7fff;
	422
	423	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	424	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|
	425	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|
	426	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;
	427	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	428	return 0;
	429	}
	430
ed67ea82 RM	431	static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
	432	{
	433	unsigned val = __raw_readl(clk->enable_reg);
	434
	435	if (rate == clk_i2s_mclk.rate / 2)
	436	ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
	437	clk->enable_reg);
	438	else if (rate == clk_i2s_mclk.rate / 4)
	439	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_SDIV,
	440	clk->enable_reg);
	441	else
	442	return -EINVAL;
	443
	444	clk_i2s_sclk.rate = rate;
	445	return 0;
	446	}
	447
	448	static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
	449	{
	450	unsigned val = __raw_readl(clk->enable_reg) &
	451	~EP93XX_I2SCLKDIV_LRDIV_MASK;
	452
	453	if (rate == clk_i2s_sclk.rate / 32)
	454	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV32,
	455	clk->enable_reg);
	456	else if (rate == clk_i2s_sclk.rate / 64)
	457	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV64,
	458	clk->enable_reg);
	459	else if (rate == clk_i2s_sclk.rate / 128)
	460	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV128,
	461	clk->enable_reg);
	462	else
	463	return -EINVAL;
	464
	465	clk_i2s_lrclk.rate = rate;
	466	return 0;
	467	}
	468
701fac82 HS	469	int clk_set_rate(struct clk *clk, unsigned long rate)
	470	{
	471	if (clk->set_rate)
	472	return clk->set_rate(clk, rate);
	473
	474	return -EINVAL;
	475	}
	476	EXPORT_SYMBOL(clk_set_rate);
	477
1d81eedb LB	478
	479	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
	480	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
	481	static char pclk_divisors[] = { 1, 2, 4, 8 };
	482
	483	/*
	484	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
	485	*/
	486	static unsigned long calc_pll_rate(u32 config_word)
	487	{
	488	unsigned long long rate;
	489	int i;
	490
ebd00c08	491	rate = clk_xtali.rate;
1d81eedb LB	492	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
	493	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
	494	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
	495	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
	496	rate >>= 1;
	497
	498	return (unsigned long)rate;
	499	}
	500
1c8daabe RM	501	static void __init ep93xx_dma_clock_init(void)
	502	{
	503	clk_m2p0.rate = clk_h.rate;
	504	clk_m2p1.rate = clk_h.rate;
	505	clk_m2p2.rate = clk_h.rate;
	506	clk_m2p3.rate = clk_h.rate;
	507	clk_m2p4.rate = clk_h.rate;
	508	clk_m2p5.rate = clk_h.rate;
	509	clk_m2p6.rate = clk_h.rate;
	510	clk_m2p7.rate = clk_h.rate;
	511	clk_m2p8.rate = clk_h.rate;
	512	clk_m2p9.rate = clk_h.rate;
	513	clk_m2m0.rate = clk_h.rate;
	514	clk_m2m1.rate = clk_h.rate;
	515	}
	516
51dd249e	517	static int __init ep93xx_clock_init(void)
1d81eedb LB	518	{
	519	u32 value;
	520
346e34ab HS	521	/* Determine the bootloader configured pll1 rate */
	522	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	523	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
ebd00c08	524	clk_pll1.rate = clk_xtali.rate;
346e34ab	525	else
1d81eedb	526	clk_pll1.rate = calc_pll_rate(value);
346e34ab HS	527
346e34ab HS	528	/* Initialize the pll1 derived clocks */
1d81eedb LB	529	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	530	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	531	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
1c8daabe	532	ep93xx_dma_clock_init();
1d81eedb	533
346e34ab	534	/* Determine the bootloader configured pll2 rate */
ba7c6a3b	535	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
346e34ab	536	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
ebd00c08	537	clk_pll2.rate = clk_xtali.rate;
346e34ab	538	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
1d81eedb	539	clk_pll2.rate = calc_pll_rate(value);
346e34ab	540	else
1d81eedb	541	clk_pll2.rate = 0;
346e34ab HS	542
346e34ab HS	543	/* Initialize the pll2 derived clocks */
1d81eedb LB	544	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
1d81eedb LB	545
4fec9978 MW	546	/*
	547	* EP93xx SSP clock rate was doubled in version E2. For more information
	548	* see:
	549	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	550	*/
	551	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
	552	clk_spi.rate /= 2;
	553
99acbb90	554	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
1d81eedb	555	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
99acbb90	556	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
1d81eedb LB	557	clk_f.rate / 1000000, clk_h.rate / 1000000,
1d81eedb LB	558	clk_p.rate / 1000000);
51dd249e	559
0a0300dc	560	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
51dd249e	561	return 0;
1d81eedb	562	}
a387f0f5	563	postcore_initcall(ep93xx_clock_init);