[net-next-2.6.git] / arch / arm / mach-ep93xx / clock.c

/*
 * arch/arm/mach-ep93xx/clock.c
 * Clock control for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>

#include <asm/clkdev.h>
#include <asm/div64.h>


struct clk {
	struct clk	*parent;
	unsigned long	rate;
	int		users;
	int		sw_locked;
	void __iomem	*enable_reg;
	u32		enable_mask;

	unsigned long	(*get_rate)(struct clk *clk);
	int		(*set_rate)(struct clk *clk, unsigned long rate);
};


static unsigned long get_uart_rate(struct clk *clk);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
static int set_div_rate(struct clk *clk, unsigned long rate);


static struct clk clk_xtali = {
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_uart1 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U1EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart2 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U2EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart3 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U3EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_pll1 = {
	.parent		= &clk_xtali,
};
static struct clk clk_f = {
	.parent		= &clk_pll1,
};
static struct clk clk_h = {
	.parent		= &clk_pll1,
};
static struct clk clk_p = {
	.parent		= &clk_pll1,
};
static struct clk clk_pll2 = {
	.parent		= &clk_xtali,
};
static struct clk clk_usb_host = {
	.parent		= &clk_pll2,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_USH_EN,
};
static struct clk clk_keypad = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_KEYTCHCLKDIV,
	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	.set_rate	= set_keytchclk_rate,
};
static struct clk clk_spi = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_pwm = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};

static struct clk clk_video = {
	.sw_locked	= 1,
	.enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
	.enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

/* DMA Clocks */
static struct clk clk_m2p0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P0,
};
static struct clk clk_m2p1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P1,
};
static struct clk clk_m2p2 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P2,
};
static struct clk clk_m2p3 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P3,
};
static struct clk clk_m2p4 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P4,
};
static struct clk clk_m2p5 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P5,
};
static struct clk clk_m2p6 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P6,
};
static struct clk clk_m2p7 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P7,
};
static struct clk clk_m2p8 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P8,
};
static struct clk clk_m2p9 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P9,
};
static struct clk clk_m2m0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M0,
};
static struct clk clk_m2m1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M1,
};

#define INIT_CK(dev,con,ck)					\
	{ .dev_id = dev, .con_id = con, .clk = ck }

static struct clk_lookup clocks[] = {
	INIT_CK(NULL,			"xtali",	&clk_xtali),
	INIT_CK("apb:uart1",		NULL,		&clk_uart1),
	INIT_CK("apb:uart2",		NULL,		&clk_uart2),
	INIT_CK("apb:uart3",		NULL,		&clk_uart3),
	INIT_CK(NULL,			"pll1",		&clk_pll1),
	INIT_CK(NULL,			"fclk",		&clk_f),
	INIT_CK(NULL,			"hclk",		&clk_h),
	INIT_CK(NULL,			"pclk",		&clk_p),
	INIT_CK(NULL,			"pll2",		&clk_pll2),
	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
	INIT_CK("ep93xx-spi.0",		NULL,		&clk_spi),
	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
	INIT_CK(NULL,			"m2p2",		&clk_m2p2),
	INIT_CK(NULL,			"m2p3",		&clk_m2p3),
	INIT_CK(NULL,			"m2p4",		&clk_m2p4),
	INIT_CK(NULL,			"m2p5",		&clk_m2p5),
	INIT_CK(NULL,			"m2p6",		&clk_m2p6),
	INIT_CK(NULL,			"m2p7",		&clk_m2p7),
	INIT_CK(NULL,			"m2p8",		&clk_m2p8),
	INIT_CK(NULL,			"m2p9",		&clk_m2p9),
	INIT_CK(NULL,			"m2m0",		&clk_m2m0),
	INIT_CK(NULL,			"m2m1",		&clk_m2m1),
};

static DEFINE_SPINLOCK(clk_lock);

static void __clk_enable(struct clk *clk)
{
	if (!clk->users++) {
		if (clk->parent)
			__clk_enable(clk->parent);

		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v |= clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}
	}
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return -EINVAL;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	if (!--clk->users) {
		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v &= ~clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}

		if (clk->parent)
			__clk_disable(clk->parent);
	}
}

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

static unsigned long get_uart_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 value;

	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
		return rate;
	else
		return rate / 2;
}

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk->get_rate)
		return clk->get_rate(clk);

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
{
	u32 val;
	u32 div_bit;

	val = __raw_readl(clk->enable_reg);

	/*
	 * The Key Matrix and ADC clocks are configured using the same
	 * System Controller register.  The clock used will be either
	 * 1/4 or 1/16 the external clock rate depending on the
	 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	 * bit being set or cleared.
	 */
	div_bit = clk->enable_mask >> 15;

	if (rate == EP93XX_KEYTCHCLK_DIV4)
		val |= div_bit;
	else if (rate == EP93XX_KEYTCHCLK_DIV16)
		val &= ~div_bit;
	else
		return -EINVAL;

	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	clk->rate = rate;
	return 0;
}

static int calc_clk_div(struct clk *clk, unsigned long rate,
			int *psel, int *esel, int *pdiv, int *div)
{
	struct clk *mclk;
	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
	int i, found = 0, __div = 0, __pdiv = 0;

	/* Don't exceed the maximum rate */
	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
		       clk_xtali.rate / 4);
	rate = min(rate, max_rate);

	/*
	 * Try the two pll's and the external clock
	 * Because the valid predividers are 2, 2.5 and 3, we multiply
	 * all the clocks by 2 to avoid floating point math.
	 *
	 * This is based on the algorithm in the ep93xx raster guide:
	 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	 *
	 */
	for (i = 0; i < 3; i++) {
		if (i == 0)
			mclk = &clk_xtali;
		else if (i == 1)
			mclk = &clk_pll1;
		else
			mclk = &clk_pll2;
		mclk_rate = mclk->rate * 2;

		/* Try each predivider value */
		for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
			__div = mclk_rate / (rate * __pdiv);
			if (__div < 2 || __div > 127)
				continue;

			actual_rate = mclk_rate / (__pdiv * __div);

			if (!found || abs(actual_rate - rate) < rate_err) {
				*pdiv = __pdiv - 3;
				*div = __div;
				*psel = (i == 2);
				*esel = (i != 0);
				clk->parent = mclk;
				clk->rate = actual_rate;
				rate_err = abs(actual_rate - rate);
				found = 1;
			}
		}
	}

	if (!found)
		return -EINVAL;

	return 0;
}

static int set_div_rate(struct clk *clk, unsigned long rate)
{
	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
	u32 val;

	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	if (err)
		return err;

	/* Clear the esel, psel, pdiv and div bits */
	val = __raw_readl(clk->enable_reg);
	val &= ~0x7fff;

	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
		(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
		(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	return 0;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	if (clk->set_rate)
		return clk->set_rate(clk, rate);

	return -EINVAL;
}
EXPORT_SYMBOL(clk_set_rate);


static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
static char pclk_divisors[] = { 1, 2, 4, 8 };

/*
 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;

	rate = clk_xtali.rate;
	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
		rate >>= 1;

	return (unsigned long)rate;
}

static void __init ep93xx_dma_clock_init(void)
{
	clk_m2p0.rate = clk_h.rate;
	clk_m2p1.rate = clk_h.rate;
	clk_m2p2.rate = clk_h.rate;
	clk_m2p3.rate = clk_h.rate;
	clk_m2p4.rate = clk_h.rate;
	clk_m2p5.rate = clk_h.rate;
	clk_m2p6.rate = clk_h.rate;
	clk_m2p7.rate = clk_h.rate;
	clk_m2p8.rate = clk_h.rate;
	clk_m2p9.rate = clk_h.rate;
	clk_m2m0.rate = clk_h.rate;
	clk_m2m1.rate = clk_h.rate;
}

static int __init ep93xx_clock_init(void)
{
	u32 value;

	/* Determine the bootloader configured pll1 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
		clk_pll1.rate = clk_xtali.rate;
	else
		clk_pll1.rate = calc_pll_rate(value);

	/* Initialize the pll1 derived clocks */
	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
	ep93xx_dma_clock_init();

	/* Determine the bootloader configured pll2 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
		clk_pll2.rate = clk_xtali.rate;
	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
		clk_pll2.rate = calc_pll_rate(value);
	else
		clk_pll2.rate = 0;

	/* Initialize the pll2 derived clocks */
	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);

	/*
	 * EP93xx SSP clock rate was doubled in version E2. For more information
	 * see:
	 *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	 */
	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
		clk_spi.rate /= 2;

	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
		clk_f.rate / 1000000, clk_h.rate / 1000000,
		clk_p.rate / 1000000);

	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
	return 0;
}
arch_initcall(ep93xx_clock_init);
Commit	Line	Data
1d81eedb LB	1	/*
	2	* arch/arm/mach-ep93xx/clock.c
	3	* Clock control for Cirrus EP93xx chips.
	4	*
	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or (at
	10	* your option) any later version.
	11	*/
	12
99acbb90 HS	13	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
99acbb90 HS	14
1d81eedb LB	15	#include <linux/kernel.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
51dd249e	18	#include <linux/module.h>
1d81eedb	19	#include <linux/string.h>
fced80c7	20	#include <linux/io.h>
ebd00c08 HS	21	#include <linux/spinlock.h>
	22
	23	#include <mach/hardware.h>
ae696fd5 RK	24
ae696fd5 RK	25	#include <asm/clkdev.h>
1d81eedb	26	#include <asm/div64.h>
1d81eedb	27
ff05c033	28
1d81eedb	29	struct clk {
ebd00c08	30	struct clk *parent;
1d81eedb LB	31	unsigned long rate;
1d81eedb LB	32	int users;
ff05c033	33	int sw_locked;
c3e3badd	34	void __iomem *enable_reg;
1d81eedb	35	u32 enable_mask;
ff05c033 HS	36
ff05c033 HS	37	unsigned long (get_rate)(struct clk clk);
701fac82	38	int (set_rate)(struct clk clk, unsigned long rate);
1d81eedb LB	39	};
1d81eedb LB	40
ff05c033 HS	41
	42	static unsigned long get_uart_rate(struct clk *clk);
	43
701fac82	44	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
c6012189	45	static int set_div_rate(struct clk *clk, unsigned long rate);
ff05c033	46
ebd00c08 HS	47
	48	static struct clk clk_xtali = {
	49	.rate = EP93XX_EXT_CLK_RATE,
	50	};
ff05c033	51	static struct clk clk_uart1 = {
ebd00c08	52	.parent = &clk_xtali,
ff05c033	53	.sw_locked = 1,
02239f0a HS	54	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	55	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
ff05c033 HS	56	.get_rate = get_uart_rate,
	57	};
	58	static struct clk clk_uart2 = {
ebd00c08	59	.parent = &clk_xtali,
ff05c033	60	.sw_locked = 1,
02239f0a HS	61	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	62	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
ff05c033 HS	63	.get_rate = get_uart_rate,
	64	};
	65	static struct clk clk_uart3 = {
ebd00c08	66	.parent = &clk_xtali,
ff05c033	67	.sw_locked = 1,
02239f0a HS	68	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	69	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
ff05c033	70	.get_rate = get_uart_rate,
ed519ded	71	};
ebd00c08 HS	72	static struct clk clk_pll1 = {
	73	.parent = &clk_xtali,
	74	};
	75	static struct clk clk_f = {
	76	.parent = &clk_pll1,
	77	};
	78	static struct clk clk_h = {
	79	.parent = &clk_pll1,
	80	};
	81	static struct clk clk_p = {
	82	.parent = &clk_pll1,
	83	};
	84	static struct clk clk_pll2 = {
	85	.parent = &clk_xtali,
	86	};
1d81eedb	87	static struct clk clk_usb_host = {
ebd00c08	88	.parent = &clk_pll2,
40702432 HS	89	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	90	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
1d81eedb	91	};
701fac82	92	static struct clk clk_keypad = {
ebd00c08	93	.parent = &clk_xtali,
701fac82 HS	94	.sw_locked = 1,
	95	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
	96	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	97	.set_rate = set_keytchclk_rate,
	98	};
4fec9978 MW	99	static struct clk clk_spi = {
	100	.parent = &clk_xtali,
	101	.rate = EP93XX_EXT_CLK_RATE,
	102	};
ef12379f	103	static struct clk clk_pwm = {
ebd00c08	104	.parent = &clk_xtali,
ef12379f HS	105	.rate = EP93XX_EXT_CLK_RATE,
ef12379f HS	106	};
1d81eedb	107
c6012189 RM	108	static struct clk clk_video = {
	109	.sw_locked = 1,
	110	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
	111	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	112	.set_rate = set_div_rate,
	113	};
	114
1c8daabe RM	115	/* DMA Clocks */
1c8daabe RM	116	static struct clk clk_m2p0 = {
ebd00c08	117	.parent = &clk_h,
40702432 HS	118	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	119	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
1c8daabe RM	120	};
1c8daabe RM	121	static struct clk clk_m2p1 = {
ebd00c08	122	.parent = &clk_h,
40702432 HS	123	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	124	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
1c8daabe RM	125	};
1c8daabe RM	126	static struct clk clk_m2p2 = {
ebd00c08	127	.parent = &clk_h,
40702432 HS	128	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	129	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
1c8daabe RM	130	};
1c8daabe RM	131	static struct clk clk_m2p3 = {
ebd00c08	132	.parent = &clk_h,
40702432 HS	133	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	134	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
1c8daabe RM	135	};
1c8daabe RM	136	static struct clk clk_m2p4 = {
ebd00c08	137	.parent = &clk_h,
40702432 HS	138	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	139	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
1c8daabe RM	140	};
1c8daabe RM	141	static struct clk clk_m2p5 = {
ebd00c08	142	.parent = &clk_h,
40702432 HS	143	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	144	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
1c8daabe RM	145	};
1c8daabe RM	146	static struct clk clk_m2p6 = {
ebd00c08	147	.parent = &clk_h,
40702432 HS	148	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	149	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
1c8daabe RM	150	};
1c8daabe RM	151	static struct clk clk_m2p7 = {
ebd00c08	152	.parent = &clk_h,
40702432 HS	153	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	154	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
1c8daabe RM	155	};
1c8daabe RM	156	static struct clk clk_m2p8 = {
ebd00c08	157	.parent = &clk_h,
40702432 HS	158	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	159	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
1c8daabe RM	160	};
1c8daabe RM	161	static struct clk clk_m2p9 = {
ebd00c08	162	.parent = &clk_h,
40702432 HS	163	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	164	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
1c8daabe RM	165	};
1c8daabe RM	166	static struct clk clk_m2m0 = {
ebd00c08	167	.parent = &clk_h,
40702432 HS	168	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	169	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
1c8daabe RM	170	};
1c8daabe RM	171	static struct clk clk_m2m1 = {
ebd00c08	172	.parent = &clk_h,
40702432 HS	173	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	174	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
1c8daabe RM	175	};
1c8daabe RM	176
ae696fd5 RK	177	#define INIT_CK(dev,con,ck) \
	178	{ .dev_id = dev, .con_id = con, .clk = ck }
	179
	180	static struct clk_lookup clocks[] = {
ebd00c08	181	INIT_CK(NULL, "xtali", &clk_xtali),
701fac82 HS	182	INIT_CK("apb:uart1", NULL, &clk_uart1),
	183	INIT_CK("apb:uart2", NULL, &clk_uart2),
	184	INIT_CK("apb:uart3", NULL, &clk_uart3),
	185	INIT_CK(NULL, "pll1", &clk_pll1),
	186	INIT_CK(NULL, "fclk", &clk_f),
	187	INIT_CK(NULL, "hclk", &clk_h),
	188	INIT_CK(NULL, "pclk", &clk_p),
	189	INIT_CK(NULL, "pll2", &clk_pll2),
	190	INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
	191	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
c6012189	192	INIT_CK("ep93xx-fb", NULL, &clk_video),
4fec9978	193	INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
ef12379f	194	INIT_CK(NULL, "pwm_clk", &clk_pwm),
701fac82 HS	195	INIT_CK(NULL, "m2p0", &clk_m2p0),
	196	INIT_CK(NULL, "m2p1", &clk_m2p1),
	197	INIT_CK(NULL, "m2p2", &clk_m2p2),
	198	INIT_CK(NULL, "m2p3", &clk_m2p3),
	199	INIT_CK(NULL, "m2p4", &clk_m2p4),
	200	INIT_CK(NULL, "m2p5", &clk_m2p5),
	201	INIT_CK(NULL, "m2p6", &clk_m2p6),
	202	INIT_CK(NULL, "m2p7", &clk_m2p7),
	203	INIT_CK(NULL, "m2p8", &clk_m2p8),
	204	INIT_CK(NULL, "m2p9", &clk_m2p9),
	205	INIT_CK(NULL, "m2m0", &clk_m2m0),
	206	INIT_CK(NULL, "m2m1", &clk_m2m1),
1d81eedb LB	207	};
1d81eedb LB	208
ebd00c08 HS	209	static DEFINE_SPINLOCK(clk_lock);
	210
	211	static void __clk_enable(struct clk *clk)
	212	{
	213	if (!clk->users++) {
	214	if (clk->parent)
	215	__clk_enable(clk->parent);
	216
	217	if (clk->enable_reg) {
	218	u32 v;
	219
	220	v = __raw_readl(clk->enable_reg);
	221	v \|= clk->enable_mask;
	222	if (clk->sw_locked)
	223	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	224	else
	225	__raw_writel(v, clk->enable_reg);
	226	}
	227	}
	228	}
1d81eedb LB	229
	230	int clk_enable(struct clk *clk)
	231	{
ebd00c08	232	unsigned long flags;
1d81eedb	233
ebd00c08 HS	234	if (!clk)
	235	return -EINVAL;
	236
	237	spin_lock_irqsave(&clk_lock, flags);
	238	__clk_enable(clk);
	239	spin_unlock_irqrestore(&clk_lock, flags);
1d81eedb LB	240
	241	return 0;
	242	}
0c5d5b70	243	EXPORT_SYMBOL(clk_enable);
1d81eedb	244
ebd00c08	245	static void __clk_disable(struct clk *clk)
1d81eedb	246	{
ebd00c08 HS	247	if (!--clk->users) {
	248	if (clk->enable_reg) {
	249	u32 v;
	250
	251	v = __raw_readl(clk->enable_reg);
	252	v &= ~clk->enable_mask;
	253	if (clk->sw_locked)
	254	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	255	else
	256	__raw_writel(v, clk->enable_reg);
	257	}
1d81eedb	258
ebd00c08 HS	259	if (clk->parent)
ebd00c08 HS	260	__clk_disable(clk->parent);
1d81eedb LB	261	}
1d81eedb LB	262	}
ebd00c08 HS	263
	264	void clk_disable(struct clk *clk)
	265	{
	266	unsigned long flags;
	267
	268	if (!clk)
	269	return;
	270
	271	spin_lock_irqsave(&clk_lock, flags);
	272	__clk_disable(clk);
	273	spin_unlock_irqrestore(&clk_lock, flags);
	274	}
0c5d5b70	275	EXPORT_SYMBOL(clk_disable);
1d81eedb	276
ff05c033 HS	277	static unsigned long get_uart_rate(struct clk *clk)
ff05c033 HS	278	{
ebd00c08	279	unsigned long rate = clk_get_rate(clk->parent);
ff05c033 HS	280	u32 value;
ff05c033 HS	281
ca8cbc83 MK	282	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
ca8cbc83 MK	283	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
ebd00c08	284	return rate;
ff05c033	285	else
ebd00c08	286	return rate / 2;
ff05c033 HS	287	}
ff05c033 HS	288
1d81eedb LB	289	unsigned long clk_get_rate(struct clk *clk)
1d81eedb LB	290	{
ff05c033 HS	291	if (clk->get_rate)
	292	return clk->get_rate(clk);
	293
1d81eedb LB	294	return clk->rate;
1d81eedb LB	295	}
0c5d5b70	296	EXPORT_SYMBOL(clk_get_rate);
1d81eedb	297
701fac82 HS	298	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
	299	{
	300	u32 val;
	301	u32 div_bit;
	302
	303	val = __raw_readl(clk->enable_reg);
	304
	305	/*
	306	* The Key Matrix and ADC clocks are configured using the same
	307	* System Controller register. The clock used will be either
	308	* 1/4 or 1/16 the external clock rate depending on the
	309	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	310	* bit being set or cleared.
	311	*/
	312	div_bit = clk->enable_mask >> 15;
	313
	314	if (rate == EP93XX_KEYTCHCLK_DIV4)
	315	val \|= div_bit;
	316	else if (rate == EP93XX_KEYTCHCLK_DIV16)
	317	val &= ~div_bit;
	318	else
	319	return -EINVAL;
	320
	321	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	322	clk->rate = rate;
	323	return 0;
	324	}
	325
ebd00c08 HS	326	static int calc_clk_div(struct clk *clk, unsigned long rate,
ebd00c08 HS	327	int psel, int esel, int pdiv, int div)
c6012189	328	{
ebd00c08 HS	329	struct clk *mclk;
ebd00c08 HS	330	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
c6012189 RM	331	int i, found = 0, __div = 0, __pdiv = 0;
	332
	333	/* Don't exceed the maximum rate */
	334	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
ebd00c08	335	clk_xtali.rate / 4);
c6012189 RM	336	rate = min(rate, max_rate);
	337
	338	/*
	339	* Try the two pll's and the external clock
	340	* Because the valid predividers are 2, 2.5 and 3, we multiply
	341	* all the clocks by 2 to avoid floating point math.
	342	*
	343	* This is based on the algorithm in the ep93xx raster guide:
	344	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	345	*
	346	*/
	347	for (i = 0; i < 3; i++) {
	348	if (i == 0)
ebd00c08	349	mclk = &clk_xtali;
c6012189	350	else if (i == 1)
ebd00c08 HS	351	mclk = &clk_pll1;
	352	else
	353	mclk = &clk_pll2;
	354	mclk_rate = mclk->rate * 2;
c6012189 RM	355
	356	/* Try each predivider value */
	357	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
	358	__div = mclk_rate / (rate * __pdiv);
	359	if (__div < 2 \|\| __div > 127)
	360	continue;
	361
	362	actual_rate = mclk_rate / (__pdiv * __div);
	363
	364	if (!found \|\| abs(actual_rate - rate) < rate_err) {
	365	*pdiv = __pdiv - 3;
	366	*div = __div;
	367	*psel = (i == 2);
	368	*esel = (i != 0);
ebd00c08 HS	369	clk->parent = mclk;
ebd00c08 HS	370	clk->rate = actual_rate;
c6012189 RM	371	rate_err = abs(actual_rate - rate);
	372	found = 1;
	373	}
	374	}
	375	}
	376
	377	if (!found)
ebd00c08	378	return -EINVAL;
c6012189	379
ebd00c08	380	return 0;
c6012189 RM	381	}
	382
	383	static int set_div_rate(struct clk *clk, unsigned long rate)
	384	{
ebd00c08	385	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
c6012189 RM	386	u32 val;
c6012189 RM	387
ebd00c08 HS	388	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	389	if (err)
	390	return err;
c6012189 RM	391
	392	/* Clear the esel, psel, pdiv and div bits */
	393	val = __raw_readl(clk->enable_reg);
	394	val &= ~0x7fff;
	395
	396	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	397	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|
	398	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|
	399	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;
	400	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	401	return 0;
	402	}
	403
701fac82 HS	404	int clk_set_rate(struct clk *clk, unsigned long rate)
	405	{
	406	if (clk->set_rate)
	407	return clk->set_rate(clk, rate);
	408
	409	return -EINVAL;
	410	}
	411	EXPORT_SYMBOL(clk_set_rate);
	412
1d81eedb LB	413
	414	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
	415	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
	416	static char pclk_divisors[] = { 1, 2, 4, 8 };
	417
	418	/*
	419	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
	420	*/
	421	static unsigned long calc_pll_rate(u32 config_word)
	422	{
	423	unsigned long long rate;
	424	int i;
	425
ebd00c08	426	rate = clk_xtali.rate;
1d81eedb LB	427	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
	428	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
	429	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
	430	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
	431	rate >>= 1;
	432
	433	return (unsigned long)rate;
	434	}
	435
1c8daabe RM	436	static void __init ep93xx_dma_clock_init(void)
	437	{
	438	clk_m2p0.rate = clk_h.rate;
	439	clk_m2p1.rate = clk_h.rate;
	440	clk_m2p2.rate = clk_h.rate;
	441	clk_m2p3.rate = clk_h.rate;
	442	clk_m2p4.rate = clk_h.rate;
	443	clk_m2p5.rate = clk_h.rate;
	444	clk_m2p6.rate = clk_h.rate;
	445	clk_m2p7.rate = clk_h.rate;
	446	clk_m2p8.rate = clk_h.rate;
	447	clk_m2p9.rate = clk_h.rate;
	448	clk_m2m0.rate = clk_h.rate;
	449	clk_m2m1.rate = clk_h.rate;
	450	}
	451
51dd249e	452	static int __init ep93xx_clock_init(void)
1d81eedb LB	453	{
	454	u32 value;
	455
346e34ab HS	456	/* Determine the bootloader configured pll1 rate */
	457	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	458	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
ebd00c08	459	clk_pll1.rate = clk_xtali.rate;
346e34ab	460	else
1d81eedb	461	clk_pll1.rate = calc_pll_rate(value);
346e34ab HS	462
346e34ab HS	463	/* Initialize the pll1 derived clocks */
1d81eedb LB	464	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	465	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	466	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
1c8daabe	467	ep93xx_dma_clock_init();
1d81eedb	468
346e34ab	469	/* Determine the bootloader configured pll2 rate */
ba7c6a3b	470	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
346e34ab	471	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
ebd00c08	472	clk_pll2.rate = clk_xtali.rate;
346e34ab	473	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
1d81eedb	474	clk_pll2.rate = calc_pll_rate(value);
346e34ab	475	else
1d81eedb	476	clk_pll2.rate = 0;
346e34ab HS	477
346e34ab HS	478	/* Initialize the pll2 derived clocks */
1d81eedb LB	479	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
1d81eedb LB	480
4fec9978 MW	481	/*
	482	* EP93xx SSP clock rate was doubled in version E2. For more information
	483	* see:
	484	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	485	*/
	486	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
	487	clk_spi.rate /= 2;
	488
99acbb90	489	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
1d81eedb	490	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
99acbb90	491	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
1d81eedb LB	492	clk_f.rate / 1000000, clk_h.rate / 1000000,
1d81eedb LB	493	clk_p.rate / 1000000);
51dd249e	494
0a0300dc	495	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
51dd249e	496	return 0;
1d81eedb	497	}
51dd249e	498	arch_initcall(ep93xx_clock_init);