[net-next-2.6.git] / arch / arm / mach-davinci / gpio.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <mach/gpio.h>

#include <asm/mach/irq.h>

static DEFINE_SPINLOCK(gpio_lock);

struct davinci_gpio {
	struct gpio_chip	chip;
	struct gpio_controller	__iomem *regs;
	int			irq_base;
};

#define chip2controller(chip)	\
	container_of(chip, struct davinci_gpio, chip)

static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];

/* create a non-inlined version */
static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
{
	return __gpio_to_controller(gpio);
}

static inline struct gpio_controller __iomem *irq2controller(int irq)
{
	struct gpio_controller __iomem *g;

	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);

	return g;
}

static int __init davinci_gpio_irq_setup(void);

/*--------------------------------------------------------------------------*/

/*
 * board setup code *MUST* set PINMUX0 and PINMUX1 as
 * needed, and enable the GPIO clock.
 */

static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio *d = chip2controller(chip);
	struct gpio_controller __iomem *g = d->regs;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock(&gpio_lock);
	temp = __raw_readl(&g->dir);
	if (out) {
		temp &= ~mask;
		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	__raw_writel(temp, &g->dir);
	spin_unlock(&gpio_lock);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio *d = chip2controller(chip);
	struct gpio_controller __iomem *g = d->regs;

	return (1 << offset) & __raw_readl(&g->in_data);
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio *d = chip2controller(chip);
	struct gpio_controller __iomem *g = d->regs;

	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}

static int __init davinci_gpio_setup(void)
{
	int i, base;
	unsigned ngpio;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = soc_info->gpio_num;
	if (ngpio == 0) {
		pr_err("GPIO setup:  how many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
		ngpio = DAVINCI_N_GPIO;

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

		chips[i].regs = gpio2controller(base);

		gpiochip_add(&chips[i].chip);
	}

	davinci_gpio_irq_setup();
	return 0;
}
pure_initcall(davinci_gpio_setup);

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(unsigned irq)
{
	struct gpio_controller __iomem *g = irq2controller(irq);
	u32 mask = (u32) get_irq_data(irq);

	__raw_writel(mask, &g->clr_falling);
	__raw_writel(mask, &g->clr_rising);
}

static void gpio_irq_enable(unsigned irq)
{
	struct gpio_controller __iomem *g = irq2controller(irq);
	u32 mask = (u32) get_irq_data(irq);
	unsigned status = irq_desc[irq].status;

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		__raw_writel(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		__raw_writel(mask, &g->set_rising);
}

static int gpio_irq_type(unsigned irq, unsigned trigger)
{
	struct gpio_controller __iomem *g = irq2controller(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	irq_desc[irq].status |= trigger;

	/* don't enable the IRQ if it's currently disabled */
	if (irq_desc[irq].depth == 0) {
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
			     ? &g->set_falling : &g->clr_falling);
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
			     ? &g->set_rising : &g->clr_rising);
	}
	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.enable		= gpio_irq_enable,
	.disable	= gpio_irq_disable,
	.set_type	= gpio_irq_type,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct gpio_controller __iomem *g = irq2controller(irq);
	u32 mask = 0xffff;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->mask(irq);
	desc->chip->ack(irq);
	while (1) {
		u32		status;
		int		n;
		int		res;

		/* ack any irqs */
		status = __raw_readl(&g->intstat) & mask;
		if (!status)
			break;
		__raw_writel(status, &g->intstat);
		if (irq & 1)
			status >>= 16;

		/* now demux them to the right lowlevel handler */
		n = (int)get_irq_data(irq);
		while (status) {
			res = ffs(status);
			n += res;
			generic_handle_irq(n - 1);
			status >>= res;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio *d = chip2controller(chip);

	if (d->irq_base >= 0)
		return d->irq_base + offset;
	else
		return -ENODEV;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/* NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < soc_info->gpio_unbanked)
		return soc_info->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
	struct gpio_controller __iomem *g = irq2controller(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int __init davinci_gpio_irq_setup(void)
{
	unsigned	gpio, irq, bank;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct gpio_controller	__iomem *g;

	ngpio = soc_info->gpio_num;

	bank_irq = soc_info->gpio_irq;
	if (bank_irq == 0) {
		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
		return -EINVAL;
	}

	clk = clk_get(NULL, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_base = soc_info->gpio_unbanked
			? -EINVAL
			: (soc_info->intc_irq_num + gpio);
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (soc_info->gpio_unbanked) {
		static struct irq_chip gpio_irqchip_unbanked;

		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
		gpio_irqchip_unbanked.name = "GPIO-AINTC";
		gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2controller(0);
		__raw_writel(~0, &g->set_falling);
		__raw_writel(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
			set_irq_chip(irq, &gpio_irqchip_unbanked);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_chip_data(irq, (__force void *) g);
			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
			gpio < ngpio;
			bank++, bank_irq++) {
		unsigned		i;

		/* disabled by default, enabled only as needed */
		g = gpio2controller(gpio);
		__raw_writel(~0, &g->clr_falling);
		__raw_writel(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		set_irq_chained_handler(bank_irq, gpio_irq_handler);
		set_irq_chip_data(bank_irq, (__force void *) g);
		set_irq_data(bank_irq, (void *) irq);

		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
			set_irq_chip(irq, &gpio_irqchip);
			set_irq_chip_data(irq, (__force void *) g);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID);
		}

		binten |= BIT(bank);
	}

done:
	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	__raw_writel(binten, soc_info->gpio_base + 0x08);

	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

	return 0;
}
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/errno.h>
	14	#include <linux/kernel.h>
3d9edf09 VB	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
3d9edf09	18
a09e64fb	19	#include <mach/gpio.h>
3d9edf09 VB	20
	21	#include <asm/mach/irq.h>
	22
dce1115b	23	static DEFINE_SPINLOCK(gpio_lock);
3d9edf09	24
dce1115b DB	25	struct davinci_gpio {
dce1115b DB	26	struct gpio_chip chip;
28552c2e	27	struct gpio_controller __iomem *regs;
7a36071e	28	int irq_base;
dce1115b	29	};
3d9edf09	30
ba4a984e CC	31	#define chip2controller(chip) \
	32	container_of(chip, struct davinci_gpio, chip)
	33
dce1115b	34	static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
3d9edf09	35
3d9edf09	36	/* create a non-inlined version */
28552c2e	37	static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
3d9edf09 VB	38	{
	39	return __gpio_to_controller(gpio);
	40	}
	41
21ce873d KH	42	static inline struct gpio_controller __iomem *irq2controller(int irq)
	43	{
	44	struct gpio_controller __iomem *g;
	45
	46	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
	47
	48	return g;
	49	}
	50
dc756026	51	static int __init davinci_gpio_irq_setup(void);
dce1115b DB	52
	53	/--------------------------------------------------------------------------/
	54
3d9edf09	55	/*
dce1115b DB	56	* board setup code MUST set PINMUX0 and PINMUX1 as
dce1115b DB	57	* needed, and enable the GPIO clock.
3d9edf09	58	*/
dce1115b	59
ba4a984e CC	60	static inline int __davinci_direction(struct gpio_chip *chip,
ba4a984e CC	61	unsigned offset, bool out, int value)
3d9edf09	62	{
ba4a984e	63	struct davinci_gpio *d = chip2controller(chip);
28552c2e	64	struct gpio_controller __iomem *g = d->regs;
dce1115b	65	u32 temp;
ba4a984e	66	u32 mask = 1 << offset;
3d9edf09	67
dce1115b DB	68	spin_lock(&gpio_lock);
dce1115b DB	69	temp = __raw_readl(&g->dir);
ba4a984e CC	70	if (out) {
	71	temp &= ~mask;
	72	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	73	} else {
	74	temp \|= mask;
	75	}
dce1115b DB	76	__raw_writel(temp, &g->dir);
dce1115b DB	77	spin_unlock(&gpio_lock);
3d9edf09	78
dce1115b DB	79	return 0;
dce1115b DB	80	}
3d9edf09	81
ba4a984e CC	82	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	83	{
	84	return __davinci_direction(chip, offset, false, 0);
	85	}
	86
	87	static int
	88	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	89	{
	90	return __davinci_direction(chip, offset, true, value);
	91	}
	92
3d9edf09 VB	93	/*
	94	* Read the pin's value (works even if it's set up as output);
	95	* returns zero/nonzero.
	96	*
	97	* Note that changes are synched to the GPIO clock, so reading values back
	98	* right after you've set them may give old values.
	99	*/
dce1115b	100	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	101	{
ba4a984e	102	struct davinci_gpio *d = chip2controller(chip);
28552c2e	103	struct gpio_controller __iomem *g = d->regs;
3d9edf09	104
dce1115b	105	return (1 << offset) & __raw_readl(&g->in_data);
3d9edf09	106	}
3d9edf09	107
dce1115b DB	108	/*
	109	* Assuming the pin is muxed as a gpio output, set its output value.
	110	*/
	111	static void
	112	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	113	{
ba4a984e	114	struct davinci_gpio *d = chip2controller(chip);
28552c2e	115	struct gpio_controller __iomem *g = d->regs;
3d9edf09	116
dce1115b DB	117	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
	118	}
	119
	120	static int __init davinci_gpio_setup(void)
	121	{
	122	int i, base;
a994955c MG	123	unsigned ngpio;
a994955c MG	124	struct davinci_soc_info *soc_info = &davinci_soc_info;
dce1115b	125
a994955c MG	126	/*
a994955c MG	127	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	128	* and "ngpio" is one more than the largest zero-based
	129	* bit index that's valid.
	130	*/
a994955c MG	131	ngpio = soc_info->gpio_num;
a994955c MG	132	if (ngpio == 0) {
474dad54 DB	133	pr_err("GPIO setup: how many GPIOs?\n");
	134	return -EINVAL;
	135	}
	136
	137	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
	138	ngpio = DAVINCI_N_GPIO;
	139
	140	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	141	chips[i].chip.label = "DaVinci";
	142
	143	chips[i].chip.direction_input = davinci_direction_in;
	144	chips[i].chip.get = davinci_gpio_get;
	145	chips[i].chip.direction_output = davinci_direction_out;
	146	chips[i].chip.set = davinci_gpio_set;
	147
	148	chips[i].chip.base = base;
474dad54	149	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	150	if (chips[i].chip.ngpio > 32)
	151	chips[i].chip.ngpio = 32;
	152
	153	chips[i].regs = gpio2controller(base);
	154
	155	gpiochip_add(&chips[i].chip);
	156	}
3d9edf09	157
dc756026	158	davinci_gpio_irq_setup();
3d9edf09 VB	159	return 0;
3d9edf09 VB	160	}
dce1115b	161	pure_initcall(davinci_gpio_setup);
3d9edf09	162
dce1115b	163	/--------------------------------------------------------------------------/
3d9edf09 VB	164	/*
	165	* We expect irqs will normally be set up as input pins, but they can also be
	166	* used as output pins ... which is convenient for testing.
	167	*
474dad54	168	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	169	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	170	*
474dad54	171	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	172	* serve as EDMA event triggers.
	173	*/
	174
	175	static void gpio_irq_disable(unsigned irq)
	176	{
21ce873d	177	struct gpio_controller __iomem *g = irq2controller(irq);
7a36071e	178	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	179
	180	__raw_writel(mask, &g->clr_falling);
	181	__raw_writel(mask, &g->clr_rising);
	182	}
	183
	184	static void gpio_irq_enable(unsigned irq)
	185	{
21ce873d	186	struct gpio_controller __iomem *g = irq2controller(irq);
7a36071e	187	u32 mask = (u32) get_irq_data(irq);
df4aab46	188	unsigned status = irq_desc[irq].status;
3d9edf09	189
df4aab46 DB	190	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	191	if (!status)
	192	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	193
	194	if (status & IRQ_TYPE_EDGE_FALLING)
3d9edf09	195	__raw_writel(mask, &g->set_falling);
df4aab46	196	if (status & IRQ_TYPE_EDGE_RISING)
3d9edf09 VB	197	__raw_writel(mask, &g->set_rising);
	198	}
	199
	200	static int gpio_irq_type(unsigned irq, unsigned trigger)
	201	{
21ce873d	202	struct gpio_controller __iomem *g = irq2controller(irq);
7a36071e	203	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	204
	205	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	206	return -EINVAL;
	207
	208	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	209	irq_desc[irq].status \|= trigger;
	210
df4aab46 DB	211	/* don't enable the IRQ if it's currently disabled */
	212	if (irq_desc[irq].depth == 0) {
	213	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	214	? &g->set_falling : &g->clr_falling);
	215	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	216	? &g->set_rising : &g->clr_rising);
	217	}
3d9edf09 VB	218	return 0;
	219	}
	220
	221	static struct irq_chip gpio_irqchip = {
	222	.name = "GPIO",
	223	.enable = gpio_irq_enable,
	224	.disable = gpio_irq_disable,
	225	.set_type = gpio_irq_type,
	226	};
	227
	228	static void
	229	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	230	{
21ce873d	231	struct gpio_controller __iomem *g = irq2controller(irq);
3d9edf09 VB	232	u32 mask = 0xffff;
	233
	234	/* we only care about one bank */
	235	if (irq & 1)
	236	mask <<= 16;
	237
	238	/* temporarily mask (level sensitive) parent IRQ */
dc756026	239	desc->chip->mask(irq);
3d9edf09 VB	240	desc->chip->ack(irq);
	241	while (1) {
	242	u32 status;
3d9edf09 VB	243	int n;
	244	int res;
	245
	246	/* ack any irqs */
	247	status = __raw_readl(&g->intstat) & mask;
	248	if (!status)
	249	break;
	250	__raw_writel(status, &g->intstat);
	251	if (irq & 1)
	252	status >>= 16;
	253
	254	/* now demux them to the right lowlevel handler */
	255	n = (int)get_irq_data(irq);
3d9edf09 VB	256	while (status) {
	257	res = ffs(status);
	258	n += res;
d8aa0251	259	generic_handle_irq(n - 1);
3d9edf09 VB	260	status >>= res;
	261	}
	262	}
	263	desc->chip->unmask(irq);
	264	/* now it may re-trigger */
	265	}
	266
7a36071e DB	267	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
7a36071e DB	268	{
ba4a984e	269	struct davinci_gpio *d = chip2controller(chip);
7a36071e DB	270
	271	if (d->irq_base >= 0)
	272	return d->irq_base + offset;
	273	else
	274	return -ENODEV;
	275	}
	276
	277	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	278	{
	279	struct davinci_soc_info *soc_info = &davinci_soc_info;
	280
	281	/* NOTE: we assume for now that only irqs in the first gpio_chip
	282	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	283	*/
	284	if (offset < soc_info->gpio_unbanked)
	285	return soc_info->gpio_irq + offset;
	286	else
	287	return -ENODEV;
	288	}
	289
	290	static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
	291	{
21ce873d	292	struct gpio_controller __iomem *g = irq2controller(irq);
7a36071e DB	293	u32 mask = (u32) get_irq_data(irq);
	294
	295	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	296	return -EINVAL;
	297
	298	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	299	? &g->set_falling : &g->clr_falling);
	300	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	301	? &g->set_rising : &g->clr_rising);
	302
	303	return 0;
	304	}
	305
3d9edf09	306	/*
474dad54 DB	307	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	308	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	309	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	310	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	311	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	312	*/
	313
	314	static int __init davinci_gpio_irq_setup(void)
	315	{
	316	unsigned gpio, irq, bank;
	317	struct clk *clk;
474dad54	318	u32 binten = 0;
a994955c MG	319	unsigned ngpio, bank_irq;
a994955c MG	320	struct davinci_soc_info *soc_info = &davinci_soc_info;
28552c2e	321	struct gpio_controller __iomem *g;
a994955c MG	322
a994955c MG	323	ngpio = soc_info->gpio_num;
474dad54	324
a994955c MG	325	bank_irq = soc_info->gpio_irq;
a994955c MG	326	if (bank_irq == 0) {
474dad54 DB	327	printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
	328	return -EINVAL;
	329	}
3d9edf09 VB	330
	331	clk = clk_get(NULL, "gpio");
	332	if (IS_ERR(clk)) {
	333	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	334	PTR_ERR(clk));
474dad54	335	return PTR_ERR(clk);
3d9edf09	336	}
3d9edf09 VB	337	clk_enable(clk);
3d9edf09 VB	338
7a36071e DB	339	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	340	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	341	* IRQs, while the others use banked IRQs, would need some setup
	342	* tweaks to recognize hardware which can do that.
	343	*/
	344	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	345	chips[bank].chip.to_irq = gpio_to_irq_banked;
	346	chips[bank].irq_base = soc_info->gpio_unbanked
	347	? -EINVAL
	348	: (soc_info->intc_irq_num + gpio);
	349	}
	350
	351	/*
	352	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	353	* controller only handling trigger modes. We currently assume no
	354	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	355	*/
	356	if (soc_info->gpio_unbanked) {
	357	static struct irq_chip gpio_irqchip_unbanked;
	358
	359	/* pass "bank 0" GPIO IRQs to AINTC */
	360	chips[0].chip.to_irq = gpio_to_irq_unbanked;
	361	binten = BIT(0);
	362
	363	/* AINTC handles mask/unmask; GPIO handles triggering */
	364	irq = bank_irq;
	365	gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
	366	gpio_irqchip_unbanked.name = "GPIO-AINTC";
	367	gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
	368
	369	/* default trigger: both edges */
	370	g = gpio2controller(0);
	371	__raw_writel(~0, &g->set_falling);
	372	__raw_writel(~0, &g->set_rising);
	373
	374	/* set the direct IRQs up to use that irqchip */
	375	for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
	376	set_irq_chip(irq, &gpio_irqchip_unbanked);
	377	set_irq_data(irq, (void *) __gpio_mask(gpio));
21ce873d	378	set_irq_chip_data(irq, (__force void *) g);
7a36071e DB	379	irq_desc[irq].status \|= IRQ_TYPE_EDGE_BOTH;
	380	}
	381
	382	goto done;
	383	}
	384
	385	/*
	386	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	387	* then chain through our own handler.
	388	*/
474dad54 DB	389	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
	390	gpio < ngpio;
	391	bank++, bank_irq++) {
3d9edf09 VB	392	unsigned i;
3d9edf09 VB	393
7a36071e DB	394	/* disabled by default, enabled only as needed */
7a36071e DB	395	g = gpio2controller(gpio);
3d9edf09 VB	396	__raw_writel(~0, &g->clr_falling);
	397	__raw_writel(~0, &g->clr_rising);
	398
	399	/* set up all irqs in this bank */
474dad54	400	set_irq_chained_handler(bank_irq, gpio_irq_handler);
21ce873d KH	401	set_irq_chip_data(bank_irq, (__force void *) g);
21ce873d KH	402	set_irq_data(bank_irq, (void *) irq);
3d9edf09	403
474dad54	404	for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
3d9edf09	405	set_irq_chip(irq, &gpio_irqchip);
21ce873d	406	set_irq_chip_data(irq, (__force void *) g);
7a36071e	407	set_irq_data(irq, (void *) __gpio_mask(gpio));
3d9edf09 VB	408	set_irq_handler(irq, handle_simple_irq);
	409	set_irq_flags(irq, IRQF_VALID);
	410	}
474dad54 DB	411
474dad54 DB	412	binten \|= BIT(bank);
3d9edf09 VB	413	}
3d9edf09 VB	414
7a36071e	415	done:
3d9edf09 VB	416	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	417	* bits be set/cleared dynamically.
	418	*/
a994955c	419	__raw_writel(binten, soc_info->gpio_base + 0x08);
3d9edf09 VB	420
	421	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
	422
	423	return 0;
	424	}