[net-next-2.6.git] / arch / arm / mach-davinci / gpio.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/bitops.h>

#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/gpio.h>

#include <asm/mach/irq.h>


static DEFINE_SPINLOCK(gpio_lock);

struct davinci_gpio {
	struct gpio_chip	chip;
	struct gpio_controller	*__iomem regs;
	int			irq_base;
};

static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];

/* create a non-inlined version */
static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
{
	return __gpio_to_controller(gpio);
}

static int __init davinci_gpio_irq_setup(void);

/*--------------------------------------------------------------------------*/

/*
 * board setup code *MUST* set PINMUX0 and PINMUX1 as
 * needed, and enable the GPIO clock.
 */

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	struct gpio_controller *__iomem g = d->regs;
	u32 temp;

	spin_lock(&gpio_lock);
	temp = __raw_readl(&g->dir);
	temp |= (1 << offset);
	__raw_writel(temp, &g->dir);
	spin_unlock(&gpio_lock);

	return 0;
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	struct gpio_controller *__iomem g = d->regs;

	return (1 << offset) & __raw_readl(&g->in_data);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	struct gpio_controller *__iomem g = d->regs;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock(&gpio_lock);
	temp = __raw_readl(&g->dir);
	temp &= ~mask;
	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	__raw_writel(temp, &g->dir);
	spin_unlock(&gpio_lock);
	return 0;
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	struct gpio_controller *__iomem g = d->regs;

	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}

static int __init davinci_gpio_setup(void)
{
	int i, base;
	unsigned ngpio;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = soc_info->gpio_num;
	if (ngpio == 0) {
		pr_err("GPIO setup:  how many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
		ngpio = DAVINCI_N_GPIO;

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

		chips[i].regs = gpio2controller(base);

		gpiochip_add(&chips[i].chip);
	}

	davinci_gpio_irq_setup();
	return 0;
}
pure_initcall(davinci_gpio_setup);

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(unsigned irq)
{
	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	u32 mask = (u32) get_irq_data(irq);

	__raw_writel(mask, &g->clr_falling);
	__raw_writel(mask, &g->clr_rising);
}

static void gpio_irq_enable(unsigned irq)
{
	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	u32 mask = (u32) get_irq_data(irq);
	unsigned status = irq_desc[irq].status;

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		__raw_writel(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		__raw_writel(mask, &g->set_rising);
}

static int gpio_irq_type(unsigned irq, unsigned trigger)
{
	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	irq_desc[irq].status |= trigger;

	/* don't enable the IRQ if it's currently disabled */
	if (irq_desc[irq].depth == 0) {
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
			     ? &g->set_falling : &g->clr_falling);
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
			     ? &g->set_rising : &g->clr_rising);
	}
	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.enable		= gpio_irq_enable,
	.disable	= gpio_irq_disable,
	.set_type	= gpio_irq_type,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	u32 mask = 0xffff;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->mask(irq);
	desc->chip->ack(irq);
	while (1) {
		u32		status;
		int		n;
		int		res;

		/* ack any irqs */
		status = __raw_readl(&g->intstat) & mask;
		if (!status)
			break;
		__raw_writel(status, &g->intstat);
		if (irq & 1)
			status >>= 16;

		/* now demux them to the right lowlevel handler */
		n = (int)get_irq_data(irq);
		while (status) {
			res = ffs(status);
			n += res;
			generic_handle_irq(n - 1);
			status >>= res;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);

	if (d->irq_base >= 0)
		return d->irq_base + offset;
	else
		return -ENODEV;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/* NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < soc_info->gpio_unbanked)
		return soc_info->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int __init davinci_gpio_irq_setup(void)
{
	unsigned	gpio, irq, bank;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct gpio_controller	*__iomem g;

	ngpio = soc_info->gpio_num;

	bank_irq = soc_info->gpio_irq;
	if (bank_irq == 0) {
		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
		return -EINVAL;
	}

	clk = clk_get(NULL, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_base = soc_info->gpio_unbanked
			? -EINVAL
			: (soc_info->intc_irq_num + gpio);
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (soc_info->gpio_unbanked) {
		static struct irq_chip gpio_irqchip_unbanked;

		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
		gpio_irqchip_unbanked.name = "GPIO-AINTC";
		gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2controller(0);
		__raw_writel(~0, &g->set_falling);
		__raw_writel(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
			set_irq_chip(irq, &gpio_irqchip_unbanked);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_chip_data(irq, g);
			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
			gpio < ngpio;
			bank++, bank_irq++) {
		unsigned		i;

		/* disabled by default, enabled only as needed */
		g = gpio2controller(gpio);
		__raw_writel(~0, &g->clr_falling);
		__raw_writel(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		set_irq_chained_handler(bank_irq, gpio_irq_handler);
		set_irq_chip_data(bank_irq, g);
		set_irq_data(bank_irq, (void *)irq);

		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
			set_irq_chip(irq, &gpio_irqchip);
			set_irq_chip_data(irq, g);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID);
		}

		binten |= BIT(bank);
	}

done:
	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	__raw_writel(binten, soc_info->gpio_base + 0x08);

	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

	return 0;
}
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/errno.h>
	14	#include <linux/kernel.h>
	15	#include <linux/list.h>
	16	#include <linux/module.h>
	17	#include <linux/clk.h>
	18	#include <linux/err.h>
	19	#include <linux/io.h>
	20	#include <linux/irq.h>
	21	#include <linux/bitops.h>
	22
474dad54	23	#include <mach/cputype.h>
a09e64fb RK	24	#include <mach/irqs.h>
a09e64fb RK	25	#include <mach/hardware.h>
a994955c	26	#include <mach/common.h>
a09e64fb	27	#include <mach/gpio.h>
3d9edf09 VB	28
	29	#include <asm/mach/irq.h>
	30
3d9edf09	31
dce1115b	32	static DEFINE_SPINLOCK(gpio_lock);
3d9edf09	33
dce1115b DB	34	struct davinci_gpio {
	35	struct gpio_chip chip;
	36	struct gpio_controller *__iomem regs;
7a36071e	37	int irq_base;
dce1115b	38	};
3d9edf09	39
dce1115b	40	static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
3d9edf09	41
3d9edf09	42	/* create a non-inlined version */
474dad54	43	static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
3d9edf09 VB	44	{
	45	return __gpio_to_controller(gpio);
	46	}
	47
dc756026	48	static int __init davinci_gpio_irq_setup(void);
dce1115b DB	49
	50	/--------------------------------------------------------------------------/
	51
3d9edf09	52	/*
dce1115b DB	53	* board setup code MUST set PINMUX0 and PINMUX1 as
dce1115b DB	54	* needed, and enable the GPIO clock.
3d9edf09	55	*/
dce1115b DB	56
dce1115b DB	57	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
3d9edf09	58	{
dce1115b DB	59	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	60	struct gpio_controller *__iomem g = d->regs;
	61	u32 temp;
3d9edf09	62
dce1115b DB	63	spin_lock(&gpio_lock);
	64	temp = __raw_readl(&g->dir);
	65	temp \|= (1 << offset);
	66	__raw_writel(temp, &g->dir);
	67	spin_unlock(&gpio_lock);
3d9edf09	68
dce1115b DB	69	return 0;
dce1115b DB	70	}
3d9edf09 VB	71
	72	/*
	73	* Read the pin's value (works even if it's set up as output);
	74	* returns zero/nonzero.
	75	*
	76	* Note that changes are synched to the GPIO clock, so reading values back
	77	* right after you've set them may give old values.
	78	*/
dce1115b	79	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	80	{
dce1115b DB	81	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
dce1115b DB	82	struct gpio_controller *__iomem g = d->regs;
3d9edf09	83
dce1115b	84	return (1 << offset) & __raw_readl(&g->in_data);
3d9edf09	85	}
3d9edf09	86
dce1115b DB	87	static int
dce1115b DB	88	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	89	{
dce1115b DB	90	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
dce1115b DB	91	struct gpio_controller *__iomem g = d->regs;
3d9edf09	92	u32 temp;
dce1115b	93	u32 mask = 1 << offset;
3d9edf09 VB	94
3d9edf09 VB	95	spin_lock(&gpio_lock);
3d9edf09	96	temp = __raw_readl(&g->dir);
dce1115b DB	97	temp &= ~mask;
dce1115b DB	98	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
3d9edf09 VB	99	__raw_writel(temp, &g->dir);
	100	spin_unlock(&gpio_lock);
	101	return 0;
	102	}
3d9edf09	103
dce1115b DB	104	/*
	105	* Assuming the pin is muxed as a gpio output, set its output value.
	106	*/
	107	static void
	108	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	109	{
dce1115b DB	110	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
dce1115b DB	111	struct gpio_controller *__iomem g = d->regs;
3d9edf09	112
dce1115b DB	113	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
	114	}
	115
	116	static int __init davinci_gpio_setup(void)
	117	{
	118	int i, base;
a994955c MG	119	unsigned ngpio;
a994955c MG	120	struct davinci_soc_info *soc_info = &davinci_soc_info;
dce1115b	121
a994955c MG	122	/*
a994955c MG	123	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	124	* and "ngpio" is one more than the largest zero-based
	125	* bit index that's valid.
	126	*/
a994955c MG	127	ngpio = soc_info->gpio_num;
a994955c MG	128	if (ngpio == 0) {
474dad54 DB	129	pr_err("GPIO setup: how many GPIOs?\n");
	130	return -EINVAL;
	131	}
	132
	133	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
	134	ngpio = DAVINCI_N_GPIO;
	135
	136	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	137	chips[i].chip.label = "DaVinci";
	138
	139	chips[i].chip.direction_input = davinci_direction_in;
	140	chips[i].chip.get = davinci_gpio_get;
	141	chips[i].chip.direction_output = davinci_direction_out;
	142	chips[i].chip.set = davinci_gpio_set;
	143
	144	chips[i].chip.base = base;
474dad54	145	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	146	if (chips[i].chip.ngpio > 32)
	147	chips[i].chip.ngpio = 32;
	148
	149	chips[i].regs = gpio2controller(base);
	150
	151	gpiochip_add(&chips[i].chip);
	152	}
3d9edf09	153
dc756026	154	davinci_gpio_irq_setup();
3d9edf09 VB	155	return 0;
3d9edf09 VB	156	}
dce1115b	157	pure_initcall(davinci_gpio_setup);
3d9edf09	158
dce1115b	159	/--------------------------------------------------------------------------/
3d9edf09 VB	160	/*
	161	* We expect irqs will normally be set up as input pins, but they can also be
	162	* used as output pins ... which is convenient for testing.
	163	*
474dad54	164	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	165	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	166	*
474dad54	167	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	168	* serve as EDMA event triggers.
	169	*/
	170
	171	static void gpio_irq_disable(unsigned irq)
	172	{
	173	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
7a36071e	174	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	175
	176	__raw_writel(mask, &g->clr_falling);
	177	__raw_writel(mask, &g->clr_rising);
	178	}
	179
	180	static void gpio_irq_enable(unsigned irq)
	181	{
	182	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
7a36071e	183	u32 mask = (u32) get_irq_data(irq);
df4aab46	184	unsigned status = irq_desc[irq].status;
3d9edf09	185
df4aab46 DB	186	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	187	if (!status)
	188	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	189
	190	if (status & IRQ_TYPE_EDGE_FALLING)
3d9edf09	191	__raw_writel(mask, &g->set_falling);
df4aab46	192	if (status & IRQ_TYPE_EDGE_RISING)
3d9edf09 VB	193	__raw_writel(mask, &g->set_rising);
	194	}
	195
	196	static int gpio_irq_type(unsigned irq, unsigned trigger)
	197	{
	198	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
7a36071e	199	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	200
	201	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	202	return -EINVAL;
	203
	204	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	205	irq_desc[irq].status \|= trigger;
	206
df4aab46 DB	207	/* don't enable the IRQ if it's currently disabled */
	208	if (irq_desc[irq].depth == 0) {
	209	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	210	? &g->set_falling : &g->clr_falling);
	211	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	212	? &g->set_rising : &g->clr_rising);
	213	}
3d9edf09 VB	214	return 0;
	215	}
	216
	217	static struct irq_chip gpio_irqchip = {
	218	.name = "GPIO",
	219	.enable = gpio_irq_enable,
	220	.disable = gpio_irq_disable,
	221	.set_type = gpio_irq_type,
	222	};
	223
	224	static void
	225	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	226	{
	227	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	228	u32 mask = 0xffff;
	229
	230	/* we only care about one bank */
	231	if (irq & 1)
	232	mask <<= 16;
	233
	234	/* temporarily mask (level sensitive) parent IRQ */
dc756026	235	desc->chip->mask(irq);
3d9edf09 VB	236	desc->chip->ack(irq);
	237	while (1) {
	238	u32 status;
3d9edf09 VB	239	int n;
	240	int res;
	241
	242	/* ack any irqs */
	243	status = __raw_readl(&g->intstat) & mask;
	244	if (!status)
	245	break;
	246	__raw_writel(status, &g->intstat);
	247	if (irq & 1)
	248	status >>= 16;
	249
	250	/* now demux them to the right lowlevel handler */
	251	n = (int)get_irq_data(irq);
3d9edf09 VB	252	while (status) {
	253	res = ffs(status);
	254	n += res;
d8aa0251	255	generic_handle_irq(n - 1);
3d9edf09 VB	256	status >>= res;
	257	}
	258	}
	259	desc->chip->unmask(irq);
	260	/* now it may re-trigger */
	261	}
	262
7a36071e DB	263	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
	264	{
	265	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
	266
	267	if (d->irq_base >= 0)
	268	return d->irq_base + offset;
	269	else
	270	return -ENODEV;
	271	}
	272
	273	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	274	{
	275	struct davinci_soc_info *soc_info = &davinci_soc_info;
	276
	277	/* NOTE: we assume for now that only irqs in the first gpio_chip
	278	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	279	*/
	280	if (offset < soc_info->gpio_unbanked)
	281	return soc_info->gpio_irq + offset;
	282	else
	283	return -ENODEV;
	284	}
	285
	286	static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
	287	{
	288	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
	289	u32 mask = (u32) get_irq_data(irq);
	290
	291	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	292	return -EINVAL;
	293
	294	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	295	? &g->set_falling : &g->clr_falling);
	296	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	297	? &g->set_rising : &g->clr_rising);
	298
	299	return 0;
	300	}
	301
3d9edf09	302	/*
474dad54 DB	303	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	304	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	305	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	306	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	307	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	308	*/
	309
	310	static int __init davinci_gpio_irq_setup(void)
	311	{
	312	unsigned gpio, irq, bank;
	313	struct clk *clk;
474dad54	314	u32 binten = 0;
a994955c MG	315	unsigned ngpio, bank_irq;
a994955c MG	316	struct davinci_soc_info *soc_info = &davinci_soc_info;
7a36071e	317	struct gpio_controller *__iomem g;
a994955c MG	318
a994955c MG	319	ngpio = soc_info->gpio_num;
474dad54	320
a994955c MG	321	bank_irq = soc_info->gpio_irq;
a994955c MG	322	if (bank_irq == 0) {
474dad54 DB	323	printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
	324	return -EINVAL;
	325	}
3d9edf09 VB	326
	327	clk = clk_get(NULL, "gpio");
	328	if (IS_ERR(clk)) {
	329	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	330	PTR_ERR(clk));
474dad54	331	return PTR_ERR(clk);
3d9edf09	332	}
3d9edf09 VB	333	clk_enable(clk);
3d9edf09 VB	334
7a36071e DB	335	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	336	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	337	* IRQs, while the others use banked IRQs, would need some setup
	338	* tweaks to recognize hardware which can do that.
	339	*/
	340	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	341	chips[bank].chip.to_irq = gpio_to_irq_banked;
	342	chips[bank].irq_base = soc_info->gpio_unbanked
	343	? -EINVAL
	344	: (soc_info->intc_irq_num + gpio);
	345	}
	346
	347	/*
	348	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	349	* controller only handling trigger modes. We currently assume no
	350	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	351	*/
	352	if (soc_info->gpio_unbanked) {
	353	static struct irq_chip gpio_irqchip_unbanked;
	354
	355	/* pass "bank 0" GPIO IRQs to AINTC */
	356	chips[0].chip.to_irq = gpio_to_irq_unbanked;
	357	binten = BIT(0);
	358
	359	/* AINTC handles mask/unmask; GPIO handles triggering */
	360	irq = bank_irq;
	361	gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
	362	gpio_irqchip_unbanked.name = "GPIO-AINTC";
	363	gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
	364
	365	/* default trigger: both edges */
	366	g = gpio2controller(0);
	367	__raw_writel(~0, &g->set_falling);
	368	__raw_writel(~0, &g->set_rising);
	369
	370	/* set the direct IRQs up to use that irqchip */
	371	for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
	372	set_irq_chip(irq, &gpio_irqchip_unbanked);
	373	set_irq_data(irq, (void *) __gpio_mask(gpio));
	374	set_irq_chip_data(irq, g);
	375	irq_desc[irq].status \|= IRQ_TYPE_EDGE_BOTH;
	376	}
	377
	378	goto done;
	379	}
	380
	381	/*
	382	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	383	* then chain through our own handler.
	384	*/
474dad54 DB	385	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
	386	gpio < ngpio;
	387	bank++, bank_irq++) {
3d9edf09 VB	388	unsigned i;
3d9edf09 VB	389
7a36071e DB	390	/* disabled by default, enabled only as needed */
7a36071e DB	391	g = gpio2controller(gpio);
3d9edf09 VB	392	__raw_writel(~0, &g->clr_falling);
	393	__raw_writel(~0, &g->clr_rising);
	394
	395	/* set up all irqs in this bank */
474dad54 DB	396	set_irq_chained_handler(bank_irq, gpio_irq_handler);
	397	set_irq_chip_data(bank_irq, g);
	398	set_irq_data(bank_irq, (void *)irq);
3d9edf09	399
474dad54	400	for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
3d9edf09 VB	401	set_irq_chip(irq, &gpio_irqchip);
3d9edf09 VB	402	set_irq_chip_data(irq, g);
7a36071e	403	set_irq_data(irq, (void *) __gpio_mask(gpio));
3d9edf09 VB	404	set_irq_handler(irq, handle_simple_irq);
	405	set_irq_flags(irq, IRQF_VALID);
	406	}
474dad54 DB	407
474dad54 DB	408	binten \|= BIT(bank);
3d9edf09 VB	409	}
3d9edf09 VB	410
7a36071e	411	done:
3d9edf09 VB	412	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	413	* bits be set/cleared dynamically.
	414	*/
a994955c	415	__raw_writel(binten, soc_info->gpio_base + 0x08);
3d9edf09 VB	416
	417	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
	418
	419	return 0;
	420	}