[net-next-2.6.git] / arch / arm / mach-davinci / dm646x.c

/*
 * TI DaVinci DM644x chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

#include <mach/dm646x.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>

#include "clock.h"
#include "mux.h"

/*
 * Device specific clocks
 */
#define DM646X_REF_FREQ		27000000
#define DM646X_AUX_FREQ		24000000

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	.rate = DM646X_REF_FREQ,
};

static struct clk aux_clkin = {
	.name = "aux_clkin",
	.rate = DM646X_AUX_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.pll_data = &pll1_data,
	.flags = CLK_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclk5 = {
	.name = "pll1_sysclk5",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV5,
};

static struct clk pll1_sysclk6 = {
	.name = "pll1_sysclk6",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV6,
};

static struct clk pll1_sysclk8 = {
	.name = "pll1_sysclk8",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV8,
};

static struct clk pll1_sysclk9 = {
	.name = "pll1_sysclk9",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV9,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll2_clk = {
	.name = "pll2_clk",
	.parent = &ref_clk,
	.pll_data = &pll2_data,
	.flags = CLK_PLL,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk dsp_clk = {
	.name = "dsp",
	.parent = &pll1_sysclk1,
	.lpsc = DM646X_LPSC_C64X_CPU,
	.flags = PSC_DSP,
	.usecount = 1,			/* REVISIT how to disable? */
};

static struct clk arm_clk = {
	.name = "arm",
	.parent = &pll1_sysclk2,
	.lpsc = DM646X_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "I2CCLK",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_I2C,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_AEMIF,
	.flags = ALWAYS_ENABLED,
};

static struct clk emac_clk = {
	.name = "emac",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_EMAC,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM0,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM1,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_sysclk3,
	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
};

static struct clk vpif0_clk = {
	.name = "vpif0",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSMSTR,
	.flags = ALWAYS_ENABLED,
};

static struct clk vpif1_clk = {
	.name = "vpif1",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSSLV,
	.flags = ALWAYS_ENABLED,
};

struct davinci_clk dm646x_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "aux", &aux_clkin),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "dsp", &dsp_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK("davinci_emac.1", NULL, &emac_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "vpif0", &vpif0_clk),
	CLK(NULL, "vpif1", &vpif1_clk),
	CLK(NULL, NULL, NULL),
};

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm646x_pins[] = {
MUX_CFG(DM646X, ATAEN,		0,   0,     1,	  1,	 true)

MUX_CFG(DM646X, AUDCK1,		0,   29,    1,	  0,	 false)

MUX_CFG(DM646X, AUDCK0,		0,   28,    1,	  0,	 false)

MUX_CFG(DM646X, CRGMUX,			0,   24,    7,    5,	 true)

MUX_CFG(DM646X, STSOMUX_DISABLE,	0,   22,    3,    0,	 true)

MUX_CFG(DM646X, STSIMUX_DISABLE,	0,   20,    3,    0,	 true)

MUX_CFG(DM646X, PTSOMUX_DISABLE,	0,   18,    3,    0,	 true)

MUX_CFG(DM646X, PTSIMUX_DISABLE,	0,   16,    3,    0,	 true)

MUX_CFG(DM646X, STSOMUX,		0,   22,    3,    2,	 true)

MUX_CFG(DM646X, STSIMUX,		0,   20,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_PARALLEL,	0,   18,    3,    2,	 true)

MUX_CFG(DM646X, PTSIMUX_PARALLEL,	0,   16,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_SERIAL,		0,   18,    3,    3,	 true)

MUX_CFG(DM646X, PTSIMUX_SERIAL,		0,   16,    3,    3,	 true)
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm646x_no_event[] = {
	 0,  1,  2,  3, 13,
	14, 15, 24, 25, 26,
	27, 30, 31, 54, 55,
	56,
	-1
};

static struct edma_soc_info dm646x_edma_info = {
	.n_channel	= 64,
	.n_region	= 6,	/* 0-1, 4-7 */
	.n_slot		= 512,
	.n_tc		= 4,
	.noevent	= dma_chan_dm646x_no_event,
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc2",
		.start	= 0x01c10800,
		.end	= 0x01c10800 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc3",
		.start	= 0x01c10c00,
		.end	= 0x01c10c00 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using TC*_ERR */
};

static struct platform_device dm646x_edma_device = {
	.name			= "edma",
	.id			= -1,
	.dev.platform_data	= &dm646x_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

void __init dm646x_init(void)
{
	davinci_clk_init(dm646x_clks);
	davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
}

static int __init dm646x_init_devices(void)
{
	if (!cpu_is_davinci_dm646x())
		return 0;

	platform_device_register(&dm646x_edma_device);
	return 0;
}
postcore_initcall(dm646x_init_devices);
Commit	Line	Data
e38d92fd KH	1	/*
	2	* TI DaVinci DM644x chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
	14	#include <linux/platform_device.h>
	15
	16	#include <mach/dm646x.h>
	17	#include <mach/clock.h>
	18	#include <mach/cputype.h>
	19	#include <mach/edma.h>
	20	#include <mach/irqs.h>
	21	#include <mach/psc.h>
	22	#include <mach/mux.h>
	23
	24	#include "clock.h"
	25	#include "mux.h"
	26
	27	/*
	28	* Device specific clocks
	29	*/
	30	#define DM646X_REF_FREQ 27000000
	31	#define DM646X_AUX_FREQ 24000000
	32
	33	static struct pll_data pll1_data = {
	34	.num = 1,
	35	.phys_base = DAVINCI_PLL1_BASE,
	36	};
	37
	38	static struct pll_data pll2_data = {
	39	.num = 2,
	40	.phys_base = DAVINCI_PLL2_BASE,
	41	};
	42
	43	static struct clk ref_clk = {
	44	.name = "ref_clk",
	45	.rate = DM646X_REF_FREQ,
	46	};
	47
	48	static struct clk aux_clkin = {
	49	.name = "aux_clkin",
	50	.rate = DM646X_AUX_FREQ,
	51	};
	52
	53	static struct clk pll1_clk = {
	54	.name = "pll1",
	55	.parent = &ref_clk,
	56	.pll_data = &pll1_data,
	57	.flags = CLK_PLL,
	58	};
	59
	60	static struct clk pll1_sysclk1 = {
	61	.name = "pll1_sysclk1",
	62	.parent = &pll1_clk,
	63	.flags = CLK_PLL,
	64	.div_reg = PLLDIV1,
65	};
66
67	static struct clk pll1_sysclk2 = {
68	.name = "pll1_sysclk2",
69	.parent = &pll1_clk,
70	.flags = CLK_PLL,
71	.div_reg = PLLDIV2,
72	};
73
74	static struct clk pll1_sysclk3 = {
75	.name = "pll1_sysclk3",
76	.parent = &pll1_clk,
77	.flags = CLK_PLL,
78	.div_reg = PLLDIV3,
79	};
80
81	static struct clk pll1_sysclk4 = {
82	.name = "pll1_sysclk4",
83	.parent = &pll1_clk,
84	.flags = CLK_PLL,
85	.div_reg = PLLDIV4,
86	};
87
88	static struct clk pll1_sysclk5 = {
89	.name = "pll1_sysclk5",
90	.parent = &pll1_clk,
91	.flags = CLK_PLL,
92	.div_reg = PLLDIV5,
93	};
94
95	static struct clk pll1_sysclk6 = {
96	.name = "pll1_sysclk6",
97	.parent = &pll1_clk,
98	.flags = CLK_PLL,
99	.div_reg = PLLDIV6,
100	};
101
102	static struct clk pll1_sysclk8 = {
103	.name = "pll1_sysclk8",
104	.parent = &pll1_clk,
105	.flags = CLK_PLL,
106	.div_reg = PLLDIV8,
107	};
108
109	static struct clk pll1_sysclk9 = {
110	.name = "pll1_sysclk9",
111	.parent = &pll1_clk,
112	.flags = CLK_PLL,
113	.div_reg = PLLDIV9,
114	};
115
116	static struct clk pll1_sysclkbp = {
117	.name = "pll1_sysclkbp",
118	.parent = &pll1_clk,
119	.flags = CLK_PLL \| PRE_PLL,
120	.div_reg = BPDIV,
121	};
122
123	static struct clk pll1_aux_clk = {
124	.name = "pll1_aux_clk",
125	.parent = &pll1_clk,
126	.flags = CLK_PLL \| PRE_PLL,
127	};
128
129	static struct clk pll2_clk = {
130	.name = "pll2_clk",
131	.parent = &ref_clk,
132	.pll_data = &pll2_data,
133	.flags = CLK_PLL,
134	};
135
136	static struct clk pll2_sysclk1 = {
137	.name = "pll2_sysclk1",
138	.parent = &pll2_clk,
139	.flags = CLK_PLL,
140	.div_reg = PLLDIV1,
141	};
142
143	static struct clk dsp_clk = {
144	.name = "dsp",
145	.parent = &pll1_sysclk1,
146	.lpsc = DM646X_LPSC_C64X_CPU,
147	.flags = PSC_DSP,
148	.usecount = 1, /* REVISIT how to disable? */
149	};
150
151	static struct clk arm_clk = {
152	.name = "arm",
153	.parent = &pll1_sysclk2,
154	.lpsc = DM646X_LPSC_ARM,
155	.flags = ALWAYS_ENABLED,
156	};
157
158	static struct clk uart0_clk = {
159	.name = "uart0",
160	.parent = &aux_clkin,
161	.lpsc = DM646X_LPSC_UART0,
162	};
163
164	static struct clk uart1_clk = {
165	.name = "uart1",
166	.parent = &aux_clkin,
167	.lpsc = DM646X_LPSC_UART1,
168	};
169
170	static struct clk uart2_clk = {
171	.name = "uart2",
172	.parent = &aux_clkin,
173	.lpsc = DM646X_LPSC_UART2,
174	};
175
176	static struct clk i2c_clk = {
177	.name = "I2CCLK",
178	.parent = &pll1_sysclk3,
179	.lpsc = DM646X_LPSC_I2C,
180	};
181
182	static struct clk gpio_clk = {
183	.name = "gpio",
184	.parent = &pll1_sysclk3,
185	.lpsc = DM646X_LPSC_GPIO,
186	};
187
188	static struct clk aemif_clk = {
189	.name = "aemif",
190	.parent = &pll1_sysclk3,
191	.lpsc = DM646X_LPSC_AEMIF,
192	.flags = ALWAYS_ENABLED,
193	};
194
195	static struct clk emac_clk = {
196	.name = "emac",
197	.parent = &pll1_sysclk3,
198	.lpsc = DM646X_LPSC_EMAC,
199	};
200
201	static struct clk pwm0_clk = {
202	.name = "pwm0",
203	.parent = &pll1_sysclk3,
204	.lpsc = DM646X_LPSC_PWM0,
205	.usecount = 1, /* REVIST: disabling hangs system */
206	};
207
208	static struct clk pwm1_clk = {
209	.name = "pwm1",
210	.parent = &pll1_sysclk3,
211	.lpsc = DM646X_LPSC_PWM1,
212	.usecount = 1, /* REVIST: disabling hangs system */
213	};
214
215	static struct clk timer0_clk = {
216	.name = "timer0",
217	.parent = &pll1_sysclk3,
218	.lpsc = DM646X_LPSC_TIMER0,
219	};
220
221	static struct clk timer1_clk = {
222	.name = "timer1",
223	.parent = &pll1_sysclk3,
224	.lpsc = DM646X_LPSC_TIMER1,
225	};
226
227	static struct clk timer2_clk = {
228	.name = "timer2",
229	.parent = &pll1_sysclk3,
230	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
231	};
232
233	static struct clk vpif0_clk = {
234	.name = "vpif0",
235	.parent = &ref_clk,
236	.lpsc = DM646X_LPSC_VPSSMSTR,
237	.flags = ALWAYS_ENABLED,
238	};
239
240	static struct clk vpif1_clk = {
241	.name = "vpif1",
242	.parent = &ref_clk,
243	.lpsc = DM646X_LPSC_VPSSSLV,
244	.flags = ALWAYS_ENABLED,
245	};
246
247	struct davinci_clk dm646x_clks[] = {
248	CLK(NULL, "ref", &ref_clk),
249	CLK(NULL, "aux", &aux_clkin),
250	CLK(NULL, "pll1", &pll1_clk),
251	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
252	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
253	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
254	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
255	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
256	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
257	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
258	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
259	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
260	CLK(NULL, "pll1_aux", &pll1_aux_clk),
261	CLK(NULL, "pll2", &pll2_clk),
262	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
263	CLK(NULL, "dsp", &dsp_clk),
264	CLK(NULL, "arm", &arm_clk),
265	CLK(NULL, "uart0", &uart0_clk),
266	CLK(NULL, "uart1", &uart1_clk),
267	CLK(NULL, "uart2", &uart2_clk),
268	CLK("i2c_davinci.1", NULL, &i2c_clk),
269	CLK(NULL, "gpio", &gpio_clk),
270	CLK(NULL, "aemif", &aemif_clk),
271	CLK("davinci_emac.1", NULL, &emac_clk),
272	CLK(NULL, "pwm0", &pwm0_clk),
273	CLK(NULL, "pwm1", &pwm1_clk),
274	CLK(NULL, "timer0", &timer0_clk),
275	CLK(NULL, "timer1", &timer1_clk),
276	CLK("watchdog", NULL, &timer2_clk),
277	CLK(NULL, "vpif0", &vpif0_clk),
278	CLK(NULL, "vpif1", &vpif1_clk),
279	CLK(NULL, NULL, NULL),
280	};
281
282	/*
283	* Device specific mux setup
284	*
285	* soc description mux mode mode mux dbg
286	* reg offset mask mode
287	*/
288	static const struct mux_config dm646x_pins[] = {
289	MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
290
291	MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
292
293	MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
294
295	MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
296
297	MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
298
299	MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
300
301	MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
302
303	MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
304
305	MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
306
307	MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
308
309	MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
310
311	MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
312
313	MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
314
315	MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
316	};
317
318	/----------------------------------------------------------------------/
319
320	static const s8 dma_chan_dm646x_no_event[] = {
321	0, 1, 2, 3, 13,
322	14, 15, 24, 25, 26,
323	27, 30, 31, 54, 55,
324	56,
325	-1
326	};
327
328	static struct edma_soc_info dm646x_edma_info = {
329	.n_channel = 64,
330	.n_region = 6, /* 0-1, 4-7 */
331	.n_slot = 512,
332	.n_tc = 4,
333	.noevent = dma_chan_dm646x_no_event,
334	};
335
336	static struct resource edma_resources[] = {
337	{
338	.name = "edma_cc",
339	.start = 0x01c00000,
340	.end = 0x01c00000 + SZ_64K - 1,
341	.flags = IORESOURCE_MEM,
342	},
343	{
344	.name = "edma_tc0",
345	.start = 0x01c10000,
346	.end = 0x01c10000 + SZ_1K - 1,
347	.flags = IORESOURCE_MEM,
348	},
349	{
350	.name = "edma_tc1",
351	.start = 0x01c10400,
352	.end = 0x01c10400 + SZ_1K - 1,
353	.flags = IORESOURCE_MEM,
354	},
355	{
356	.name = "edma_tc2",
357	.start = 0x01c10800,
358	.end = 0x01c10800 + SZ_1K - 1,
359	.flags = IORESOURCE_MEM,
360	},
361	{
362	.name = "edma_tc3",
363	.start = 0x01c10c00,
364	.end = 0x01c10c00 + SZ_1K - 1,
365	.flags = IORESOURCE_MEM,
366	},
367	{
368	.start = IRQ_CCINT0,
369	.flags = IORESOURCE_IRQ,
370	},
371	{
372	.start = IRQ_CCERRINT,
373	.flags = IORESOURCE_IRQ,
374	},
375	/* not using TC_ERR /
376	};
377
378	static struct platform_device dm646x_edma_device = {
379	.name = "edma",
380	.id = -1,
381	.dev.platform_data = &dm646x_edma_info,
382	.num_resources = ARRAY_SIZE(edma_resources),
383	.resource = edma_resources,
384	};
385
386	/----------------------------------------------------------------------/
387
388	void __init dm646x_init(void)
389	{
390	davinci_clk_init(dm646x_clks);
391	davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
392	}
393
394	static int __init dm646x_init_devices(void)
395	{
396	if (!cpu_is_davinci_dm646x())
397	return 0;
398
399	platform_device_register(&dm646x_edma_device);
400	return 0;
401	}
402	postcore_initcall(dm646x_init_devices);