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davinci: dm646x-evm: Add support for IDE
[net-next-2.6.git] / arch / arm / mach-davinci / dm646x.c
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e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
65e866a9 14#include <linux/serial_8250.h>
e38d92fd 15#include <linux/platform_device.h>
a994955c 16#include <linux/gpio.h>
e38d92fd 17
79c3c0b7
MG		 18#include <asm/mach/map.h>
19
e38d92fd
KH		 20#include <mach/dm646x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h>
23#include <mach/edma.h>
24#include <mach/irqs.h>
25#include <mach/psc.h>
26#include <mach/mux.h>
f64691b3 27#include <mach/time.h>
65e866a9 28#include <mach/serial.h>
79c3c0b7 29#include <mach/common.h>
25acf553 30#include <mach/asp.h>
e38d92fd
KH		 31
32#include "clock.h"
33#include "mux.h"
34
35/*
36 * Device specific clocks
37 */
38#define DM646X_REF_FREQ 27000000
39#define DM646X_AUX_FREQ 24000000
40
41static struct pll_data pll1_data = {
42 .num = 1,
43 .phys_base = DAVINCI_PLL1_BASE,
44};
45
46static struct pll_data pll2_data = {
47 .num = 2,
48 .phys_base = DAVINCI_PLL2_BASE,
49};
50
51static struct clk ref_clk = {
52 .name = "ref_clk",
53 .rate = DM646X_REF_FREQ,
54};
55
56static struct clk aux_clkin = {
57 .name = "aux_clkin",
58 .rate = DM646X_AUX_FREQ,
59};
60
61static struct clk pll1_clk = {
62 .name = "pll1",
63 .parent = &ref_clk,
64 .pll_data = &pll1_data,
65 .flags = CLK_PLL,
66};
67
68static struct clk pll1_sysclk1 = {
69 .name = "pll1_sysclk1",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV1,
73};
74
75static struct clk pll1_sysclk2 = {
76 .name = "pll1_sysclk2",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV2,
80};
81
82static struct clk pll1_sysclk3 = {
83 .name = "pll1_sysclk3",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV3,
87};
88
89static struct clk pll1_sysclk4 = {
90 .name = "pll1_sysclk4",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV4,
94};
95
96static struct clk pll1_sysclk5 = {
97 .name = "pll1_sysclk5",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV5,
101};
102
103static struct clk pll1_sysclk6 = {
104 .name = "pll1_sysclk6",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV6,
108};
109
110static struct clk pll1_sysclk8 = {
111 .name = "pll1_sysclk8",
112 .parent = &pll1_clk,
113 .flags = CLK_PLL,
114 .div_reg = PLLDIV8,
115};
116
117static struct clk pll1_sysclk9 = {
118 .name = "pll1_sysclk9",
119 .parent = &pll1_clk,
120 .flags = CLK_PLL,
121 .div_reg = PLLDIV9,
122};
123
124static struct clk pll1_sysclkbp = {
125 .name = "pll1_sysclkbp",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL | PRE_PLL,
128 .div_reg = BPDIV,
129};
130
131static struct clk pll1_aux_clk = {
132 .name = "pll1_aux_clk",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL | PRE_PLL,
135};
136
137static struct clk pll2_clk = {
138 .name = "pll2_clk",
139 .parent = &ref_clk,
140 .pll_data = &pll2_data,
141 .flags = CLK_PLL,
142};
143
144static struct clk pll2_sysclk1 = {
145 .name = "pll2_sysclk1",
146 .parent = &pll2_clk,
147 .flags = CLK_PLL,
148 .div_reg = PLLDIV1,
149};
150
151static struct clk dsp_clk = {
152 .name = "dsp",
153 .parent = &pll1_sysclk1,
154 .lpsc = DM646X_LPSC_C64X_CPU,
155 .flags = PSC_DSP,
156 .usecount = 1, /* REVISIT how to disable? */
157};
158
159static struct clk arm_clk = {
160 .name = "arm",
161 .parent = &pll1_sysclk2,
162 .lpsc = DM646X_LPSC_ARM,
163 .flags = ALWAYS_ENABLED,
164};
165
2bcb613a
SR		 166static struct clk edma_cc_clk = {
167 .name = "edma_cc",
168 .parent = &pll1_sysclk2,
169 .lpsc = DM646X_LPSC_TPCC,
170 .flags = ALWAYS_ENABLED,
171};
172
173static struct clk edma_tc0_clk = {
174 .name = "edma_tc0",
175 .parent = &pll1_sysclk2,
176 .lpsc = DM646X_LPSC_TPTC0,
177 .flags = ALWAYS_ENABLED,
178};
179
180static struct clk edma_tc1_clk = {
181 .name = "edma_tc1",
182 .parent = &pll1_sysclk2,
183 .lpsc = DM646X_LPSC_TPTC1,
184 .flags = ALWAYS_ENABLED,
185};
186
187static struct clk edma_tc2_clk = {
188 .name = "edma_tc2",
189 .parent = &pll1_sysclk2,
190 .lpsc = DM646X_LPSC_TPTC2,
191 .flags = ALWAYS_ENABLED,
192};
193
194static struct clk edma_tc3_clk = {
195 .name = "edma_tc3",
196 .parent = &pll1_sysclk2,
197 .lpsc = DM646X_LPSC_TPTC3,
198 .flags = ALWAYS_ENABLED,
199};
200
e38d92fd
KH		 201static struct clk uart0_clk = {
202 .name = "uart0",
203 .parent = &aux_clkin,
204 .lpsc = DM646X_LPSC_UART0,
205};
206
207static struct clk uart1_clk = {
208 .name = "uart1",
209 .parent = &aux_clkin,
210 .lpsc = DM646X_LPSC_UART1,
211};
212
213static struct clk uart2_clk = {
214 .name = "uart2",
215 .parent = &aux_clkin,
216 .lpsc = DM646X_LPSC_UART2,
217};
218
219static struct clk i2c_clk = {
220 .name = "I2CCLK",
221 .parent = &pll1_sysclk3,
222 .lpsc = DM646X_LPSC_I2C,
223};
224
225static struct clk gpio_clk = {
226 .name = "gpio",
227 .parent = &pll1_sysclk3,
228 .lpsc = DM646X_LPSC_GPIO,
229};
230
75d0fa70
C		 231static struct clk mcasp0_clk = {
232 .name = "mcasp0",
233 .parent = &pll1_sysclk3,
234 .lpsc = DM646X_LPSC_McASP0,
235};
236
237static struct clk mcasp1_clk = {
238 .name = "mcasp1",
239 .parent = &pll1_sysclk3,
240 .lpsc = DM646X_LPSC_McASP1,
241};
242
e38d92fd
KH		 243static struct clk aemif_clk = {
244 .name = "aemif",
245 .parent = &pll1_sysclk3,
246 .lpsc = DM646X_LPSC_AEMIF,
247 .flags = ALWAYS_ENABLED,
248};
249
250static struct clk emac_clk = {
251 .name = "emac",
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_EMAC,
254};
255
256static struct clk pwm0_clk = {
257 .name = "pwm0",
258 .parent = &pll1_sysclk3,
259 .lpsc = DM646X_LPSC_PWM0,
260 .usecount = 1, /* REVIST: disabling hangs system */
261};
262
263static struct clk pwm1_clk = {
264 .name = "pwm1",
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_PWM1,
267 .usecount = 1, /* REVIST: disabling hangs system */
268};
269
270static struct clk timer0_clk = {
271 .name = "timer0",
272 .parent = &pll1_sysclk3,
273 .lpsc = DM646X_LPSC_TIMER0,
274};
275
276static struct clk timer1_clk = {
277 .name = "timer1",
278 .parent = &pll1_sysclk3,
279 .lpsc = DM646X_LPSC_TIMER1,
280};
281
282static struct clk timer2_clk = {
283 .name = "timer2",
284 .parent = &pll1_sysclk3,
285 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
286};
287
3e25d5f4
HP		 288
289static struct clk ide_clk = {
290 .name = "ide",
291 .parent = &pll1_sysclk4,
292 .lpsc = DAVINCI_LPSC_ATA,
293};
294
e38d92fd
KH		 295static struct clk vpif0_clk = {
296 .name = "vpif0",
297 .parent = &ref_clk,
298 .lpsc = DM646X_LPSC_VPSSMSTR,
299 .flags = ALWAYS_ENABLED,
300};
301
302static struct clk vpif1_clk = {
303 .name = "vpif1",
304 .parent = &ref_clk,
305 .lpsc = DM646X_LPSC_VPSSSLV,
306 .flags = ALWAYS_ENABLED,
307};
308
309struct davinci_clk dm646x_clks[] = {
310 CLK(NULL, "ref", &ref_clk),
311 CLK(NULL, "aux", &aux_clkin),
312 CLK(NULL, "pll1", &pll1_clk),
313 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
314 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
315 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
316 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
317 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
318 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
319 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
320 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
322 CLK(NULL, "pll1_aux", &pll1_aux_clk),
323 CLK(NULL, "pll2", &pll2_clk),
324 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
325 CLK(NULL, "dsp", &dsp_clk),
326 CLK(NULL, "arm", &arm_clk),
2bcb613a
SR		 327 CLK(NULL, "edma_cc", &edma_cc_clk),
328 CLK(NULL, "edma_tc0", &edma_tc0_clk),
329 CLK(NULL, "edma_tc1", &edma_tc1_clk),
330 CLK(NULL, "edma_tc2", &edma_tc2_clk),
331 CLK(NULL, "edma_tc3", &edma_tc3_clk),
e38d92fd
KH		 332 CLK(NULL, "uart0", &uart0_clk),
333 CLK(NULL, "uart1", &uart1_clk),
334 CLK(NULL, "uart2", &uart2_clk),
335 CLK("i2c_davinci.1", NULL, &i2c_clk),
336 CLK(NULL, "gpio", &gpio_clk),
75d0fa70
C		 337 CLK(NULL, "mcasp0", &mcasp0_clk),
338 CLK(NULL, "mcasp1", &mcasp1_clk),
e38d92fd
KH		 339 CLK(NULL, "aemif", &aemif_clk),
340 CLK("davinci_emac.1", NULL, &emac_clk),
341 CLK(NULL, "pwm0", &pwm0_clk),
342 CLK(NULL, "pwm1", &pwm1_clk),
343 CLK(NULL, "timer0", &timer0_clk),
344 CLK(NULL, "timer1", &timer1_clk),
345 CLK("watchdog", NULL, &timer2_clk),
3e25d5f4 346 CLK("palm_bk3710", NULL, &ide_clk),
e38d92fd
KH		 347 CLK(NULL, "vpif0", &vpif0_clk),
348 CLK(NULL, "vpif1", &vpif1_clk),
349 CLK(NULL, NULL, NULL),
350};
351
972412b6
MG		 352static struct emac_platform_data dm646x_emac_pdata = {
353 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
354 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
355 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
356 .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
357 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
358 .version = EMAC_VERSION_2,
359};
360
ac7b75b5
KH		 361static struct resource dm646x_emac_resources[] = {
362 {
363 .start = DM646X_EMAC_BASE,
364 .end = DM646X_EMAC_BASE + 0x47ff,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = IRQ_DM646X_EMACRXTHINT,
369 .end = IRQ_DM646X_EMACRXTHINT,
370 .flags = IORESOURCE_IRQ,
371 },
372 {
373 .start = IRQ_DM646X_EMACRXINT,
374 .end = IRQ_DM646X_EMACRXINT,
375 .flags = IORESOURCE_IRQ,
376 },
377 {
378 .start = IRQ_DM646X_EMACTXINT,
379 .end = IRQ_DM646X_EMACTXINT,
380 .flags = IORESOURCE_IRQ,
381 },
382 {
383 .start = IRQ_DM646X_EMACMISCINT,
384 .end = IRQ_DM646X_EMACMISCINT,
385 .flags = IORESOURCE_IRQ,
386 },
387};
388
389static struct platform_device dm646x_emac_device = {
390 .name = "davinci_emac",
391 .id = 1,
972412b6
MG		 392 .dev = {
393 .platform_data = &dm646x_emac_pdata,
394 },
ac7b75b5
KH		 395 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
396 .resource = dm646x_emac_resources,
397};
398
5570078c
MG		 399#define PINMUX0 0x00
400#define PINMUX1 0x04
401
e38d92fd
KH		 402/*
403 * Device specific mux setup
404 *
405 * soc description mux mode mode mux dbg
406 * reg offset mask mode
407 */
408static const struct mux_config dm646x_pins[] = {
0e585952 409#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 410MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
e38d92fd
KH		 411
412MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
413
414MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
415
416MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
417
418MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
419
420MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
421
422MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
423
424MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
425
426MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
427
428MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
429
430MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
431
432MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
433
434MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
435
436MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 437#endif
e38d92fd
KH		 438};
439
673dd36f
MG		 440static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
441 [IRQ_DM646X_VP_VERTINT0] = 7,
442 [IRQ_DM646X_VP_VERTINT1] = 7,
443 [IRQ_DM646X_VP_VERTINT2] = 7,
444 [IRQ_DM646X_VP_VERTINT3] = 7,
445 [IRQ_DM646X_VP_ERRINT] = 7,
446 [IRQ_DM646X_RESERVED_1] = 7,
447 [IRQ_DM646X_RESERVED_2] = 7,
448 [IRQ_DM646X_WDINT] = 7,
449 [IRQ_DM646X_CRGENINT0] = 7,
450 [IRQ_DM646X_CRGENINT1] = 7,
451 [IRQ_DM646X_TSIFINT0] = 7,
452 [IRQ_DM646X_TSIFINT1] = 7,
453 [IRQ_DM646X_VDCEINT] = 7,
454 [IRQ_DM646X_USBINT] = 7,
455 [IRQ_DM646X_USBDMAINT] = 7,
456 [IRQ_DM646X_PCIINT] = 7,
457 [IRQ_CCINT0] = 7, /* dma */
458 [IRQ_CCERRINT] = 7, /* dma */
459 [IRQ_TCERRINT0] = 7, /* dma */
460 [IRQ_TCERRINT] = 7, /* dma */
461 [IRQ_DM646X_TCERRINT2] = 7,
462 [IRQ_DM646X_TCERRINT3] = 7,
463 [IRQ_DM646X_IDE] = 7,
464 [IRQ_DM646X_HPIINT] = 7,
465 [IRQ_DM646X_EMACRXTHINT] = 7,
466 [IRQ_DM646X_EMACRXINT] = 7,
467 [IRQ_DM646X_EMACTXINT] = 7,
468 [IRQ_DM646X_EMACMISCINT] = 7,
469 [IRQ_DM646X_MCASP0TXINT] = 7,
470 [IRQ_DM646X_MCASP0RXINT] = 7,
471 [IRQ_AEMIFINT] = 7,
472 [IRQ_DM646X_RESERVED_3] = 7,
473 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
474 [IRQ_TINT0_TINT34] = 7, /* clocksource */
475 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
476 [IRQ_TINT1_TINT34] = 7, /* system tick */
477 [IRQ_PWMINT0] = 7,
478 [IRQ_PWMINT1] = 7,
479 [IRQ_DM646X_VLQINT] = 7,
480 [IRQ_I2C] = 7,
481 [IRQ_UARTINT0] = 7,
482 [IRQ_UARTINT1] = 7,
483 [IRQ_DM646X_UARTINT2] = 7,
484 [IRQ_DM646X_SPINT0] = 7,
485 [IRQ_DM646X_SPINT1] = 7,
486 [IRQ_DM646X_DSP2ARMINT] = 7,
487 [IRQ_DM646X_RESERVED_4] = 7,
488 [IRQ_DM646X_PSCINT] = 7,
489 [IRQ_DM646X_GPIO0] = 7,
490 [IRQ_DM646X_GPIO1] = 7,
491 [IRQ_DM646X_GPIO2] = 7,
492 [IRQ_DM646X_GPIO3] = 7,
493 [IRQ_DM646X_GPIO4] = 7,
494 [IRQ_DM646X_GPIO5] = 7,
495 [IRQ_DM646X_GPIO6] = 7,
496 [IRQ_DM646X_GPIO7] = 7,
497 [IRQ_DM646X_GPIOBNK0] = 7,
498 [IRQ_DM646X_GPIOBNK1] = 7,
499 [IRQ_DM646X_GPIOBNK2] = 7,
500 [IRQ_DM646X_DDRINT] = 7,
501 [IRQ_DM646X_AEMIFINT] = 7,
502 [IRQ_COMMTX] = 7,
503 [IRQ_COMMRX] = 7,
504 [IRQ_EMUINT] = 7,
505};
506
e38d92fd
KH		 507/*----------------------------------------------------------------------*/
508
509static const s8 dma_chan_dm646x_no_event[] = {
510 0, 1, 2, 3, 13,
511 14, 15, 24, 25, 26,
512 27, 30, 31, 54, 55,
513 56,
514 -1
515};
516
60902a2c
SR		 517/* Four Transfer Controllers on DM646x */
518static const s8
519dm646x_queue_tc_mapping[][2] = {
520 /* {event queue no, TC no} */
521 {0, 0},
522 {1, 1},
523 {2, 2},
524 {3, 3},
525 {-1, -1},
526};
527
528static const s8
529dm646x_queue_priority_mapping[][2] = {
530 /* {event queue no, Priority} */
531 {0, 4},
532 {1, 0},
533 {2, 5},
534 {3, 1},
535 {-1, -1},
536};
537
538static struct edma_soc_info dm646x_edma_info[] = {
539 {
540 .n_channel = 64,
541 .n_region = 6, /* 0-1, 4-7 */
542 .n_slot = 512,
543 .n_tc = 4,
544 .n_cc = 1,
545 .noevent = dma_chan_dm646x_no_event,
546 .queue_tc_mapping = dm646x_queue_tc_mapping,
547 .queue_priority_mapping = dm646x_queue_priority_mapping,
548 },
e38d92fd
KH		 549};
550
551static struct resource edma_resources[] = {
552 {
60902a2c 553 .name = "edma_cc0",
e38d92fd
KH		 554 .start = 0x01c00000,
555 .end = 0x01c00000 + SZ_64K - 1,
556 .flags = IORESOURCE_MEM,
557 },
558 {
559 .name = "edma_tc0",
560 .start = 0x01c10000,
561 .end = 0x01c10000 + SZ_1K - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 .name = "edma_tc1",
566 .start = 0x01c10400,
567 .end = 0x01c10400 + SZ_1K - 1,
568 .flags = IORESOURCE_MEM,
569 },
570 {
571 .name = "edma_tc2",
572 .start = 0x01c10800,
573 .end = 0x01c10800 + SZ_1K - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "edma_tc3",
578 .start = 0x01c10c00,
579 .end = 0x01c10c00 + SZ_1K - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
60902a2c 583 .name = "edma0",
e38d92fd
KH		 584 .start = IRQ_CCINT0,
585 .flags = IORESOURCE_IRQ,
586 },
587 {
60902a2c 588 .name = "edma0_err",
e38d92fd
KH		 589 .start = IRQ_CCERRINT,
590 .flags = IORESOURCE_IRQ,
591 },
592 /* not using TC*_ERR */
593};
594
595static struct platform_device dm646x_edma_device = {
596 .name = "edma",
60902a2c
SR		 597 .id = 0,
598 .dev.platform_data = dm646x_edma_info,
e38d92fd
KH		 599 .num_resources = ARRAY_SIZE(edma_resources),
600 .resource = edma_resources,
601};
602
1c92a554
HP		 603static struct resource ide_resources[] = {
604 {
605 .start = DM646X_ATA_REG_BASE,
606 .end = DM646X_ATA_REG_BASE + 0x7ff,
607 .flags = IORESOURCE_MEM,
608 },
609 {
610 .start = IRQ_DM646X_IDE,
611 .end = IRQ_DM646X_IDE,
612 .flags = IORESOURCE_IRQ,
613 },
614};
615
616static u64 ide_dma_mask = DMA_BIT_MASK(32);
617
618static struct platform_device ide_dev = {
619 .name = "palm_bk3710",
620 .id = -1,
621 .resource = ide_resources,
622 .num_resources = ARRAY_SIZE(ide_resources),
623 .dev = {
624 .dma_mask = &ide_dma_mask,
625 .coherent_dma_mask = DMA_BIT_MASK(32),
626 },
627};
628
25acf553
C		 629static struct resource dm646x_mcasp0_resources[] = {
630 {
631 .name = "mcasp0",
632 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
633 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
634 .flags = IORESOURCE_MEM,
635 },
636 /* first TX, then RX */
637 {
638 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
639 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
640 .flags = IORESOURCE_DMA,
641 },
642 {
643 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
644 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
645 .flags = IORESOURCE_DMA,
646 },
647};
648
649static struct resource dm646x_mcasp1_resources[] = {
650 {
651 .name = "mcasp1",
652 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
653 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
654 .flags = IORESOURCE_MEM,
655 },
656 /* DIT mode, only TX event */
657 {
658 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
659 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
660 .flags = IORESOURCE_DMA,
661 },
662 /* DIT mode, dummy entry */
663 {
664 .start = -1,
665 .end = -1,
666 .flags = IORESOURCE_DMA,
667 },
668};
669
670static struct platform_device dm646x_mcasp0_device = {
671 .name = "davinci-mcasp",
672 .id = 0,
673 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
674 .resource = dm646x_mcasp0_resources,
675};
676
677static struct platform_device dm646x_mcasp1_device = {
678 .name = "davinci-mcasp",
679 .id = 1,
680 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
681 .resource = dm646x_mcasp1_resources,
682};
683
684static struct platform_device dm646x_dit_device = {
685 .name = "spdif-dit",
686 .id = -1,
687};
688
e38d92fd
KH		 689/*----------------------------------------------------------------------*/
690
79c3c0b7
MG		 691static struct map_desc dm646x_io_desc[] = {
692 {
693 .virtual = IO_VIRT,
694 .pfn = __phys_to_pfn(IO_PHYS),
695 .length = IO_SIZE,
696 .type = MT_DEVICE
697 },
0d04eb47
DB		 698 {
699 .virtual = SRAM_VIRT,
700 .pfn = __phys_to_pfn(0x00010000),
701 .length = SZ_32K,
702 /* MT_MEMORY_NONCACHED requires supersection alignment */
703 .type = MT_DEVICE,
704 },
79c3c0b7
MG		 705};
706
b9ab1279
MG		 707/* Contents of JTAG ID register used to identify exact cpu type */
708static struct davinci_id dm646x_ids[] = {
709 {
710 .variant = 0x0,
711 .part_no = 0xb770,
712 .manufacturer = 0x017,
713 .cpu_id = DAVINCI_CPU_ID_DM6467,
714 .name = "dm6467",
715 },
716};
717
d81d188c
MG		 718static void __iomem *dm646x_psc_bases[] = {
719 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
720};
721
f64691b3
MG		 722/*
723 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
724 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
725 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
726 * T1_TOP: Timer 1, top : <unused>
727 */
728struct davinci_timer_info dm646x_timer_info = {
729 .timers = davinci_timer_instance,
730 .clockevent_id = T0_BOT,
731 .clocksource_id = T0_TOP,
732};
733
65e866a9
MG		 734static struct plat_serial8250_port dm646x_serial_platform_data[] = {
735 {
736 .mapbase = DAVINCI_UART0_BASE,
737 .irq = IRQ_UARTINT0,
738 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
739 UPF_IOREMAP,
740 .iotype = UPIO_MEM32,
741 .regshift = 2,
742 },
743 {
744 .mapbase = DAVINCI_UART1_BASE,
745 .irq = IRQ_UARTINT1,
746 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
747 UPF_IOREMAP,
748 .iotype = UPIO_MEM32,
749 .regshift = 2,
750 },
751 {
752 .mapbase = DAVINCI_UART2_BASE,
753 .irq = IRQ_DM646X_UARTINT2,
754 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
755 UPF_IOREMAP,
756 .iotype = UPIO_MEM32,
757 .regshift = 2,
758 },
759 {
760 .flags = 0
761 },
762};
763
764static struct platform_device dm646x_serial_device = {
765 .name = "serial8250",
766 .id = PLAT8250_DEV_PLATFORM,
767 .dev = {
768 .platform_data = dm646x_serial_platform_data,
769 },
770};
771
79c3c0b7
MG		 772static struct davinci_soc_info davinci_soc_info_dm646x = {
773 .io_desc = dm646x_io_desc,
774 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
b9ab1279
MG		 775 .jtag_id_base = IO_ADDRESS(0x01c40028),
776 .ids = dm646x_ids,
777 .ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399 778 .cpu_clks = dm646x_clks,
d81d188c
MG		 779 .psc_bases = dm646x_psc_bases,
780 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
0e585952
MG		 781 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
782 .pinmux_pins = dm646x_pins,
783 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
673dd36f
MG		 784 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
785 .intc_type = DAVINCI_INTC_TYPE_AINTC,
786 .intc_irq_prios = dm646x_default_priorities,
787 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 788 .timer_info = &dm646x_timer_info,
a994955c
MG		 789 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
790 .gpio_num = 43, /* Only 33 usable */
791 .gpio_irq = IRQ_DM646X_GPIOBNK0,
65e866a9 792 .serial_dev = &dm646x_serial_device,
972412b6 793 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 794 .sram_dma = 0x10010000,
795 .sram_len = SZ_32K,
79c3c0b7
MG		 796};
797
1c92a554
HP		 798void __init dm646x_init_ide()
799{
800 davinci_cfg_reg(DM646X_ATAEN);
801 platform_device_register(&ide_dev);
802}
803
25acf553
C		 804void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
805{
806 dm646x_mcasp0_device.dev.platform_data = pdata;
807 platform_device_register(&dm646x_mcasp0_device);
808}
809
810void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
811{
812 dm646x_mcasp1_device.dev.platform_data = pdata;
813 platform_device_register(&dm646x_mcasp1_device);
814 platform_device_register(&dm646x_dit_device);
815}
816
e38d92fd
KH		 817void __init dm646x_init(void)
818{
79c3c0b7 819 davinci_common_init(&davinci_soc_info_dm646x);
e38d92fd
KH		 820}
821
822static int __init dm646x_init_devices(void)
823{
824 if (!cpu_is_davinci_dm646x())
825 return 0;
826
827 platform_device_register(&dm646x_edma_device);
972412b6 828 platform_device_register(&dm646x_emac_device);
e38d92fd
KH		 829 return 0;
830}
831postcore_initcall(dm646x_init_devices);
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