[net-next-2.6.git] / arch / arm / mach-davinci / dm646x.c

/*
 * TI DaVinci DM644x chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

#include <asm/mach/map.h>

#include <mach/dm646x.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/common.h>

#include "clock.h"
#include "mux.h"

/*
 * Device specific clocks
 */
#define DM646X_REF_FREQ		27000000
#define DM646X_AUX_FREQ		24000000

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	.rate = DM646X_REF_FREQ,
};

static struct clk aux_clkin = {
	.name = "aux_clkin",
	.rate = DM646X_AUX_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.pll_data = &pll1_data,
	.flags = CLK_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclk5 = {
	.name = "pll1_sysclk5",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV5,
};

static struct clk pll1_sysclk6 = {
	.name = "pll1_sysclk6",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV6,
};

static struct clk pll1_sysclk8 = {
	.name = "pll1_sysclk8",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV8,
};

static struct clk pll1_sysclk9 = {
	.name = "pll1_sysclk9",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV9,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll2_clk = {
	.name = "pll2_clk",
	.parent = &ref_clk,
	.pll_data = &pll2_data,
	.flags = CLK_PLL,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk dsp_clk = {
	.name = "dsp",
	.parent = &pll1_sysclk1,
	.lpsc = DM646X_LPSC_C64X_CPU,
	.flags = PSC_DSP,
	.usecount = 1,			/* REVISIT how to disable? */
};

static struct clk arm_clk = {
	.name = "arm",
	.parent = &pll1_sysclk2,
	.lpsc = DM646X_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "I2CCLK",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_I2C,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_AEMIF,
	.flags = ALWAYS_ENABLED,
};

static struct clk emac_clk = {
	.name = "emac",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_EMAC,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM0,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM1,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_sysclk3,
	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
};

static struct clk vpif0_clk = {
	.name = "vpif0",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSMSTR,
	.flags = ALWAYS_ENABLED,
};

static struct clk vpif1_clk = {
	.name = "vpif1",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSSLV,
	.flags = ALWAYS_ENABLED,
};

struct davinci_clk dm646x_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "aux", &aux_clkin),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "dsp", &dsp_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK("davinci_emac.1", NULL, &emac_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "vpif0", &vpif0_clk),
	CLK(NULL, "vpif1", &vpif1_clk),
	CLK(NULL, NULL, NULL),
};

#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
static struct resource dm646x_emac_resources[] = {
	{
		.start	= DM646X_EMAC_BASE,
		.end	= DM646X_EMAC_BASE + 0x47ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DM646X_EMACRXTHINT,
		.end	= IRQ_DM646X_EMACRXTHINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACRXINT,
		.end	= IRQ_DM646X_EMACRXINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACTXINT,
		.end	= IRQ_DM646X_EMACTXINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACMISCINT,
		.end	= IRQ_DM646X_EMACMISCINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dm646x_emac_device = {
	.name		= "davinci_emac",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(dm646x_emac_resources),
	.resource	= dm646x_emac_resources,
};

#endif

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN,		0,   0,     1,	  1,	 true)

MUX_CFG(DM646X, AUDCK1,		0,   29,    1,	  0,	 false)

MUX_CFG(DM646X, AUDCK0,		0,   28,    1,	  0,	 false)

MUX_CFG(DM646X, CRGMUX,			0,   24,    7,    5,	 true)

MUX_CFG(DM646X, STSOMUX_DISABLE,	0,   22,    3,    0,	 true)

MUX_CFG(DM646X, STSIMUX_DISABLE,	0,   20,    3,    0,	 true)

MUX_CFG(DM646X, PTSOMUX_DISABLE,	0,   18,    3,    0,	 true)

MUX_CFG(DM646X, PTSIMUX_DISABLE,	0,   16,    3,    0,	 true)

MUX_CFG(DM646X, STSOMUX,		0,   22,    3,    2,	 true)

MUX_CFG(DM646X, STSIMUX,		0,   20,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_PARALLEL,	0,   18,    3,    2,	 true)

MUX_CFG(DM646X, PTSIMUX_PARALLEL,	0,   16,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_SERIAL,		0,   18,    3,    3,	 true)

MUX_CFG(DM646X, PTSIMUX_SERIAL,		0,   16,    3,    3,	 true)
#endif
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm646x_no_event[] = {
	 0,  1,  2,  3, 13,
	14, 15, 24, 25, 26,
	27, 30, 31, 54, 55,
	56,
	-1
};

static struct edma_soc_info dm646x_edma_info = {
	.n_channel	= 64,
	.n_region	= 6,	/* 0-1, 4-7 */
	.n_slot		= 512,
	.n_tc		= 4,
	.noevent	= dma_chan_dm646x_no_event,
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc2",
		.start	= 0x01c10800,
		.end	= 0x01c10800 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc3",
		.start	= 0x01c10c00,
		.end	= 0x01c10c00 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using TC*_ERR */
};

static struct platform_device dm646x_edma_device = {
	.name			= "edma",
	.id			= -1,
	.dev.platform_data	= &dm646x_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)

void dm646x_init_emac(struct emac_platform_data *pdata)
{
	pdata->ctrl_reg_offset		= DM646X_EMAC_CNTRL_OFFSET;
	pdata->ctrl_mod_reg_offset	= DM646X_EMAC_CNTRL_MOD_OFFSET;
	pdata->ctrl_ram_offset		= DM646X_EMAC_CNTRL_RAM_OFFSET;
	pdata->mdio_reg_offset		= DM646X_EMAC_MDIO_OFFSET;
	pdata->ctrl_ram_size		= DM646X_EMAC_CNTRL_RAM_SIZE;
	pdata->version			= EMAC_VERSION_2;
	dm646x_emac_device.dev.platform_data = pdata;
	platform_device_register(&dm646x_emac_device);
}
#else

void dm646x_init_emac(struct emac_platform_data *unused) {}

#endif

static struct map_desc dm646x_io_desc[] = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
};

/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm646x_ids[] = {
	{
		.variant	= 0x0,
		.part_no	= 0xb770,
		.manufacturer	= 0x017,
		.cpu_id		= DAVINCI_CPU_ID_DM6467,
		.name		= "dm6467",
	},
};

static void __iomem *dm646x_psc_bases[] = {
	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};

static struct davinci_soc_info davinci_soc_info_dm646x = {
	.io_desc		= dm646x_io_desc,
	.io_desc_num		= ARRAY_SIZE(dm646x_io_desc),
	.jtag_id_base		= IO_ADDRESS(0x01c40028),
	.ids			= dm646x_ids,
	.ids_num		= ARRAY_SIZE(dm646x_ids),
	.cpu_clks		= dm646x_clks,
	.psc_bases		= dm646x_psc_bases,
	.psc_bases_num		= ARRAY_SIZE(dm646x_psc_bases),
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	.pinmux_pins		= dm646x_pins,
	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
};

void __init dm646x_init(void)
{
	davinci_common_init(&davinci_soc_info_dm646x);
}

static int __init dm646x_init_devices(void)
{
	if (!cpu_is_davinci_dm646x())
		return 0;

	platform_device_register(&dm646x_edma_device);
	return 0;
}
postcore_initcall(dm646x_init_devices);
Commit	Line	Data
e38d92fd KH	1	/*
	2	* TI DaVinci DM644x chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
	14	#include <linux/platform_device.h>
	15
79c3c0b7 MG	16	#include <asm/mach/map.h>
79c3c0b7 MG	17
e38d92fd KH	18	#include <mach/dm646x.h>
	19	#include <mach/clock.h>
	20	#include <mach/cputype.h>
	21	#include <mach/edma.h>
	22	#include <mach/irqs.h>
	23	#include <mach/psc.h>
	24	#include <mach/mux.h>
79c3c0b7	25	#include <mach/common.h>
e38d92fd KH	26
	27	#include "clock.h"
	28	#include "mux.h"
	29
	30	/*
	31	* Device specific clocks
	32	*/
	33	#define DM646X_REF_FREQ 27000000
	34	#define DM646X_AUX_FREQ 24000000
	35
	36	static struct pll_data pll1_data = {
	37	.num = 1,
	38	.phys_base = DAVINCI_PLL1_BASE,
	39	};
	40
	41	static struct pll_data pll2_data = {
	42	.num = 2,
	43	.phys_base = DAVINCI_PLL2_BASE,
	44	};
	45
	46	static struct clk ref_clk = {
	47	.name = "ref_clk",
	48	.rate = DM646X_REF_FREQ,
	49	};
	50
	51	static struct clk aux_clkin = {
	52	.name = "aux_clkin",
	53	.rate = DM646X_AUX_FREQ,
	54	};
	55
	56	static struct clk pll1_clk = {
	57	.name = "pll1",
	58	.parent = &ref_clk,
	59	.pll_data = &pll1_data,
	60	.flags = CLK_PLL,
	61	};
	62
	63	static struct clk pll1_sysclk1 = {
	64	.name = "pll1_sysclk1",
	65	.parent = &pll1_clk,
	66	.flags = CLK_PLL,
	67	.div_reg = PLLDIV1,
	68	};
	69
	70	static struct clk pll1_sysclk2 = {
	71	.name = "pll1_sysclk2",
	72	.parent = &pll1_clk,
	73	.flags = CLK_PLL,
	74	.div_reg = PLLDIV2,
	75	};
	76
	77	static struct clk pll1_sysclk3 = {
	78	.name = "pll1_sysclk3",
	79	.parent = &pll1_clk,
	80	.flags = CLK_PLL,
	81	.div_reg = PLLDIV3,
	82	};
	83
	84	static struct clk pll1_sysclk4 = {
	85	.name = "pll1_sysclk4",
	86	.parent = &pll1_clk,
	87	.flags = CLK_PLL,
	88	.div_reg = PLLDIV4,
	89	};
90
91	static struct clk pll1_sysclk5 = {
92	.name = "pll1_sysclk5",
93	.parent = &pll1_clk,
94	.flags = CLK_PLL,
95	.div_reg = PLLDIV5,
96	};
97
98	static struct clk pll1_sysclk6 = {
99	.name = "pll1_sysclk6",
100	.parent = &pll1_clk,
101	.flags = CLK_PLL,
102	.div_reg = PLLDIV6,
103	};
104
105	static struct clk pll1_sysclk8 = {
106	.name = "pll1_sysclk8",
107	.parent = &pll1_clk,
108	.flags = CLK_PLL,
109	.div_reg = PLLDIV8,
110	};
111
112	static struct clk pll1_sysclk9 = {
113	.name = "pll1_sysclk9",
114	.parent = &pll1_clk,
115	.flags = CLK_PLL,
116	.div_reg = PLLDIV9,
117	};
118
119	static struct clk pll1_sysclkbp = {
120	.name = "pll1_sysclkbp",
121	.parent = &pll1_clk,
122	.flags = CLK_PLL \| PRE_PLL,
123	.div_reg = BPDIV,
124	};
125
126	static struct clk pll1_aux_clk = {
127	.name = "pll1_aux_clk",
128	.parent = &pll1_clk,
129	.flags = CLK_PLL \| PRE_PLL,
130	};
131
132	static struct clk pll2_clk = {
133	.name = "pll2_clk",
134	.parent = &ref_clk,
135	.pll_data = &pll2_data,
136	.flags = CLK_PLL,
137	};
138
139	static struct clk pll2_sysclk1 = {
140	.name = "pll2_sysclk1",
141	.parent = &pll2_clk,
142	.flags = CLK_PLL,
143	.div_reg = PLLDIV1,
144	};
145
146	static struct clk dsp_clk = {
147	.name = "dsp",
148	.parent = &pll1_sysclk1,
149	.lpsc = DM646X_LPSC_C64X_CPU,
150	.flags = PSC_DSP,
151	.usecount = 1, /* REVISIT how to disable? */
152	};
153
154	static struct clk arm_clk = {
155	.name = "arm",
156	.parent = &pll1_sysclk2,
157	.lpsc = DM646X_LPSC_ARM,
158	.flags = ALWAYS_ENABLED,
159	};
160
161	static struct clk uart0_clk = {
162	.name = "uart0",
163	.parent = &aux_clkin,
164	.lpsc = DM646X_LPSC_UART0,
165	};
166
167	static struct clk uart1_clk = {
168	.name = "uart1",
169	.parent = &aux_clkin,
170	.lpsc = DM646X_LPSC_UART1,
171	};
172
173	static struct clk uart2_clk = {
174	.name = "uart2",
175	.parent = &aux_clkin,
176	.lpsc = DM646X_LPSC_UART2,
177	};
178
179	static struct clk i2c_clk = {
180	.name = "I2CCLK",
181	.parent = &pll1_sysclk3,
182	.lpsc = DM646X_LPSC_I2C,
183	};
184
185	static struct clk gpio_clk = {
186	.name = "gpio",
187	.parent = &pll1_sysclk3,
188	.lpsc = DM646X_LPSC_GPIO,
189	};
190
191	static struct clk aemif_clk = {
192	.name = "aemif",
193	.parent = &pll1_sysclk3,
194	.lpsc = DM646X_LPSC_AEMIF,
195	.flags = ALWAYS_ENABLED,
196	};
197
198	static struct clk emac_clk = {
199	.name = "emac",
200	.parent = &pll1_sysclk3,
201	.lpsc = DM646X_LPSC_EMAC,
202	};
203
204	static struct clk pwm0_clk = {
205	.name = "pwm0",
206	.parent = &pll1_sysclk3,
207	.lpsc = DM646X_LPSC_PWM0,
208	.usecount = 1, /* REVIST: disabling hangs system */
209	};
210
211	static struct clk pwm1_clk = {
212	.name = "pwm1",
213	.parent = &pll1_sysclk3,
214	.lpsc = DM646X_LPSC_PWM1,
215	.usecount = 1, /* REVIST: disabling hangs system */
216	};
217
218	static struct clk timer0_clk = {
219	.name = "timer0",
220	.parent = &pll1_sysclk3,
221	.lpsc = DM646X_LPSC_TIMER0,
222	};
223
224	static struct clk timer1_clk = {
225	.name = "timer1",
226	.parent = &pll1_sysclk3,
227	.lpsc = DM646X_LPSC_TIMER1,
228	};
229
230	static struct clk timer2_clk = {
231	.name = "timer2",
232	.parent = &pll1_sysclk3,
233	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
234	};
235
236	static struct clk vpif0_clk = {
237	.name = "vpif0",
238	.parent = &ref_clk,
239	.lpsc = DM646X_LPSC_VPSSMSTR,
240	.flags = ALWAYS_ENABLED,
241	};
242
243	static struct clk vpif1_clk = {
244	.name = "vpif1",
245	.parent = &ref_clk,
246	.lpsc = DM646X_LPSC_VPSSSLV,
247	.flags = ALWAYS_ENABLED,
248	};
249
250	struct davinci_clk dm646x_clks[] = {
251	CLK(NULL, "ref", &ref_clk),
252	CLK(NULL, "aux", &aux_clkin),
253	CLK(NULL, "pll1", &pll1_clk),
254	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
255	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
256	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
257	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
258	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
259	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
260	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
261	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
262	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
263	CLK(NULL, "pll1_aux", &pll1_aux_clk),
264	CLK(NULL, "pll2", &pll2_clk),
265	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
266	CLK(NULL, "dsp", &dsp_clk),
267	CLK(NULL, "arm", &arm_clk),
268	CLK(NULL, "uart0", &uart0_clk),
269	CLK(NULL, "uart1", &uart1_clk),
270	CLK(NULL, "uart2", &uart2_clk),
271	CLK("i2c_davinci.1", NULL, &i2c_clk),
272	CLK(NULL, "gpio", &gpio_clk),
273	CLK(NULL, "aemif", &aemif_clk),
274	CLK("davinci_emac.1", NULL, &emac_clk),
275	CLK(NULL, "pwm0", &pwm0_clk),
276	CLK(NULL, "pwm1", &pwm1_clk),
277	CLK(NULL, "timer0", &timer0_clk),
278	CLK(NULL, "timer1", &timer1_clk),
279	CLK("watchdog", NULL, &timer2_clk),
280	CLK(NULL, "vpif0", &vpif0_clk),
281	CLK(NULL, "vpif1", &vpif1_clk),
282	CLK(NULL, NULL, NULL),
283	};
284
ac7b75b5 KH	285	#if defined(CONFIG_TI_DAVINCI_EMAC) \|\| defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
	286	static struct resource dm646x_emac_resources[] = {
	287	{
	288	.start = DM646X_EMAC_BASE,
	289	.end = DM646X_EMAC_BASE + 0x47ff,
	290	.flags = IORESOURCE_MEM,
	291	},
	292	{
	293	.start = IRQ_DM646X_EMACRXTHINT,
	294	.end = IRQ_DM646X_EMACRXTHINT,
	295	.flags = IORESOURCE_IRQ,
	296	},
	297	{
	298	.start = IRQ_DM646X_EMACRXINT,
	299	.end = IRQ_DM646X_EMACRXINT,
	300	.flags = IORESOURCE_IRQ,
	301	},
	302	{
	303	.start = IRQ_DM646X_EMACTXINT,
	304	.end = IRQ_DM646X_EMACTXINT,
	305	.flags = IORESOURCE_IRQ,
	306	},
	307	{
	308	.start = IRQ_DM646X_EMACMISCINT,
	309	.end = IRQ_DM646X_EMACMISCINT,
	310	.flags = IORESOURCE_IRQ,
	311	},
	312	};
	313
	314	static struct platform_device dm646x_emac_device = {
	315	.name = "davinci_emac",
	316	.id = 1,
	317	.num_resources = ARRAY_SIZE(dm646x_emac_resources),
	318	.resource = dm646x_emac_resources,
	319	};
	320
	321	#endif
	322
e38d92fd KH	323	/*
	324	* Device specific mux setup
	325	*
	326	* soc description mux mode mode mux dbg
	327	* reg offset mask mode
	328	*/
	329	static const struct mux_config dm646x_pins[] = {
0e585952	330	#ifdef CONFIG_DAVINCI_MUX
e38d92fd KH	331	MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
	332
	333	MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
	334
	335	MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
	336
	337	MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
	338
	339	MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
	340
	341	MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
	342
	343	MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
	344
	345	MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
	346
	347	MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
	348
	349	MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
	350
	351	MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
	352
	353	MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
	354
	355	MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
	356
	357	MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952	358	#endif
e38d92fd KH	359	};
	360
	361	/----------------------------------------------------------------------/
	362
	363	static const s8 dma_chan_dm646x_no_event[] = {
	364	0, 1, 2, 3, 13,
	365	14, 15, 24, 25, 26,
	366	27, 30, 31, 54, 55,
	367	56,
	368	-1
	369	};
	370
	371	static struct edma_soc_info dm646x_edma_info = {
	372	.n_channel = 64,
	373	.n_region = 6, /* 0-1, 4-7 */
	374	.n_slot = 512,
	375	.n_tc = 4,
	376	.noevent = dma_chan_dm646x_no_event,
	377	};
	378
	379	static struct resource edma_resources[] = {
	380	{
	381	.name = "edma_cc",
	382	.start = 0x01c00000,
	383	.end = 0x01c00000 + SZ_64K - 1,
	384	.flags = IORESOURCE_MEM,
	385	},
	386	{
	387	.name = "edma_tc0",
	388	.start = 0x01c10000,
	389	.end = 0x01c10000 + SZ_1K - 1,
	390	.flags = IORESOURCE_MEM,
	391	},
	392	{
	393	.name = "edma_tc1",
	394	.start = 0x01c10400,
	395	.end = 0x01c10400 + SZ_1K - 1,
	396	.flags = IORESOURCE_MEM,
	397	},
	398	{
	399	.name = "edma_tc2",
	400	.start = 0x01c10800,
	401	.end = 0x01c10800 + SZ_1K - 1,
	402	.flags = IORESOURCE_MEM,
	403	},
	404	{
	405	.name = "edma_tc3",
	406	.start = 0x01c10c00,
	407	.end = 0x01c10c00 + SZ_1K - 1,
	408	.flags = IORESOURCE_MEM,
	409	},
	410	{
	411	.start = IRQ_CCINT0,
	412	.flags = IORESOURCE_IRQ,
	413	},
	414	{
	415	.start = IRQ_CCERRINT,
	416	.flags = IORESOURCE_IRQ,
	417	},
	418	/* not using TC_ERR /
	419	};
	420
	421	static struct platform_device dm646x_edma_device = {
	422	.name = "edma",
423	.id = -1,
424	.dev.platform_data = &dm646x_edma_info,
425	.num_resources = ARRAY_SIZE(edma_resources),
426	.resource = edma_resources,
427	};
428
429	/----------------------------------------------------------------------/
430
ac7b75b5 KH	431	#if defined(CONFIG_TI_DAVINCI_EMAC) \|\| defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
	432
	433	void dm646x_init_emac(struct emac_platform_data *pdata)
	434	{
	435	pdata->ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET;
	436	pdata->ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET;
	437	pdata->ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET;
	438	pdata->mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET;
	439	pdata->ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE;
	440	pdata->version = EMAC_VERSION_2;
	441	dm646x_emac_device.dev.platform_data = pdata;
	442	platform_device_register(&dm646x_emac_device);
	443	}
	444	#else
	445
	446	void dm646x_init_emac(struct emac_platform_data *unused) {}
	447
	448	#endif
	449
79c3c0b7 MG	450	static struct map_desc dm646x_io_desc[] = {
	451	{
	452	.virtual = IO_VIRT,
	453	.pfn = __phys_to_pfn(IO_PHYS),
	454	.length = IO_SIZE,
	455	.type = MT_DEVICE
	456	},
	457	};
	458
b9ab1279 MG	459	/* Contents of JTAG ID register used to identify exact cpu type */
	460	static struct davinci_id dm646x_ids[] = {
	461	{
	462	.variant = 0x0,
	463	.part_no = 0xb770,
	464	.manufacturer = 0x017,
	465	.cpu_id = DAVINCI_CPU_ID_DM6467,
	466	.name = "dm6467",
	467	},
	468	};
	469
d81d188c MG	470	static void __iomem *dm646x_psc_bases[] = {
	471	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
	472	};
	473
79c3c0b7 MG	474	static struct davinci_soc_info davinci_soc_info_dm646x = {
	475	.io_desc = dm646x_io_desc,
	476	.io_desc_num = ARRAY_SIZE(dm646x_io_desc),
b9ab1279 MG	477	.jtag_id_base = IO_ADDRESS(0x01c40028),
	478	.ids = dm646x_ids,
	479	.ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399	480	.cpu_clks = dm646x_clks,
d81d188c MG	481	.psc_bases = dm646x_psc_bases,
d81d188c MG	482	.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
0e585952 MG	483	.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	484	.pinmux_pins = dm646x_pins,
	485	.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
79c3c0b7 MG	486	};
79c3c0b7 MG	487
e38d92fd KH	488	void __init dm646x_init(void)
e38d92fd KH	489	{
79c3c0b7	490	davinci_common_init(&davinci_soc_info_dm646x);
e38d92fd KH	491	}
	492
	493	static int __init dm646x_init_devices(void)
	494	{
	495	if (!cpu_is_davinci_dm646x())
	496	return 0;
	497
	498	platform_device_register(&dm646x_edma_device);
	499	return 0;
	500	}
	501	postcore_initcall(dm646x_init_devices);