[net-next-2.6.git] / arch / arm / mach-davinci / dm644x.c

/*
 * TI DaVinci DM644x chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <asm/mach/map.h>

#include <mach/dm644x.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/time.h>
#include <mach/serial.h>
#include <mach/common.h>

#include "clock.h"
#include "mux.h"

/*
 * Device specific clocks
 */
#define DM644X_REF_FREQ		27000000

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	.rate = DM644X_REF_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.pll_data = &pll1_data,
	.flags = CLK_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk5 = {
	.name = "pll1_sysclk5",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV5,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk pll2_clk = {
	.name = "pll2",
	.parent = &ref_clk,
	.pll_data = &pll2_data,
	.flags = CLK_PLL,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll2_sysclk2 = {
	.name = "pll2_sysclk2",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll2_sysclkbp = {
	.name = "pll2_sysclkbp",
	.parent = &pll2_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk dsp_clk = {
	.name = "dsp",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_GEM,
	.flags = PSC_DSP,
	.usecount = 1,			/* REVISIT how to disable? */
};

static struct clk arm_clk = {
	.name = "arm",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

static struct clk vicp_clk = {
	.name = "vicp",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_IMCOP,
	.flags = PSC_DSP,
	.usecount = 1,			/* REVISIT how to disable? */
};

static struct clk vpss_master_clk = {
	.name = "vpss_master",
	.parent = &pll1_sysclk3,
	.lpsc = DAVINCI_LPSC_VPSSMSTR,
	.flags = CLK_PSC,
};

static struct clk vpss_slave_clk = {
	.name = "vpss_slave",
	.parent = &pll1_sysclk3,
	.lpsc = DAVINCI_LPSC_VPSSSLV,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART2,
};

static struct clk emac_clk = {
	.name = "emac",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
};

static struct clk i2c_clk = {
	.name = "i2c",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_I2C,
};

static struct clk ide_clk = {
	.name = "ide",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_ATA,
};

static struct clk asp_clk = {
	.name = "asp0",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_McBSP,
};

static struct clk mmcsd_clk = {
	.name = "mmcsd",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_MMC_SD,
};

static struct clk spi_clk = {
	.name = "spi",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_SPI,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_GPIO,
};

static struct clk usb_clk = {
	.name = "usb",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_USB,
};

static struct clk vlynq_clk = {
	.name = "vlynq",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_VLYNQ,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk5,
	.lpsc = DAVINCI_LPSC_AEMIF,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM0,
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM1,
};

static struct clk pwm2_clk = {
	.name = "pwm2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM2,
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER2,
	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
};

struct davinci_clk dm644x_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
	CLK(NULL, "dsp", &dsp_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "vicp", &vicp_clk),
	CLK(NULL, "vpss_master", &vpss_master_clk),
	CLK(NULL, "vpss_slave", &vpss_slave_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("davinci_emac.1", NULL, &emac_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK("palm_bk3710", NULL, &ide_clk),
	CLK("soc-audio.0", NULL, &asp_clk),
	CLK("davinci_mmc.0", NULL, &mmcsd_clk),
	CLK(NULL, "spi", &spi_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "usb", &usb_clk),
	CLK(NULL, "vlynq", &vlynq_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "pwm2", &pwm2_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, NULL, NULL),
};

static struct emac_platform_data dm644x_emac_pdata = {
	.ctrl_reg_offset	= DM644X_EMAC_CNTRL_OFFSET,
	.ctrl_mod_reg_offset	= DM644X_EMAC_CNTRL_MOD_OFFSET,
	.ctrl_ram_offset	= DM644X_EMAC_CNTRL_RAM_OFFSET,
	.mdio_reg_offset	= DM644X_EMAC_MDIO_OFFSET,
	.ctrl_ram_size		= DM644X_EMAC_CNTRL_RAM_SIZE,
	.version		= EMAC_VERSION_1,
};

static struct resource dm644x_emac_resources[] = {
	{
		.start	= DM644X_EMAC_BASE,
		.end	= DM644X_EMAC_BASE + 0x47ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start = IRQ_EMACINT,
		.end   = IRQ_EMACINT,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device dm644x_emac_device = {
       .name		= "davinci_emac",
       .id		= 1,
       .dev = {
	       .platform_data	= &dm644x_emac_pdata,
       },
       .num_resources	= ARRAY_SIZE(dm644x_emac_resources),
       .resource	= dm644x_emac_resources,
};

#define PINMUX0		0x00
#define PINMUX1		0x04

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm644x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM644X, HDIREN,		0,   16,    1,	  1,	 true)
MUX_CFG(DM644X, ATAEN,		0,   17,    1,	  1,	 true)
MUX_CFG(DM644X, ATAEN_DISABLE,	0,   17,    1,	  0,	 true)

MUX_CFG(DM644X, HPIEN_DISABLE,	0,   29,    1,	  0,	 true)

MUX_CFG(DM644X, AEAW,		0,   0,     31,	  31,	 true)

MUX_CFG(DM644X, MSTK,		1,   9,     1,	  0,	 false)

MUX_CFG(DM644X, I2C,		1,   7,     1,	  1,	 false)

MUX_CFG(DM644X, MCBSP,		1,   10,    1,	  1,	 false)

MUX_CFG(DM644X, UART1,		1,   1,     1,	  1,	 true)
MUX_CFG(DM644X, UART2,		1,   2,     1,	  1,	 true)

MUX_CFG(DM644X, PWM0,		1,   4,     1,	  1,	 false)

MUX_CFG(DM644X, PWM1,		1,   5,     1,	  1,	 false)

MUX_CFG(DM644X, PWM2,		1,   6,     1,	  1,	 false)

MUX_CFG(DM644X, VLYNQEN,	0,   15,    1,	  1,	 false)
MUX_CFG(DM644X, VLSCREN,	0,   14,    1,	  1,	 false)
MUX_CFG(DM644X, VLYNQWD,	0,   12,    3,	  3,	 false)

MUX_CFG(DM644X, EMACEN,		0,   31,    1,	  1,	 true)

MUX_CFG(DM644X, GPIO3V,		0,   31,    1,	  0,	 true)

MUX_CFG(DM644X, GPIO0,		0,   24,    1,	  0,	 true)
MUX_CFG(DM644X, GPIO3,		0,   25,    1,	  0,	 false)
MUX_CFG(DM644X, GPIO43_44,	1,   7,     1,	  0,	 false)
MUX_CFG(DM644X, GPIO46_47,	0,   22,    1,	  0,	 true)

MUX_CFG(DM644X, RGB666,		0,   22,    1,	  1,	 true)

MUX_CFG(DM644X, LOEEN,		0,   24,    1,	  1,	 true)
MUX_CFG(DM644X, LFLDEN,		0,   25,    1,	  1,	 false)
#endif
};

/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	[IRQ_VDINT0]		= 2,
	[IRQ_VDINT1]		= 6,
	[IRQ_VDINT2]		= 6,
	[IRQ_HISTINT]		= 6,
	[IRQ_H3AINT]		= 6,
	[IRQ_PRVUINT]		= 6,
	[IRQ_RSZINT]		= 6,
	[7]			= 7,
	[IRQ_VENCINT]		= 6,
	[IRQ_ASQINT]		= 6,
	[IRQ_IMXINT]		= 6,
	[IRQ_VLCDINT]		= 6,
	[IRQ_USBINT]		= 4,
	[IRQ_EMACINT]		= 4,
	[14]			= 7,
	[15]			= 7,
	[IRQ_CCINT0]		= 5,	/* dma */
	[IRQ_CCERRINT]		= 5,	/* dma */
	[IRQ_TCERRINT0]		= 5,	/* dma */
	[IRQ_TCERRINT]		= 5,	/* dma */
	[IRQ_PSCIN]		= 7,
	[21]			= 7,
	[IRQ_IDE]		= 4,
	[23]			= 7,
	[IRQ_MBXINT]		= 7,
	[IRQ_MBRINT]		= 7,
	[IRQ_MMCINT]		= 7,
	[IRQ_SDIOINT]		= 7,
	[28]			= 7,
	[IRQ_DDRINT]		= 7,
	[IRQ_AEMIFINT]		= 7,
	[IRQ_VLQINT]		= 4,
	[IRQ_TINT0_TINT12]	= 2,	/* clockevent */
	[IRQ_TINT0_TINT34]	= 2,	/* clocksource */
	[IRQ_TINT1_TINT12]	= 7,	/* DSP timer */
	[IRQ_TINT1_TINT34]	= 7,	/* system tick */
	[IRQ_PWMINT0]		= 7,
	[IRQ_PWMINT1]		= 7,
	[IRQ_PWMINT2]		= 7,
	[IRQ_I2C]		= 3,
	[IRQ_UARTINT0]		= 3,
	[IRQ_UARTINT1]		= 3,
	[IRQ_UARTINT2]		= 3,
	[IRQ_SPINT0]		= 3,
	[IRQ_SPINT1]		= 3,
	[45]			= 7,
	[IRQ_DSP2ARM0]		= 4,
	[IRQ_DSP2ARM1]		= 4,
	[IRQ_GPIO0]		= 7,
	[IRQ_GPIO1]		= 7,
	[IRQ_GPIO2]		= 7,
	[IRQ_GPIO3]		= 7,
	[IRQ_GPIO4]		= 7,
	[IRQ_GPIO5]		= 7,
	[IRQ_GPIO6]		= 7,
	[IRQ_GPIO7]		= 7,
	[IRQ_GPIOBNK0]		= 7,
	[IRQ_GPIOBNK1]		= 7,
	[IRQ_GPIOBNK2]		= 7,
	[IRQ_GPIOBNK3]		= 7,
	[IRQ_GPIOBNK4]		= 7,
	[IRQ_COMMTX]		= 7,
	[IRQ_COMMRX]		= 7,
	[IRQ_EMUINT]		= 7,
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm644x_no_event[] = {
	 0,  1, 12, 13, 14,
	15, 25, 30, 31, 45,
	46, 47, 55, 56, 57,
	58, 59, 60, 61, 62,
	63,
	-1
};

static const s8
queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{1, 1},
	{-1, -1},
};

static const s8
queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{1, 7},
	{-1, -1},
};

static struct edma_soc_info dm644x_edma_info[] = {
	{
		.n_channel		= 64,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 2,
		.n_cc			= 1,
		.noevent		= dma_chan_dm644x_no_event,
		.queue_tc_mapping	= queue_tc_mapping,
		.queue_priority_mapping	= queue_priority_mapping,
	},
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using TC*_ERR */
};

static struct platform_device dm644x_edma_device = {
	.name			= "edma",
	.id			= 0,
	.dev.platform_data	= dm644x_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

static struct map_desc dm644x_io_desc[] = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= SRAM_VIRT,
		.pfn		= __phys_to_pfn(0x00008000),
		.length		= SZ_16K,
		/* MT_MEMORY_NONCACHED requires supersection alignment */
		.type		= MT_DEVICE,
	},
};

/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm644x_ids[] = {
	{
		.variant	= 0x0,
		.part_no	= 0xb700,
		.manufacturer	= 0x017,
		.cpu_id		= DAVINCI_CPU_ID_DM6446,
		.name		= "dm6446",
	},
};

static void __iomem *dm644x_psc_bases[] = {
	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};

/*
 * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 * T1_TOP: Timer 1, top   :  <unused>
 */
struct davinci_timer_info dm644x_timer_info = {
	.timers		= davinci_timer_instance,
	.clockevent_id	= T0_BOT,
	.clocksource_id	= T0_TOP,
};

static struct plat_serial8250_port dm644x_serial_platform_data[] = {
	{
		.mapbase	= DAVINCI_UART0_BASE,
		.irq		= IRQ_UARTINT0,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DAVINCI_UART1_BASE,
		.irq		= IRQ_UARTINT1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DAVINCI_UART2_BASE,
		.irq		= IRQ_UARTINT2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.flags		= 0
	},
};

static struct platform_device dm644x_serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= dm644x_serial_platform_data,
	},
};

static struct davinci_soc_info davinci_soc_info_dm644x = {
	.io_desc		= dm644x_io_desc,
	.io_desc_num		= ARRAY_SIZE(dm644x_io_desc),
	.jtag_id_base		= IO_ADDRESS(0x01c40028),
	.ids			= dm644x_ids,
	.ids_num		= ARRAY_SIZE(dm644x_ids),
	.cpu_clks		= dm644x_clks,
	.psc_bases		= dm644x_psc_bases,
	.psc_bases_num		= ARRAY_SIZE(dm644x_psc_bases),
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	.pinmux_pins		= dm644x_pins,
	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
	.intc_irq_prios 	= dm644x_default_priorities,
	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
	.timer_info		= &dm644x_timer_info,
	.wdt_base		= IO_ADDRESS(DAVINCI_WDOG_BASE),
	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
	.gpio_num		= 71,
	.gpio_irq		= IRQ_GPIOBNK0,
	.serial_dev		= &dm644x_serial_device,
	.emac_pdata		= &dm644x_emac_pdata,
	.sram_dma		= 0x00008000,
	.sram_len		= SZ_16K,
};

void __init dm644x_init(void)
{
	davinci_common_init(&davinci_soc_info_dm644x);
}

static int __init dm644x_init_devices(void)
{
	if (!cpu_is_davinci_dm644x())
		return 0;

	platform_device_register(&dm644x_edma_device);
	platform_device_register(&dm644x_emac_device);
	return 0;
}
postcore_initcall(dm644x_init_devices);
Commit	Line	Data
d0e47fba KH	1	/*
	2	* TI DaVinci DM644x chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
65e866a9	14	#include <linux/serial_8250.h>
d0e47fba	15	#include <linux/platform_device.h>
a994955c	16	#include <linux/gpio.h>
d0e47fba	17
79c3c0b7 MG	18	#include <asm/mach/map.h>
79c3c0b7 MG	19
d0e47fba KH	20	#include <mach/dm644x.h>
	21	#include <mach/clock.h>
	22	#include <mach/cputype.h>
	23	#include <mach/edma.h>
	24	#include <mach/irqs.h>
	25	#include <mach/psc.h>
	26	#include <mach/mux.h>
f64691b3	27	#include <mach/time.h>
65e866a9	28	#include <mach/serial.h>
79c3c0b7	29	#include <mach/common.h>
d0e47fba KH	30
	31	#include "clock.h"
	32	#include "mux.h"
	33
	34	/*
	35	* Device specific clocks
	36	*/
	37	#define DM644X_REF_FREQ 27000000
	38
	39	static struct pll_data pll1_data = {
	40	.num = 1,
	41	.phys_base = DAVINCI_PLL1_BASE,
	42	};
	43
	44	static struct pll_data pll2_data = {
	45	.num = 2,
	46	.phys_base = DAVINCI_PLL2_BASE,
	47	};
	48
	49	static struct clk ref_clk = {
	50	.name = "ref_clk",
	51	.rate = DM644X_REF_FREQ,
	52	};
	53
	54	static struct clk pll1_clk = {
	55	.name = "pll1",
	56	.parent = &ref_clk,
	57	.pll_data = &pll1_data,
	58	.flags = CLK_PLL,
	59	};
	60
	61	static struct clk pll1_sysclk1 = {
	62	.name = "pll1_sysclk1",
	63	.parent = &pll1_clk,
	64	.flags = CLK_PLL,
	65	.div_reg = PLLDIV1,
	66	};
	67
	68	static struct clk pll1_sysclk2 = {
	69	.name = "pll1_sysclk2",
	70	.parent = &pll1_clk,
	71	.flags = CLK_PLL,
	72	.div_reg = PLLDIV2,
	73	};
	74
	75	static struct clk pll1_sysclk3 = {
	76	.name = "pll1_sysclk3",
	77	.parent = &pll1_clk,
	78	.flags = CLK_PLL,
	79	.div_reg = PLLDIV3,
	80	};
	81
	82	static struct clk pll1_sysclk5 = {
	83	.name = "pll1_sysclk5",
	84	.parent = &pll1_clk,
	85	.flags = CLK_PLL,
	86	.div_reg = PLLDIV5,
	87	};
	88
	89	static struct clk pll1_aux_clk = {
	90	.name = "pll1_aux_clk",
	91	.parent = &pll1_clk,
	92	.flags = CLK_PLL \| PRE_PLL,
	93	};
94
95	static struct clk pll1_sysclkbp = {
96	.name = "pll1_sysclkbp",
97	.parent = &pll1_clk,
98	.flags = CLK_PLL \| PRE_PLL,
99	.div_reg = BPDIV
100	};
101
102	static struct clk pll2_clk = {
103	.name = "pll2",
104	.parent = &ref_clk,
105	.pll_data = &pll2_data,
106	.flags = CLK_PLL,
107	};
108
109	static struct clk pll2_sysclk1 = {
110	.name = "pll2_sysclk1",
111	.parent = &pll2_clk,
112	.flags = CLK_PLL,
113	.div_reg = PLLDIV1,
114	};
115
116	static struct clk pll2_sysclk2 = {
117	.name = "pll2_sysclk2",
118	.parent = &pll2_clk,
119	.flags = CLK_PLL,
120	.div_reg = PLLDIV2,
121	};
122
123	static struct clk pll2_sysclkbp = {
124	.name = "pll2_sysclkbp",
125	.parent = &pll2_clk,
126	.flags = CLK_PLL \| PRE_PLL,
127	.div_reg = BPDIV
128	};
129
130	static struct clk dsp_clk = {
131	.name = "dsp",
132	.parent = &pll1_sysclk1,
133	.lpsc = DAVINCI_LPSC_GEM,
134	.flags = PSC_DSP,
135	.usecount = 1, /* REVISIT how to disable? */
136	};
137
138	static struct clk arm_clk = {
139	.name = "arm",
140	.parent = &pll1_sysclk2,
141	.lpsc = DAVINCI_LPSC_ARM,
142	.flags = ALWAYS_ENABLED,
143	};
144
145	static struct clk vicp_clk = {
146	.name = "vicp",
147	.parent = &pll1_sysclk2,
148	.lpsc = DAVINCI_LPSC_IMCOP,
149	.flags = PSC_DSP,
150	.usecount = 1, /* REVISIT how to disable? */
151	};
152
153	static struct clk vpss_master_clk = {
154	.name = "vpss_master",
155	.parent = &pll1_sysclk3,
156	.lpsc = DAVINCI_LPSC_VPSSMSTR,
157	.flags = CLK_PSC,
158	};
159
160	static struct clk vpss_slave_clk = {
161	.name = "vpss_slave",
162	.parent = &pll1_sysclk3,
163	.lpsc = DAVINCI_LPSC_VPSSSLV,
164	};
165
166	static struct clk uart0_clk = {
167	.name = "uart0",
168	.parent = &pll1_aux_clk,
169	.lpsc = DAVINCI_LPSC_UART0,
170	};
171
172	static struct clk uart1_clk = {
173	.name = "uart1",
174	.parent = &pll1_aux_clk,
175	.lpsc = DAVINCI_LPSC_UART1,
176	};
177
178	static struct clk uart2_clk = {
179	.name = "uart2",
180	.parent = &pll1_aux_clk,
181	.lpsc = DAVINCI_LPSC_UART2,
182	};
183
184	static struct clk emac_clk = {
185	.name = "emac",
186	.parent = &pll1_sysclk5,
187	.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
188	};
189
190	static struct clk i2c_clk = {
191	.name = "i2c",
192	.parent = &pll1_aux_clk,
193	.lpsc = DAVINCI_LPSC_I2C,
194	};
195
196	static struct clk ide_clk = {
197	.name = "ide",
198	.parent = &pll1_sysclk5,
199	.lpsc = DAVINCI_LPSC_ATA,
200	};
201
202	static struct clk asp_clk = {
203	.name = "asp0",
204	.parent = &pll1_sysclk5,
205	.lpsc = DAVINCI_LPSC_McBSP,
206	};
207
208	static struct clk mmcsd_clk = {
209	.name = "mmcsd",
210	.parent = &pll1_sysclk5,
211	.lpsc = DAVINCI_LPSC_MMC_SD,
212	};
213
214	static struct clk spi_clk = {
215	.name = "spi",
216	.parent = &pll1_sysclk5,
217	.lpsc = DAVINCI_LPSC_SPI,
218	};
219
220	static struct clk gpio_clk = {
221	.name = "gpio",
222	.parent = &pll1_sysclk5,
223	.lpsc = DAVINCI_LPSC_GPIO,
224	};
225
226	static struct clk usb_clk = {
227	.name = "usb",
228	.parent = &pll1_sysclk5,
229	.lpsc = DAVINCI_LPSC_USB,
230	};
231
232	static struct clk vlynq_clk = {
233	.name = "vlynq",
234	.parent = &pll1_sysclk5,
235	.lpsc = DAVINCI_LPSC_VLYNQ,
236	};
237
238	static struct clk aemif_clk = {
239	.name = "aemif",
240	.parent = &pll1_sysclk5,
241	.lpsc = DAVINCI_LPSC_AEMIF,
242	};
243
244	static struct clk pwm0_clk = {
245	.name = "pwm0",
246	.parent = &pll1_aux_clk,
247	.lpsc = DAVINCI_LPSC_PWM0,
248	};
249
250	static struct clk pwm1_clk = {
251	.name = "pwm1",
252	.parent = &pll1_aux_clk,
253	.lpsc = DAVINCI_LPSC_PWM1,
254	};
255
256	static struct clk pwm2_clk = {
257	.name = "pwm2",
258	.parent = &pll1_aux_clk,
259	.lpsc = DAVINCI_LPSC_PWM2,
260	};
261
262	static struct clk timer0_clk = {
263	.name = "timer0",
264	.parent = &pll1_aux_clk,
265	.lpsc = DAVINCI_LPSC_TIMER0,
266	};
267
268	static struct clk timer1_clk = {
269	.name = "timer1",
270	.parent = &pll1_aux_clk,
271	.lpsc = DAVINCI_LPSC_TIMER1,
272	};
273
274	static struct clk timer2_clk = {
275	.name = "timer2",
276	.parent = &pll1_aux_clk,
277	.lpsc = DAVINCI_LPSC_TIMER2,
278	.usecount = 1, /* REVISIT: why cant' this be disabled? */
279	};
280
281	struct davinci_clk dm644x_clks[] = {
282	CLK(NULL, "ref", &ref_clk),
283	CLK(NULL, "pll1", &pll1_clk),
284	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
285	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
286	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
287	CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
288	CLK(NULL, "pll1_aux", &pll1_aux_clk),
289	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
290	CLK(NULL, "pll2", &pll2_clk),
291	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
292	CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
293	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
294	CLK(NULL, "dsp", &dsp_clk),
295	CLK(NULL, "arm", &arm_clk),
296	CLK(NULL, "vicp", &vicp_clk),
297	CLK(NULL, "vpss_master", &vpss_master_clk),
298	CLK(NULL, "vpss_slave", &vpss_slave_clk),
299	CLK(NULL, "arm", &arm_clk),
300	CLK(NULL, "uart0", &uart0_clk),
301	CLK(NULL, "uart1", &uart1_clk),
302	CLK(NULL, "uart2", &uart2_clk),
303	CLK("davinci_emac.1", NULL, &emac_clk),
304	CLK("i2c_davinci.1", NULL, &i2c_clk),
305	CLK("palm_bk3710", NULL, &ide_clk),
306	CLK("soc-audio.0", NULL, &asp_clk),
307	CLK("davinci_mmc.0", NULL, &mmcsd_clk),
308	CLK(NULL, "spi", &spi_clk),
309	CLK(NULL, "gpio", &gpio_clk),
310	CLK(NULL, "usb", &usb_clk),
311	CLK(NULL, "vlynq", &vlynq_clk),
312	CLK(NULL, "aemif", &aemif_clk),
313	CLK(NULL, "pwm0", &pwm0_clk),
314	CLK(NULL, "pwm1", &pwm1_clk),
315	CLK(NULL, "pwm2", &pwm2_clk),
316	CLK(NULL, "timer0", &timer0_clk),
317	CLK(NULL, "timer1", &timer1_clk),
318	CLK("watchdog", NULL, &timer2_clk),
319	CLK(NULL, NULL, NULL),
320	};
321
972412b6 MG	322	static struct emac_platform_data dm644x_emac_pdata = {
	323	.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
	324	.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
	325	.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
	326	.mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET,
	327	.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
	328	.version = EMAC_VERSION_1,
	329	};
d0e47fba KH	330
	331	static struct resource dm644x_emac_resources[] = {
	332	{
	333	.start = DM644X_EMAC_BASE,
	334	.end = DM644X_EMAC_BASE + 0x47ff,
	335	.flags = IORESOURCE_MEM,
	336	},
	337	{
	338	.start = IRQ_EMACINT,
	339	.end = IRQ_EMACINT,
	340	.flags = IORESOURCE_IRQ,
	341	},
	342	};
	343
	344	static struct platform_device dm644x_emac_device = {
	345	.name = "davinci_emac",
	346	.id = 1,
972412b6 MG	347	.dev = {
	348	.platform_data = &dm644x_emac_pdata,
	349	},
d0e47fba KH	350	.num_resources = ARRAY_SIZE(dm644x_emac_resources),
	351	.resource = dm644x_emac_resources,
	352	};
	353
5570078c MG	354	#define PINMUX0 0x00
	355	#define PINMUX1 0x04
	356
d0e47fba KH	357	/*
	358	* Device specific mux setup
	359	*
	360	* soc description mux mode mode mux dbg
	361	* reg offset mask mode
	362	*/
	363	static const struct mux_config dm644x_pins[] = {
0e585952	364	#ifdef CONFIG_DAVINCI_MUX
d0e47fba KH	365	MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
	366	MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
	367	MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
	368
	369	MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
	370
	371	MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
	372
	373	MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
	374
	375	MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
	376
	377	MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
	378
	379	MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
	380	MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
	381
	382	MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
	383
	384	MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
	385
	386	MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
	387
	388	MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
	389	MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
	390	MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
	391
	392	MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
	393
	394	MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
	395
	396	MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
	397	MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
	398	MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
	399	MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
	400
	401	MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
	402
	403	MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
	404	MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
0e585952	405	#endif
d0e47fba KH	406	};
d0e47fba KH	407
673dd36f MG	408	/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
	409	static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	410	[IRQ_VDINT0] = 2,
	411	[IRQ_VDINT1] = 6,
	412	[IRQ_VDINT2] = 6,
	413	[IRQ_HISTINT] = 6,
	414	[IRQ_H3AINT] = 6,
	415	[IRQ_PRVUINT] = 6,
	416	[IRQ_RSZINT] = 6,
	417	[7] = 7,
	418	[IRQ_VENCINT] = 6,
	419	[IRQ_ASQINT] = 6,
	420	[IRQ_IMXINT] = 6,
	421	[IRQ_VLCDINT] = 6,
	422	[IRQ_USBINT] = 4,
	423	[IRQ_EMACINT] = 4,
	424	[14] = 7,
	425	[15] = 7,
	426	[IRQ_CCINT0] = 5, /* dma */
	427	[IRQ_CCERRINT] = 5, /* dma */
	428	[IRQ_TCERRINT0] = 5, /* dma */
	429	[IRQ_TCERRINT] = 5, /* dma */
	430	[IRQ_PSCIN] = 7,
	431	[21] = 7,
	432	[IRQ_IDE] = 4,
	433	[23] = 7,
	434	[IRQ_MBXINT] = 7,
	435	[IRQ_MBRINT] = 7,
	436	[IRQ_MMCINT] = 7,
	437	[IRQ_SDIOINT] = 7,
	438	[28] = 7,
	439	[IRQ_DDRINT] = 7,
	440	[IRQ_AEMIFINT] = 7,
	441	[IRQ_VLQINT] = 4,
	442	[IRQ_TINT0_TINT12] = 2, /* clockevent */
	443	[IRQ_TINT0_TINT34] = 2, /* clocksource */
	444	[IRQ_TINT1_TINT12] = 7, /* DSP timer */
	445	[IRQ_TINT1_TINT34] = 7, /* system tick */
	446	[IRQ_PWMINT0] = 7,
	447	[IRQ_PWMINT1] = 7,
	448	[IRQ_PWMINT2] = 7,
	449	[IRQ_I2C] = 3,
	450	[IRQ_UARTINT0] = 3,
	451	[IRQ_UARTINT1] = 3,
	452	[IRQ_UARTINT2] = 3,
	453	[IRQ_SPINT0] = 3,
	454	[IRQ_SPINT1] = 3,
	455	[45] = 7,
	456	[IRQ_DSP2ARM0] = 4,
	457	[IRQ_DSP2ARM1] = 4,
	458	[IRQ_GPIO0] = 7,
	459	[IRQ_GPIO1] = 7,
	460	[IRQ_GPIO2] = 7,
	461	[IRQ_GPIO3] = 7,
	462	[IRQ_GPIO4] = 7,
	463	[IRQ_GPIO5] = 7,
	464	[IRQ_GPIO6] = 7,
	465	[IRQ_GPIO7] = 7,
	466	[IRQ_GPIOBNK0] = 7,
	467	[IRQ_GPIOBNK1] = 7,
	468	[IRQ_GPIOBNK2] = 7,
	469	[IRQ_GPIOBNK3] = 7,
	470	[IRQ_GPIOBNK4] = 7,
	471	[IRQ_COMMTX] = 7,
472	[IRQ_COMMRX] = 7,
473	[IRQ_EMUINT] = 7,
474	};
475
d0e47fba KH	476	/----------------------------------------------------------------------/
	477
	478	static const s8 dma_chan_dm644x_no_event[] = {
	479	0, 1, 12, 13, 14,
	480	15, 25, 30, 31, 45,
	481	46, 47, 55, 56, 57,
	482	58, 59, 60, 61, 62,
	483	63,
	484	-1
	485	};
	486
60902a2c SR	487	static const s8
	488	queue_tc_mapping[][2] = {
	489	/* {event queue no, TC no} */
	490	{0, 0},
	491	{1, 1},
	492	{-1, -1},
	493	};
	494
	495	static const s8
	496	queue_priority_mapping[][2] = {
	497	/* {event queue no, Priority} */
	498	{0, 3},
	499	{1, 7},
	500	{-1, -1},
	501	};
	502
	503	static struct edma_soc_info dm644x_edma_info[] = {
	504	{
	505	.n_channel = 64,
	506	.n_region = 4,
	507	.n_slot = 128,
	508	.n_tc = 2,
	509	.n_cc = 1,
	510	.noevent = dma_chan_dm644x_no_event,
	511	.queue_tc_mapping = queue_tc_mapping,
	512	.queue_priority_mapping = queue_priority_mapping,
	513	},
d0e47fba KH	514	};
	515
	516	static struct resource edma_resources[] = {
	517	{
60902a2c	518	.name = "edma_cc0",
d0e47fba KH	519	.start = 0x01c00000,
	520	.end = 0x01c00000 + SZ_64K - 1,
	521	.flags = IORESOURCE_MEM,
	522	},
	523	{
	524	.name = "edma_tc0",
	525	.start = 0x01c10000,
	526	.end = 0x01c10000 + SZ_1K - 1,
	527	.flags = IORESOURCE_MEM,
	528	},
	529	{
	530	.name = "edma_tc1",
	531	.start = 0x01c10400,
	532	.end = 0x01c10400 + SZ_1K - 1,
	533	.flags = IORESOURCE_MEM,
	534	},
	535	{
60902a2c	536	.name = "edma0",
d0e47fba KH	537	.start = IRQ_CCINT0,
	538	.flags = IORESOURCE_IRQ,
	539	},
	540	{
60902a2c	541	.name = "edma0_err",
d0e47fba KH	542	.start = IRQ_CCERRINT,
	543	.flags = IORESOURCE_IRQ,
	544	},
	545	/* not using TC_ERR /
	546	};
	547
	548	static struct platform_device dm644x_edma_device = {
	549	.name = "edma",
60902a2c SR	550	.id = 0,
60902a2c SR	551	.dev.platform_data = dm644x_edma_info,
d0e47fba KH	552	.num_resources = ARRAY_SIZE(edma_resources),
	553	.resource = edma_resources,
	554	};
	555
	556	/----------------------------------------------------------------------/
ac7b75b5	557
79c3c0b7 MG	558	static struct map_desc dm644x_io_desc[] = {
	559	{
	560	.virtual = IO_VIRT,
	561	.pfn = __phys_to_pfn(IO_PHYS),
	562	.length = IO_SIZE,
	563	.type = MT_DEVICE
	564	},
0d04eb47 DB	565	{
	566	.virtual = SRAM_VIRT,
	567	.pfn = __phys_to_pfn(0x00008000),
	568	.length = SZ_16K,
	569	/* MT_MEMORY_NONCACHED requires supersection alignment */
	570	.type = MT_DEVICE,
	571	},
79c3c0b7 MG	572	};
79c3c0b7 MG	573
b9ab1279 MG	574	/* Contents of JTAG ID register used to identify exact cpu type */
	575	static struct davinci_id dm644x_ids[] = {
	576	{
	577	.variant = 0x0,
	578	.part_no = 0xb700,
	579	.manufacturer = 0x017,
	580	.cpu_id = DAVINCI_CPU_ID_DM6446,
	581	.name = "dm6446",
	582	},
	583	};
	584
d81d188c MG	585	static void __iomem *dm644x_psc_bases[] = {
	586	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
	587	};
	588
f64691b3 MG	589	/*
	590	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
	591	* T0_TOP: Timer 0, top : clocksource for generic timekeeping
	592	* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
	593	* T1_TOP: Timer 1, top : <unused>
	594	*/
	595	struct davinci_timer_info dm644x_timer_info = {
	596	.timers = davinci_timer_instance,
	597	.clockevent_id = T0_BOT,
	598	.clocksource_id = T0_TOP,
	599	};
	600
65e866a9 MG	601	static struct plat_serial8250_port dm644x_serial_platform_data[] = {
	602	{
	603	.mapbase = DAVINCI_UART0_BASE,
	604	.irq = IRQ_UARTINT0,
	605	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	606	UPF_IOREMAP,
	607	.iotype = UPIO_MEM,
	608	.regshift = 2,
	609	},
	610	{
	611	.mapbase = DAVINCI_UART1_BASE,
	612	.irq = IRQ_UARTINT1,
	613	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	614	UPF_IOREMAP,
	615	.iotype = UPIO_MEM,
	616	.regshift = 2,
	617	},
	618	{
	619	.mapbase = DAVINCI_UART2_BASE,
	620	.irq = IRQ_UARTINT2,
	621	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	622	UPF_IOREMAP,
	623	.iotype = UPIO_MEM,
	624	.regshift = 2,
	625	},
	626	{
	627	.flags = 0
	628	},
	629	};
	630
	631	static struct platform_device dm644x_serial_device = {
	632	.name = "serial8250",
	633	.id = PLAT8250_DEV_PLATFORM,
	634	.dev = {
	635	.platform_data = dm644x_serial_platform_data,
	636	},
	637	};
	638
79c3c0b7 MG	639	static struct davinci_soc_info davinci_soc_info_dm644x = {
	640	.io_desc = dm644x_io_desc,
	641	.io_desc_num = ARRAY_SIZE(dm644x_io_desc),
b9ab1279 MG	642	.jtag_id_base = IO_ADDRESS(0x01c40028),
	643	.ids = dm644x_ids,
	644	.ids_num = ARRAY_SIZE(dm644x_ids),
66e0c399	645	.cpu_clks = dm644x_clks,
d81d188c MG	646	.psc_bases = dm644x_psc_bases,
d81d188c MG	647	.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
0e585952 MG	648	.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	649	.pinmux_pins = dm644x_pins,
	650	.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
673dd36f MG	651	.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	652	.intc_type = DAVINCI_INTC_TYPE_AINTC,
	653	.intc_irq_prios = dm644x_default_priorities,
	654	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3	655	.timer_info = &dm644x_timer_info,
951d6f6d	656	.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
a994955c MG	657	.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
	658	.gpio_num = 71,
	659	.gpio_irq = IRQ_GPIOBNK0,
65e866a9	660	.serial_dev = &dm644x_serial_device,
972412b6	661	.emac_pdata = &dm644x_emac_pdata,
0d04eb47 DB	662	.sram_dma = 0x00008000,
0d04eb47 DB	663	.sram_len = SZ_16K,
79c3c0b7 MG	664	};
79c3c0b7 MG	665
d0e47fba KH	666	void __init dm644x_init(void)
d0e47fba KH	667	{
79c3c0b7	668	davinci_common_init(&davinci_soc_info_dm644x);
d0e47fba KH	669	}
	670
	671	static int __init dm644x_init_devices(void)
	672	{
	673	if (!cpu_is_davinci_dm644x())
	674	return 0;
	675
	676	platform_device_register(&dm644x_edma_device);
972412b6	677	platform_device_register(&dm644x_emac_device);
d0e47fba KH	678	return 0;
	679	}
	680	postcore_initcall(dm644x_init_devices);