[net-next-2.6.git] / arch / arm / mach-davinci / dm355.c

/*
 * TI DaVinci DM355 chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>

#include <linux/spi/spi.h>

#include <asm/mach/map.h>

#include <mach/dm355.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
#include <mach/time.h>
#include <mach/serial.h>
#include <mach/common.h>

#include "clock.h"
#include "mux.h"

#define DM355_UART2_BASE	(IO_PHYS + 0x206000)

/*
 * Device specific clocks
 */
#define DM355_REF_FREQ		24000000	/* 24 or 36 MHz */

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
	.flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
	.flags     = PLL_HAS_PREDIV,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	/* FIXME -- crystal rate is board-specific */
	.rate = DM355_REF_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll1_data,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk vpss_dac_clk = {
	.name = "vpss_dac",
	.parent = &pll1_sysclk3,
	.lpsc = DM355_LPSC_VPSS_DAC,
};

static struct clk vpss_master_clk = {
	.name = "vpss_master",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSMSTR,
	.flags = CLK_PSC,
};

static struct clk vpss_slave_clk = {
	.name = "vpss_slave",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSSLV,
};


static struct clk clkout1_clk = {
	.name = "clkout1",
	.parent = &pll1_aux_clk,
	/* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
};

static struct clk clkout2_clk = {
	.name = "clkout2",
	.parent = &pll1_sysclkbp,
};

static struct clk pll2_clk = {
	.name = "pll2",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll2_data,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll2_sysclkbp = {
	.name = "pll2_sysclkbp",
	.parent = &pll2_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk clkout3_clk = {
	.name = "clkout3",
	.parent = &pll2_sysclkbp,
	/* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
};

static struct clk arm_clk = {
	.name = "arm_clk",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

/*
 * NOT LISTED below, and not touched by Linux
 *   - in SyncReset state by default
 *	.lpsc = DAVINCI_LPSC_TPCC,
 *	.lpsc = DAVINCI_LPSC_TPTC0,
 *	.lpsc = DAVINCI_LPSC_TPTC1,
 *	.lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 *	.lpsc = DAVINCI_LPSC_MEMSTICK,
 *   - in Enabled state by default
 *	.lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 *	.lpsc = DAVINCI_LPSC_SCR2,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR3,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR4,	// "bus"
 *	.lpsc = DAVINCI_LPSC_CROSSBAR,	// "emulation"
 *	.lpsc = DAVINCI_LPSC_CFG27,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG3,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG5,	// "test"
 */

static struct clk mjcp_clk = {
	.name = "mjcp",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_IMCOP,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "i2c",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_I2C,
};

static struct clk asp0_clk = {
	.name = "asp0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_McBSP,
};

static struct clk asp1_clk = {
	.name = "asp1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_McBSP1,
};

static struct clk mmcsd0_clk = {
	.name = "mmcsd0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_MMC_SD,
};

static struct clk mmcsd1_clk = {
	.name = "mmcsd1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_MMC_SD1,
};

static struct clk spi0_clk = {
	.name = "spi0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_SPI,
};

static struct clk spi1_clk = {
	.name = "spi1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI1,
};

static struct clk spi2_clk = {
	.name = "spi2",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI2,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_AEMIF,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM0,
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM1,
};

static struct clk pwm2_clk = {
	.name = "pwm2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM2,
};

static struct clk pwm3_clk = {
	.name = "pwm3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_PWM3,
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER2,
	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
};

static struct clk timer3_clk = {
	.name = "timer3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_TIMER3,
};

static struct clk rto_clk = {
	.name = "rto",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_RTO,
};

static struct clk usb_clk = {
	.name = "usb",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_USB,
};

static struct davinci_clk dm355_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
	CLK(NULL, "vpss_dac", &vpss_dac_clk),
	CLK(NULL, "vpss_master", &vpss_master_clk),
	CLK(NULL, "vpss_slave", &vpss_slave_clk),
	CLK(NULL, "clkout1", &clkout1_clk),
	CLK(NULL, "clkout2", &clkout2_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
	CLK(NULL, "clkout3", &clkout3_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "mjcp", &mjcp_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK("soc-audio.0", NULL, &asp0_clk),
	CLK("soc-audio.1", NULL, &asp1_clk),
	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
	CLK(NULL, "spi0", &spi0_clk),
	CLK(NULL, "spi1", &spi1_clk),
	CLK(NULL, "spi2", &spi2_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "pwm2", &pwm2_clk),
	CLK(NULL, "pwm3", &pwm3_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "timer3", &timer3_clk),
	CLK(NULL, "rto", &rto_clk),
	CLK(NULL, "usb", &usb_clk),
	CLK(NULL, NULL, NULL),
};

/*----------------------------------------------------------------------*/

static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);

static struct resource dm355_spi0_resources[] = {
	{
		.start = 0x01c66000,
		.end   = 0x01c667ff,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_DM355_SPINT0_1,
		.flags = IORESOURCE_IRQ,
	},
	/* Not yet used, so not included:
	 * IORESOURCE_IRQ:
	 *  - IRQ_DM355_SPINT0_0
	 * IORESOURCE_DMA:
	 *  - DAVINCI_DMA_SPI_SPIX
	 *  - DAVINCI_DMA_SPI_SPIR
	 */
};

static struct platform_device dm355_spi0_device = {
	.name = "spi_davinci",
	.id = 0,
	.dev = {
		.dma_mask = &dm355_spi0_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
	.resource = dm355_spi0_resources,
};

void __init dm355_init_spi0(unsigned chipselect_mask,
		struct spi_board_info *info, unsigned len)
{
	/* for now, assume we need MISO */
	davinci_cfg_reg(DM355_SPI0_SDI);

	/* not all slaves will be wired up */
	if (chipselect_mask & BIT(0))
		davinci_cfg_reg(DM355_SPI0_SDENA0);
	if (chipselect_mask & BIT(1))
		davinci_cfg_reg(DM355_SPI0_SDENA1);

	spi_register_board_info(info, len);

	platform_device_register(&dm355_spi0_device);
}

/*----------------------------------------------------------------------*/

#define PINMUX0		0x00
#define PINMUX1		0x04
#define PINMUX2		0x08
#define PINMUX3		0x0c
#define PINMUX4		0x10
#define INTMUX		0x18
#define EVTMUX		0x1c

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm355_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM355,	MMCSD0,		4,   2,     1,	  0,	 false)

MUX_CFG(DM355,	SD1_CLK,	3,   6,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_CMD,	3,   7,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA3,	3,   8,     3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA2,	3,   10,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA1,	3,   12,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA0,	3,   14,    3,	  1,	 false)

MUX_CFG(DM355,	I2C_SDA,	3,   19,    1,	  1,	 false)
MUX_CFG(DM355,	I2C_SCL,	3,   20,    1,	  1,	 false)

MUX_CFG(DM355,	MCBSP0_BDX,	3,   0,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_X,	3,   1,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSX,	3,   2,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BDR,	3,   3,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_R,	3,   4,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSR,	3,   5,     1,	  1,	 false)

MUX_CFG(DM355,	SPI0_SDI,	4,   1,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA0,	4,   0,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA1,	3,   28,    1,    1,	 false)

INT_CFG(DM355,  INT_EDMA_CC,	      2,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)

EVT_CFG(DM355,  EVT8_ASP1_TX,	      0,    1,    0,     false)
EVT_CFG(DM355,  EVT9_ASP1_RX,	      1,    1,    0,     false)
EVT_CFG(DM355,  EVT26_MMC0_RX,	      2,    1,    0,     false)
#endif
};

static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	[IRQ_DM355_CCDC_VDINT0]		= 2,
	[IRQ_DM355_CCDC_VDINT1]		= 6,
	[IRQ_DM355_CCDC_VDINT2]		= 6,
	[IRQ_DM355_IPIPE_HST]		= 6,
	[IRQ_DM355_H3AINT]		= 6,
	[IRQ_DM355_IPIPE_SDR]		= 6,
	[IRQ_DM355_IPIPEIFINT]		= 6,
	[IRQ_DM355_OSDINT]		= 7,
	[IRQ_DM355_VENCINT]		= 6,
	[IRQ_ASQINT]			= 6,
	[IRQ_IMXINT]			= 6,
	[IRQ_USBINT]			= 4,
	[IRQ_DM355_RTOINT]		= 4,
	[IRQ_DM355_UARTINT2]		= 7,
	[IRQ_DM355_TINT6]		= 7,
	[IRQ_CCINT0]			= 5,	/* dma */
	[IRQ_CCERRINT]			= 5,	/* dma */
	[IRQ_TCERRINT0]			= 5,	/* dma */
	[IRQ_TCERRINT]			= 5,	/* dma */
	[IRQ_DM355_SPINT2_1]		= 7,
	[IRQ_DM355_TINT7]		= 4,
	[IRQ_DM355_SDIOINT0]		= 7,
	[IRQ_MBXINT]			= 7,
	[IRQ_MBRINT]			= 7,
	[IRQ_MMCINT]			= 7,
	[IRQ_DM355_MMCINT1]		= 7,
	[IRQ_DM355_PWMINT3]		= 7,
	[IRQ_DDRINT]			= 7,
	[IRQ_AEMIFINT]			= 7,
	[IRQ_DM355_SDIOINT1]		= 4,
	[IRQ_TINT0_TINT12]		= 2,	/* clockevent */
	[IRQ_TINT0_TINT34]		= 2,	/* clocksource */
	[IRQ_TINT1_TINT12]		= 7,	/* DSP timer */
	[IRQ_TINT1_TINT34]		= 7,	/* system tick */
	[IRQ_PWMINT0]			= 7,
	[IRQ_PWMINT1]			= 7,
	[IRQ_PWMINT2]			= 7,
	[IRQ_I2C]			= 3,
	[IRQ_UARTINT0]			= 3,
	[IRQ_UARTINT1]			= 3,
	[IRQ_DM355_SPINT0_0]		= 3,
	[IRQ_DM355_SPINT0_1]		= 3,
	[IRQ_DM355_GPIO0]		= 3,
	[IRQ_DM355_GPIO1]		= 7,
	[IRQ_DM355_GPIO2]		= 4,
	[IRQ_DM355_GPIO3]		= 4,
	[IRQ_DM355_GPIO4]		= 7,
	[IRQ_DM355_GPIO5]		= 7,
	[IRQ_DM355_GPIO6]		= 7,
	[IRQ_DM355_GPIO7]		= 7,
	[IRQ_DM355_GPIO8]		= 7,
	[IRQ_DM355_GPIO9]		= 7,
	[IRQ_DM355_GPIOBNK0]		= 7,
	[IRQ_DM355_GPIOBNK1]		= 7,
	[IRQ_DM355_GPIOBNK2]		= 7,
	[IRQ_DM355_GPIOBNK3]		= 7,
	[IRQ_DM355_GPIOBNK4]		= 7,
	[IRQ_DM355_GPIOBNK5]		= 7,
	[IRQ_DM355_GPIOBNK6]		= 7,
	[IRQ_COMMTX]			= 7,
	[IRQ_COMMRX]			= 7,
	[IRQ_EMUINT]			= 7,
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm355_no_event[] = {
	12, 13, 24, 56, 57,
	58, 59, 60, 61, 62,
	63,
	-1
};

static struct edma_soc_info dm355_edma_info = {
	.n_channel	= 64,
	.n_region	= 4,
	.n_slot		= 128,
	.n_tc		= 2,
	.noevent	= dma_chan_dm355_no_event,
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using (or muxing) TC*_ERR */
};

static struct platform_device dm355_edma_device = {
	.name			= "edma",
	.id			= -1,
	.dev.platform_data	= &dm355_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

static struct map_desc dm355_io_desc[] = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= SRAM_VIRT,
		.pfn		= __phys_to_pfn(0x00010000),
		.length		= SZ_32K,
		/* MT_MEMORY_NONCACHED requires supersection alignment */
		.type		= MT_DEVICE,
	},
};

/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm355_ids[] = {
	{
		.variant	= 0x0,
		.part_no	= 0xb73b,
		.manufacturer	= 0x00f,
		.cpu_id		= DAVINCI_CPU_ID_DM355,
		.name		= "dm355",
	},
};

static void __iomem *dm355_psc_bases[] = {
	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};

/*
 * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 * T1_TOP: Timer 1, top   :  <unused>
 */
struct davinci_timer_info dm355_timer_info = {
	.timers		= davinci_timer_instance,
	.clockevent_id	= T0_BOT,
	.clocksource_id	= T0_TOP,
};

static struct plat_serial8250_port dm355_serial_platform_data[] = {
	{
		.mapbase	= DAVINCI_UART0_BASE,
		.irq		= IRQ_UARTINT0,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DAVINCI_UART1_BASE,
		.irq		= IRQ_UARTINT1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DM355_UART2_BASE,
		.irq		= IRQ_DM355_UARTINT2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.flags		= 0
	},
};

static struct platform_device dm355_serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= dm355_serial_platform_data,
	},
};

static struct davinci_soc_info davinci_soc_info_dm355 = {
	.io_desc		= dm355_io_desc,
	.io_desc_num		= ARRAY_SIZE(dm355_io_desc),
	.jtag_id_base		= IO_ADDRESS(0x01c40028),
	.ids			= dm355_ids,
	.ids_num		= ARRAY_SIZE(dm355_ids),
	.cpu_clks		= dm355_clks,
	.psc_bases		= dm355_psc_bases,
	.psc_bases_num		= ARRAY_SIZE(dm355_psc_bases),
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	.pinmux_pins		= dm355_pins,
	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
	.intc_irq_prios		= dm355_default_priorities,
	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
	.timer_info		= &dm355_timer_info,
	.wdt_base		= IO_ADDRESS(DAVINCI_WDOG_BASE),
	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
	.gpio_num		= 104,
	.gpio_irq		= IRQ_DM355_GPIOBNK0,
	.serial_dev		= &dm355_serial_device,
	.sram_dma		= 0x00010000,
	.sram_len		= SZ_32K,
};

void __init dm355_init(void)
{
	davinci_common_init(&davinci_soc_info_dm355);
}

static int __init dm355_init_devices(void)
{
	if (!cpu_is_davinci_dm355())
		return 0;

	davinci_cfg_reg(DM355_INT_EDMA_CC);
	platform_device_register(&dm355_edma_device);
	return 0;
}
postcore_initcall(dm355_init_devices);
Commit	Line	Data
95a3477f KH	1	/*
	2	* TI DaVinci DM355 chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
65e866a9	14	#include <linux/serial_8250.h>
95a3477f KH	15	#include <linux/platform_device.h>
95a3477f KH	16	#include <linux/dma-mapping.h>
a994955c	17	#include <linux/gpio.h>
95a3477f KH	18
	19	#include <linux/spi/spi.h>
	20
79c3c0b7 MG	21	#include <asm/mach/map.h>
79c3c0b7 MG	22
95a3477f KH	23	#include <mach/dm355.h>
	24	#include <mach/clock.h>
	25	#include <mach/cputype.h>
	26	#include <mach/edma.h>
	27	#include <mach/psc.h>
	28	#include <mach/mux.h>
	29	#include <mach/irqs.h>
f64691b3	30	#include <mach/time.h>
65e866a9	31	#include <mach/serial.h>
79c3c0b7	32	#include <mach/common.h>
95a3477f KH	33
	34	#include "clock.h"
	35	#include "mux.h"
	36
96ed299f KH	37	#define DM355_UART2_BASE (IO_PHYS + 0x206000)
96ed299f KH	38
95a3477f KH	39	/*
	40	* Device specific clocks
	41	*/
	42	#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
	43
	44	static struct pll_data pll1_data = {
	45	.num = 1,
	46	.phys_base = DAVINCI_PLL1_BASE,
	47	.flags = PLL_HAS_PREDIV \| PLL_HAS_POSTDIV,
	48	};
	49
	50	static struct pll_data pll2_data = {
	51	.num = 2,
	52	.phys_base = DAVINCI_PLL2_BASE,
	53	.flags = PLL_HAS_PREDIV,
	54	};
	55
	56	static struct clk ref_clk = {
	57	.name = "ref_clk",
	58	/* FIXME -- crystal rate is board-specific */
	59	.rate = DM355_REF_FREQ,
	60	};
	61
	62	static struct clk pll1_clk = {
	63	.name = "pll1",
	64	.parent = &ref_clk,
	65	.flags = CLK_PLL,
	66	.pll_data = &pll1_data,
	67	};
	68
	69	static struct clk pll1_aux_clk = {
	70	.name = "pll1_aux_clk",
	71	.parent = &pll1_clk,
	72	.flags = CLK_PLL \| PRE_PLL,
	73	};
	74
	75	static struct clk pll1_sysclk1 = {
	76	.name = "pll1_sysclk1",
	77	.parent = &pll1_clk,
	78	.flags = CLK_PLL,
	79	.div_reg = PLLDIV1,
	80	};
	81
	82	static struct clk pll1_sysclk2 = {
	83	.name = "pll1_sysclk2",
	84	.parent = &pll1_clk,
	85	.flags = CLK_PLL,
	86	.div_reg = PLLDIV2,
	87	};
	88
	89	static struct clk pll1_sysclk3 = {
	90	.name = "pll1_sysclk3",
	91	.parent = &pll1_clk,
	92	.flags = CLK_PLL,
	93	.div_reg = PLLDIV3,
	94	};
	95
	96	static struct clk pll1_sysclk4 = {
	97	.name = "pll1_sysclk4",
	98	.parent = &pll1_clk,
	99	.flags = CLK_PLL,
	100	.div_reg = PLLDIV4,
	101	};
	102
103	static struct clk pll1_sysclkbp = {
104	.name = "pll1_sysclkbp",
105	.parent = &pll1_clk,
106	.flags = CLK_PLL \| PRE_PLL,
107	.div_reg = BPDIV
108	};
109
110	static struct clk vpss_dac_clk = {
111	.name = "vpss_dac",
112	.parent = &pll1_sysclk3,
113	.lpsc = DM355_LPSC_VPSS_DAC,
114	};
115
116	static struct clk vpss_master_clk = {
117	.name = "vpss_master",
118	.parent = &pll1_sysclk4,
119	.lpsc = DAVINCI_LPSC_VPSSMSTR,
120	.flags = CLK_PSC,
121	};
122
123	static struct clk vpss_slave_clk = {
124	.name = "vpss_slave",
125	.parent = &pll1_sysclk4,
126	.lpsc = DAVINCI_LPSC_VPSSSLV,
127	};
128
129
130	static struct clk clkout1_clk = {
131	.name = "clkout1",
132	.parent = &pll1_aux_clk,
133	/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
134	};
135
136	static struct clk clkout2_clk = {
137	.name = "clkout2",
138	.parent = &pll1_sysclkbp,
139	};
140
141	static struct clk pll2_clk = {
142	.name = "pll2",
143	.parent = &ref_clk,
144	.flags = CLK_PLL,
145	.pll_data = &pll2_data,
146	};
147
148	static struct clk pll2_sysclk1 = {
149	.name = "pll2_sysclk1",
150	.parent = &pll2_clk,
151	.flags = CLK_PLL,
152	.div_reg = PLLDIV1,
153	};
154
155	static struct clk pll2_sysclkbp = {
156	.name = "pll2_sysclkbp",
157	.parent = &pll2_clk,
158	.flags = CLK_PLL \| PRE_PLL,
159	.div_reg = BPDIV
160	};
161
162	static struct clk clkout3_clk = {
163	.name = "clkout3",
164	.parent = &pll2_sysclkbp,
165	/* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
166	};
167
168	static struct clk arm_clk = {
169	.name = "arm_clk",
170	.parent = &pll1_sysclk1,
171	.lpsc = DAVINCI_LPSC_ARM,
172	.flags = ALWAYS_ENABLED,
173	};
174
175	/*
176	* NOT LISTED below, and not touched by Linux
177	* - in SyncReset state by default
178	* .lpsc = DAVINCI_LPSC_TPCC,
179	* .lpsc = DAVINCI_LPSC_TPTC0,
180	* .lpsc = DAVINCI_LPSC_TPTC1,
181	* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
182	* .lpsc = DAVINCI_LPSC_MEMSTICK,
183	* - in Enabled state by default
184	* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
185	* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
186	* .lpsc = DAVINCI_LPSC_SCR3, // "bus"
187	* .lpsc = DAVINCI_LPSC_SCR4, // "bus"
188	* .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
189	* .lpsc = DAVINCI_LPSC_CFG27, // "test"
190	* .lpsc = DAVINCI_LPSC_CFG3, // "test"
191	* .lpsc = DAVINCI_LPSC_CFG5, // "test"
192	*/
193
194	static struct clk mjcp_clk = {
195	.name = "mjcp",
196	.parent = &pll1_sysclk1,
197	.lpsc = DAVINCI_LPSC_IMCOP,
198	};
199
200	static struct clk uart0_clk = {
201	.name = "uart0",
202	.parent = &pll1_aux_clk,
203	.lpsc = DAVINCI_LPSC_UART0,
204	};
205
206	static struct clk uart1_clk = {
207	.name = "uart1",
208	.parent = &pll1_aux_clk,
209	.lpsc = DAVINCI_LPSC_UART1,
210	};
211
212	static struct clk uart2_clk = {
213	.name = "uart2",
214	.parent = &pll1_sysclk2,
215	.lpsc = DAVINCI_LPSC_UART2,
216	};
217
218	static struct clk i2c_clk = {
219	.name = "i2c",
220	.parent = &pll1_aux_clk,
221	.lpsc = DAVINCI_LPSC_I2C,
222	};
223
224	static struct clk asp0_clk = {
225	.name = "asp0",
226	.parent = &pll1_sysclk2,
227	.lpsc = DAVINCI_LPSC_McBSP,
228	};
229
230	static struct clk asp1_clk = {
231	.name = "asp1",
232	.parent = &pll1_sysclk2,
233	.lpsc = DM355_LPSC_McBSP1,
234	};
235
236	static struct clk mmcsd0_clk = {
237	.name = "mmcsd0",
238	.parent = &pll1_sysclk2,
239	.lpsc = DAVINCI_LPSC_MMC_SD,
240	};
241
242	static struct clk mmcsd1_clk = {
243	.name = "mmcsd1",
244	.parent = &pll1_sysclk2,
245	.lpsc = DM355_LPSC_MMC_SD1,
246	};
247
248	static struct clk spi0_clk = {
249	.name = "spi0",
250	.parent = &pll1_sysclk2,
251	.lpsc = DAVINCI_LPSC_SPI,
252	};
253
254	static struct clk spi1_clk = {
255	.name = "spi1",
256	.parent = &pll1_sysclk2,
257	.lpsc = DM355_LPSC_SPI1,
258	};
259
260	static struct clk spi2_clk = {
261	.name = "spi2",
262	.parent = &pll1_sysclk2,
263	.lpsc = DM355_LPSC_SPI2,
264	};
265
266	static struct clk gpio_clk = {
267	.name = "gpio",
268	.parent = &pll1_sysclk2,
269	.lpsc = DAVINCI_LPSC_GPIO,
270	};
271
272	static struct clk aemif_clk = {
273	.name = "aemif",
274	.parent = &pll1_sysclk2,
275	.lpsc = DAVINCI_LPSC_AEMIF,
276	};
277
278	static struct clk pwm0_clk = {
279	.name = "pwm0",
280	.parent = &pll1_aux_clk,
281	.lpsc = DAVINCI_LPSC_PWM0,
282	};
283
284	static struct clk pwm1_clk = {
285	.name = "pwm1",
286	.parent = &pll1_aux_clk,
287	.lpsc = DAVINCI_LPSC_PWM1,
288	};
289
290	static struct clk pwm2_clk = {
291	.name = "pwm2",
292	.parent = &pll1_aux_clk,
293	.lpsc = DAVINCI_LPSC_PWM2,
294	};
295
296	static struct clk pwm3_clk = {
297	.name = "pwm3",
298	.parent = &pll1_aux_clk,
299	.lpsc = DM355_LPSC_PWM3,
300	};
301
302	static struct clk timer0_clk = {
303	.name = "timer0",
304	.parent = &pll1_aux_clk,
305	.lpsc = DAVINCI_LPSC_TIMER0,
306	};
307
308	static struct clk timer1_clk = {
309	.name = "timer1",
310	.parent = &pll1_aux_clk,
311	.lpsc = DAVINCI_LPSC_TIMER1,
312	};
313
314	static struct clk timer2_clk = {
315	.name = "timer2",
316	.parent = &pll1_aux_clk,
317	.lpsc = DAVINCI_LPSC_TIMER2,
318	.usecount = 1, /* REVISIT: why cant' this be disabled? */
319	};
320
321	static struct clk timer3_clk = {
322	.name = "timer3",
323	.parent = &pll1_aux_clk,
324	.lpsc = DM355_LPSC_TIMER3,
325	};
326
327	static struct clk rto_clk = {
328	.name = "rto",
329	.parent = &pll1_aux_clk,
330	.lpsc = DM355_LPSC_RTO,
331	};
332
333	static struct clk usb_clk = {
334	.name = "usb",
335	.parent = &pll1_sysclk2,
336	.lpsc = DAVINCI_LPSC_USB,
337	};
338
339	static struct davinci_clk dm355_clks[] = {
340	CLK(NULL, "ref", &ref_clk),
341	CLK(NULL, "pll1", &pll1_clk),
342	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
343	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
344	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
345	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
346	CLK(NULL, "pll1_aux", &pll1_aux_clk),
347	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
348	CLK(NULL, "vpss_dac", &vpss_dac_clk),
349	CLK(NULL, "vpss_master", &vpss_master_clk),
350	CLK(NULL, "vpss_slave", &vpss_slave_clk),
351	CLK(NULL, "clkout1", &clkout1_clk),
352	CLK(NULL, "clkout2", &clkout2_clk),
353	CLK(NULL, "pll2", &pll2_clk),
354	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
355	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
356	CLK(NULL, "clkout3", &clkout3_clk),
357	CLK(NULL, "arm", &arm_clk),
358	CLK(NULL, "mjcp", &mjcp_clk),
359	CLK(NULL, "uart0", &uart0_clk),
360	CLK(NULL, "uart1", &uart1_clk),
361	CLK(NULL, "uart2", &uart2_clk),
362	CLK("i2c_davinci.1", NULL, &i2c_clk),
363	CLK("soc-audio.0", NULL, &asp0_clk),
364	CLK("soc-audio.1", NULL, &asp1_clk),
365	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
366	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
367	CLK(NULL, "spi0", &spi0_clk),
368	CLK(NULL, "spi1", &spi1_clk),
369	CLK(NULL, "spi2", &spi2_clk),
370	CLK(NULL, "gpio", &gpio_clk),
371	CLK(NULL, "aemif", &aemif_clk),
372	CLK(NULL, "pwm0", &pwm0_clk),
373	CLK(NULL, "pwm1", &pwm1_clk),
374	CLK(NULL, "pwm2", &pwm2_clk),
375	CLK(NULL, "pwm3", &pwm3_clk),
376	CLK(NULL, "timer0", &timer0_clk),
377	CLK(NULL, "timer1", &timer1_clk),
378	CLK("watchdog", NULL, &timer2_clk),
379	CLK(NULL, "timer3", &timer3_clk),
380	CLK(NULL, "rto", &rto_clk),
381	CLK(NULL, "usb", &usb_clk),
382	CLK(NULL, NULL, NULL),
383	};
384
385	/----------------------------------------------------------------------/
386
387	static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
388
389	static struct resource dm355_spi0_resources[] = {
390	{
391	.start = 0x01c66000,
392	.end = 0x01c667ff,
393	.flags = IORESOURCE_MEM,
394	},
395	{
396	.start = IRQ_DM355_SPINT0_1,
397	.flags = IORESOURCE_IRQ,
398	},
399	/* Not yet used, so not included:
400	* IORESOURCE_IRQ:
401	* - IRQ_DM355_SPINT0_0
402	* IORESOURCE_DMA:
403	* - DAVINCI_DMA_SPI_SPIX
404	* - DAVINCI_DMA_SPI_SPIR
405	*/
406	};
407
408	static struct platform_device dm355_spi0_device = {
409	.name = "spi_davinci",
410	.id = 0,
411	.dev = {
412	.dma_mask = &dm355_spi0_dma_mask,
413	.coherent_dma_mask = DMA_BIT_MASK(32),
414	},
415	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
416	.resource = dm355_spi0_resources,
417	};
418
419	void __init dm355_init_spi0(unsigned chipselect_mask,
420	struct spi_board_info *info, unsigned len)
421	{
422	/* for now, assume we need MISO */
423	davinci_cfg_reg(DM355_SPI0_SDI);
424
425	/* not all slaves will be wired up */
426	if (chipselect_mask & BIT(0))
427	davinci_cfg_reg(DM355_SPI0_SDENA0);
428	if (chipselect_mask & BIT(1))
429	davinci_cfg_reg(DM355_SPI0_SDENA1);
430
431	spi_register_board_info(info, len);
432
433	platform_device_register(&dm355_spi0_device);
434	}
435
436	/----------------------------------------------------------------------/
437
5570078c MG	438	#define PINMUX0 0x00
	439	#define PINMUX1 0x04
	440	#define PINMUX2 0x08
	441	#define PINMUX3 0x0c
	442	#define PINMUX4 0x10
	443	#define INTMUX 0x18
	444	#define EVTMUX 0x1c
	445
95a3477f KH	446	/*
	447	* Device specific mux setup
	448	*
	449	* soc description mux mode mode mux dbg
	450	* reg offset mask mode
	451	*/
	452	static const struct mux_config dm355_pins[] = {
0e585952	453	#ifdef CONFIG_DAVINCI_MUX
95a3477f KH	454	MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
	455
	456	MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
	457	MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
	458	MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
	459	MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
	460	MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
	461	MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
	462
	463	MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
	464	MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
	465
	466	MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
	467	MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
	468	MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
	469	MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
	470	MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
	471	MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
	472
	473	MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
	474	MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
	475	MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
	476
	477	INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
	478	INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
	479	INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
	480
	481	EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
	482	EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
	483	EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
0e585952	484	#endif
95a3477f KH	485	};
95a3477f KH	486
673dd36f MG	487	static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	488	[IRQ_DM355_CCDC_VDINT0] = 2,
	489	[IRQ_DM355_CCDC_VDINT1] = 6,
	490	[IRQ_DM355_CCDC_VDINT2] = 6,
	491	[IRQ_DM355_IPIPE_HST] = 6,
	492	[IRQ_DM355_H3AINT] = 6,
	493	[IRQ_DM355_IPIPE_SDR] = 6,
	494	[IRQ_DM355_IPIPEIFINT] = 6,
	495	[IRQ_DM355_OSDINT] = 7,
	496	[IRQ_DM355_VENCINT] = 6,
	497	[IRQ_ASQINT] = 6,
	498	[IRQ_IMXINT] = 6,
	499	[IRQ_USBINT] = 4,
	500	[IRQ_DM355_RTOINT] = 4,
	501	[IRQ_DM355_UARTINT2] = 7,
	502	[IRQ_DM355_TINT6] = 7,
	503	[IRQ_CCINT0] = 5, /* dma */
	504	[IRQ_CCERRINT] = 5, /* dma */
	505	[IRQ_TCERRINT0] = 5, /* dma */
	506	[IRQ_TCERRINT] = 5, /* dma */
	507	[IRQ_DM355_SPINT2_1] = 7,
	508	[IRQ_DM355_TINT7] = 4,
	509	[IRQ_DM355_SDIOINT0] = 7,
	510	[IRQ_MBXINT] = 7,
	511	[IRQ_MBRINT] = 7,
	512	[IRQ_MMCINT] = 7,
	513	[IRQ_DM355_MMCINT1] = 7,
	514	[IRQ_DM355_PWMINT3] = 7,
	515	[IRQ_DDRINT] = 7,
	516	[IRQ_AEMIFINT] = 7,
	517	[IRQ_DM355_SDIOINT1] = 4,
	518	[IRQ_TINT0_TINT12] = 2, /* clockevent */
	519	[IRQ_TINT0_TINT34] = 2, /* clocksource */
	520	[IRQ_TINT1_TINT12] = 7, /* DSP timer */
	521	[IRQ_TINT1_TINT34] = 7, /* system tick */
	522	[IRQ_PWMINT0] = 7,
	523	[IRQ_PWMINT1] = 7,
	524	[IRQ_PWMINT2] = 7,
	525	[IRQ_I2C] = 3,
	526	[IRQ_UARTINT0] = 3,
	527	[IRQ_UARTINT1] = 3,
	528	[IRQ_DM355_SPINT0_0] = 3,
	529	[IRQ_DM355_SPINT0_1] = 3,
	530	[IRQ_DM355_GPIO0] = 3,
	531	[IRQ_DM355_GPIO1] = 7,
	532	[IRQ_DM355_GPIO2] = 4,
	533	[IRQ_DM355_GPIO3] = 4,
	534	[IRQ_DM355_GPIO4] = 7,
	535	[IRQ_DM355_GPIO5] = 7,
	536	[IRQ_DM355_GPIO6] = 7,
	537	[IRQ_DM355_GPIO7] = 7,
	538	[IRQ_DM355_GPIO8] = 7,
	539	[IRQ_DM355_GPIO9] = 7,
	540	[IRQ_DM355_GPIOBNK0] = 7,
	541	[IRQ_DM355_GPIOBNK1] = 7,
	542	[IRQ_DM355_GPIOBNK2] = 7,
	543	[IRQ_DM355_GPIOBNK3] = 7,
	544	[IRQ_DM355_GPIOBNK4] = 7,
	545	[IRQ_DM355_GPIOBNK5] = 7,
	546	[IRQ_DM355_GPIOBNK6] = 7,
	547	[IRQ_COMMTX] = 7,
	548	[IRQ_COMMRX] = 7,
	549	[IRQ_EMUINT] = 7,
	550	};
551
95a3477f KH	552	/----------------------------------------------------------------------/
	553
	554	static const s8 dma_chan_dm355_no_event[] = {
	555	12, 13, 24, 56, 57,
	556	58, 59, 60, 61, 62,
	557	63,
	558	-1
	559	};
	560
	561	static struct edma_soc_info dm355_edma_info = {
	562	.n_channel = 64,
	563	.n_region = 4,
	564	.n_slot = 128,
	565	.n_tc = 2,
	566	.noevent = dma_chan_dm355_no_event,
	567	};
	568
	569	static struct resource edma_resources[] = {
	570	{
	571	.name = "edma_cc",
	572	.start = 0x01c00000,
	573	.end = 0x01c00000 + SZ_64K - 1,
	574	.flags = IORESOURCE_MEM,
	575	},
	576	{
	577	.name = "edma_tc0",
	578	.start = 0x01c10000,
	579	.end = 0x01c10000 + SZ_1K - 1,
	580	.flags = IORESOURCE_MEM,
	581	},
	582	{
	583	.name = "edma_tc1",
	584	.start = 0x01c10400,
	585	.end = 0x01c10400 + SZ_1K - 1,
	586	.flags = IORESOURCE_MEM,
	587	},
	588	{
	589	.start = IRQ_CCINT0,
	590	.flags = IORESOURCE_IRQ,
	591	},
	592	{
	593	.start = IRQ_CCERRINT,
	594	.flags = IORESOURCE_IRQ,
	595	},
	596	/* not using (or muxing) TC_ERR /
	597	};
	598
	599	static struct platform_device dm355_edma_device = {
	600	.name = "edma",
	601	.id = -1,
	602	.dev.platform_data = &dm355_edma_info,
	603	.num_resources = ARRAY_SIZE(edma_resources),
	604	.resource = edma_resources,
	605	};
	606
	607	/----------------------------------------------------------------------/
	608
79c3c0b7 MG	609	static struct map_desc dm355_io_desc[] = {
	610	{
	611	.virtual = IO_VIRT,
	612	.pfn = __phys_to_pfn(IO_PHYS),
	613	.length = IO_SIZE,
	614	.type = MT_DEVICE
	615	},
0d04eb47 DB	616	{
	617	.virtual = SRAM_VIRT,
	618	.pfn = __phys_to_pfn(0x00010000),
	619	.length = SZ_32K,
	620	/* MT_MEMORY_NONCACHED requires supersection alignment */
	621	.type = MT_DEVICE,
	622	},
79c3c0b7 MG	623	};
79c3c0b7 MG	624
b9ab1279 MG	625	/* Contents of JTAG ID register used to identify exact cpu type */
	626	static struct davinci_id dm355_ids[] = {
	627	{
	628	.variant = 0x0,
	629	.part_no = 0xb73b,
	630	.manufacturer = 0x00f,
	631	.cpu_id = DAVINCI_CPU_ID_DM355,
	632	.name = "dm355",
	633	},
	634	};
	635
d81d188c MG	636	static void __iomem *dm355_psc_bases[] = {
	637	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
	638	};
	639
f64691b3 MG	640	/*
	641	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
	642	* T0_TOP: Timer 0, top : clocksource for generic timekeeping
	643	* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
	644	* T1_TOP: Timer 1, top : <unused>
	645	*/
	646	struct davinci_timer_info dm355_timer_info = {
	647	.timers = davinci_timer_instance,
	648	.clockevent_id = T0_BOT,
	649	.clocksource_id = T0_TOP,
	650	};
	651
65e866a9 MG	652	static struct plat_serial8250_port dm355_serial_platform_data[] = {
	653	{
	654	.mapbase = DAVINCI_UART0_BASE,
	655	.irq = IRQ_UARTINT0,
	656	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	657	UPF_IOREMAP,
	658	.iotype = UPIO_MEM,
	659	.regshift = 2,
	660	},
	661	{
	662	.mapbase = DAVINCI_UART1_BASE,
	663	.irq = IRQ_UARTINT1,
	664	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	665	UPF_IOREMAP,
	666	.iotype = UPIO_MEM,
	667	.regshift = 2,
	668	},
	669	{
	670	.mapbase = DM355_UART2_BASE,
	671	.irq = IRQ_DM355_UARTINT2,
	672	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	673	UPF_IOREMAP,
	674	.iotype = UPIO_MEM,
	675	.regshift = 2,
	676	},
	677	{
	678	.flags = 0
	679	},
	680	};
	681
	682	static struct platform_device dm355_serial_device = {
	683	.name = "serial8250",
	684	.id = PLAT8250_DEV_PLATFORM,
	685	.dev = {
	686	.platform_data = dm355_serial_platform_data,
	687	},
	688	};
	689
79c3c0b7 MG	690	static struct davinci_soc_info davinci_soc_info_dm355 = {
	691	.io_desc = dm355_io_desc,
	692	.io_desc_num = ARRAY_SIZE(dm355_io_desc),
b9ab1279 MG	693	.jtag_id_base = IO_ADDRESS(0x01c40028),
	694	.ids = dm355_ids,
	695	.ids_num = ARRAY_SIZE(dm355_ids),
66e0c399	696	.cpu_clks = dm355_clks,
d81d188c MG	697	.psc_bases = dm355_psc_bases,
d81d188c MG	698	.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
0e585952 MG	699	.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	700	.pinmux_pins = dm355_pins,
	701	.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
673dd36f MG	702	.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	703	.intc_type = DAVINCI_INTC_TYPE_AINTC,
	704	.intc_irq_prios = dm355_default_priorities,
	705	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3	706	.timer_info = &dm355_timer_info,
951d6f6d	707	.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
a994955c MG	708	.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
	709	.gpio_num = 104,
	710	.gpio_irq = IRQ_DM355_GPIOBNK0,
65e866a9	711	.serial_dev = &dm355_serial_device,
0d04eb47 DB	712	.sram_dma = 0x00010000,
0d04eb47 DB	713	.sram_len = SZ_32K,
79c3c0b7 MG	714	};
79c3c0b7 MG	715
95a3477f KH	716	void __init dm355_init(void)
95a3477f KH	717	{
79c3c0b7	718	davinci_common_init(&davinci_soc_info_dm355);
95a3477f KH	719	}
	720
	721	static int __init dm355_init_devices(void)
	722	{
	723	if (!cpu_is_davinci_dm355())
	724	return 0;
	725
	726	davinci_cfg_reg(DM355_INT_EDMA_CC);
	727	platform_device_register(&dm355_edma_device);
	728	return 0;
	729	}
	730	postcore_initcall(dm355_init_devices);