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Commit | Line | Data |
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3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
20 | #include <linux/platform_device.h> | |
fced80c7 | 21 | #include <linux/io.h> |
d6a61563 | 22 | #include <linux/delay.h> |
3e062b07 | 23 | |
a09e64fb | 24 | #include <mach/hardware.h> |
3e062b07 | 25 | |
a09e64fb | 26 | #include <mach/psc.h> |
c5b736d0 | 27 | #include <mach/cputype.h> |
3e062b07 VB |
28 | #include "clock.h" |
29 | ||
3e062b07 VB |
30 | static LIST_HEAD(clocks); |
31 | static DEFINE_MUTEX(clocks_mutex); | |
32 | static DEFINE_SPINLOCK(clockfw_lock); | |
33 | ||
c5b736d0 | 34 | static unsigned psc_domain(struct clk *clk) |
3e062b07 | 35 | { |
c5b736d0 KH |
36 | return (clk->flags & PSC_DSP) |
37 | ? DAVINCI_GPSC_DSPDOMAIN | |
38 | : DAVINCI_GPSC_ARMDOMAIN; | |
3e062b07 | 39 | } |
3e062b07 | 40 | |
c5b736d0 | 41 | static void __clk_enable(struct clk *clk) |
3e062b07 | 42 | { |
c5b736d0 KH |
43 | if (clk->parent) |
44 | __clk_enable(clk->parent); | |
45 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | |
d81d188c MG |
46 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
47 | clk->lpsc, 1); | |
3e062b07 VB |
48 | } |
49 | ||
50 | static void __clk_disable(struct clk *clk) | |
51 | { | |
c5b736d0 | 52 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 53 | return; |
c5b736d0 | 54 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) |
d81d188c MG |
55 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
56 | clk->lpsc, 0); | |
c5b736d0 KH |
57 | if (clk->parent) |
58 | __clk_disable(clk->parent); | |
3e062b07 VB |
59 | } |
60 | ||
61 | int clk_enable(struct clk *clk) | |
62 | { | |
63 | unsigned long flags; | |
3e062b07 VB |
64 | |
65 | if (clk == NULL || IS_ERR(clk)) | |
66 | return -EINVAL; | |
67 | ||
c5b736d0 KH |
68 | spin_lock_irqsave(&clockfw_lock, flags); |
69 | __clk_enable(clk); | |
70 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 71 | |
c5b736d0 | 72 | return 0; |
3e062b07 VB |
73 | } |
74 | EXPORT_SYMBOL(clk_enable); | |
75 | ||
76 | void clk_disable(struct clk *clk) | |
77 | { | |
78 | unsigned long flags; | |
79 | ||
80 | if (clk == NULL || IS_ERR(clk)) | |
81 | return; | |
82 | ||
c5b736d0 KH |
83 | spin_lock_irqsave(&clockfw_lock, flags); |
84 | __clk_disable(clk); | |
85 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
86 | } |
87 | EXPORT_SYMBOL(clk_disable); | |
88 | ||
89 | unsigned long clk_get_rate(struct clk *clk) | |
90 | { | |
91 | if (clk == NULL || IS_ERR(clk)) | |
92 | return -EINVAL; | |
93 | ||
c5b736d0 | 94 | return clk->rate; |
3e062b07 VB |
95 | } |
96 | EXPORT_SYMBOL(clk_get_rate); | |
97 | ||
98 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
99 | { | |
100 | if (clk == NULL || IS_ERR(clk)) | |
101 | return -EINVAL; | |
102 | ||
d6a61563 SN |
103 | if (clk->round_rate) |
104 | return clk->round_rate(clk, rate); | |
105 | ||
c5b736d0 | 106 | return clk->rate; |
3e062b07 VB |
107 | } |
108 | EXPORT_SYMBOL(clk_round_rate); | |
109 | ||
d6a61563 SN |
110 | /* Propagate rate to children */ |
111 | static void propagate_rate(struct clk *root) | |
112 | { | |
113 | struct clk *clk; | |
114 | ||
115 | list_for_each_entry(clk, &root->children, childnode) { | |
116 | if (clk->recalc) | |
117 | clk->rate = clk->recalc(clk); | |
118 | propagate_rate(clk); | |
119 | } | |
120 | } | |
121 | ||
3e062b07 VB |
122 | int clk_set_rate(struct clk *clk, unsigned long rate) |
123 | { | |
d6a61563 SN |
124 | unsigned long flags; |
125 | int ret = -EINVAL; | |
126 | ||
3e062b07 | 127 | if (clk == NULL || IS_ERR(clk)) |
d6a61563 SN |
128 | return ret; |
129 | ||
130 | spin_lock_irqsave(&clockfw_lock, flags); | |
131 | if (clk->set_rate) | |
132 | ret = clk->set_rate(clk, rate); | |
133 | if (ret == 0) { | |
134 | if (clk->recalc) | |
135 | clk->rate = clk->recalc(clk); | |
136 | propagate_rate(clk); | |
137 | } | |
138 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 139 | |
d6a61563 | 140 | return ret; |
3e062b07 VB |
141 | } |
142 | EXPORT_SYMBOL(clk_set_rate); | |
143 | ||
144 | int clk_register(struct clk *clk) | |
145 | { | |
146 | if (clk == NULL || IS_ERR(clk)) | |
147 | return -EINVAL; | |
148 | ||
c5b736d0 KH |
149 | if (WARN(clk->parent && !clk->parent->rate, |
150 | "CLK: %s parent %s has no rate!\n", | |
151 | clk->name, clk->parent->name)) | |
152 | return -EINVAL; | |
153 | ||
f02bf3b3 SN |
154 | INIT_LIST_HEAD(&clk->children); |
155 | ||
3e062b07 | 156 | mutex_lock(&clocks_mutex); |
c5b736d0 | 157 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
158 | if (clk->parent) |
159 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
160 | mutex_unlock(&clocks_mutex); |
161 | ||
c5b736d0 KH |
162 | /* If rate is already set, use it */ |
163 | if (clk->rate) | |
164 | return 0; | |
165 | ||
de381a91 SN |
166 | /* Else, see if there is a way to calculate it */ |
167 | if (clk->recalc) | |
168 | clk->rate = clk->recalc(clk); | |
169 | ||
c5b736d0 | 170 | /* Otherwise, default to parent rate */ |
de381a91 | 171 | else if (clk->parent) |
c5b736d0 KH |
172 | clk->rate = clk->parent->rate; |
173 | ||
3e062b07 VB |
174 | return 0; |
175 | } | |
176 | EXPORT_SYMBOL(clk_register); | |
177 | ||
178 | void clk_unregister(struct clk *clk) | |
179 | { | |
180 | if (clk == NULL || IS_ERR(clk)) | |
181 | return; | |
182 | ||
183 | mutex_lock(&clocks_mutex); | |
184 | list_del(&clk->node); | |
f02bf3b3 | 185 | list_del(&clk->childnode); |
3e062b07 VB |
186 | mutex_unlock(&clocks_mutex); |
187 | } | |
188 | EXPORT_SYMBOL(clk_unregister); | |
189 | ||
c5b736d0 KH |
190 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
191 | /* | |
192 | * Disable any unused clocks left on by the bootloader | |
193 | */ | |
194 | static int __init clk_disable_unused(void) | |
195 | { | |
196 | struct clk *ck; | |
197 | ||
198 | spin_lock_irq(&clockfw_lock); | |
199 | list_for_each_entry(ck, &clocks, node) { | |
200 | if (ck->usecount > 0) | |
201 | continue; | |
202 | if (!(ck->flags & CLK_PSC)) | |
203 | continue; | |
204 | ||
205 | /* ignore if in Disabled or SwRstDisable states */ | |
d81d188c | 206 | if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) |
c5b736d0 KH |
207 | continue; |
208 | ||
209 | pr_info("Clocks: disable unused %s\n", ck->name); | |
d81d188c | 210 | davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); |
3e062b07 | 211 | } |
c5b736d0 KH |
212 | spin_unlock_irq(&clockfw_lock); |
213 | ||
214 | return 0; | |
215 | } | |
216 | late_initcall(clk_disable_unused); | |
217 | #endif | |
3e062b07 | 218 | |
de381a91 | 219 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 220 | { |
c5b736d0 KH |
221 | u32 v, plldiv; |
222 | struct pll_data *pll; | |
de381a91 | 223 | unsigned long rate = clk->rate; |
c5b736d0 KH |
224 | |
225 | /* If this is the PLL base clock, no more calculations needed */ | |
226 | if (clk->pll_data) | |
de381a91 | 227 | return rate; |
c5b736d0 KH |
228 | |
229 | if (WARN_ON(!clk->parent)) | |
de381a91 | 230 | return rate; |
c5b736d0 | 231 | |
de381a91 | 232 | rate = clk->parent->rate; |
c5b736d0 KH |
233 | |
234 | /* Otherwise, the parent must be a PLL */ | |
235 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 236 | return rate; |
c5b736d0 KH |
237 | |
238 | pll = clk->parent->pll_data; | |
239 | ||
240 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
241 | if (clk->flags & PRE_PLL) | |
de381a91 | 242 | rate = pll->input_rate; |
c5b736d0 KH |
243 | |
244 | if (!clk->div_reg) | |
de381a91 | 245 | return rate; |
c5b736d0 KH |
246 | |
247 | v = __raw_readl(pll->base + clk->div_reg); | |
248 | if (v & PLLDIV_EN) { | |
249 | plldiv = (v & PLLDIV_RATIO_MASK) + 1; | |
250 | if (plldiv) | |
de381a91 | 251 | rate /= plldiv; |
c5b736d0 | 252 | } |
de381a91 SN |
253 | |
254 | return rate; | |
255 | } | |
256 | ||
257 | static unsigned long clk_leafclk_recalc(struct clk *clk) | |
258 | { | |
259 | if (WARN_ON(!clk->parent)) | |
260 | return clk->rate; | |
261 | ||
262 | return clk->parent->rate; | |
c5b736d0 KH |
263 | } |
264 | ||
de381a91 | 265 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
266 | { |
267 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
268 | u8 bypass; | |
269 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 270 | unsigned long rate = clk->rate; |
c5b736d0 KH |
271 | |
272 | pll->base = IO_ADDRESS(pll->phys_base); | |
273 | ctrl = __raw_readl(pll->base + PLLCTL); | |
de381a91 | 274 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
275 | |
276 | if (ctrl & PLLCTL_PLLEN) { | |
277 | bypass = 0; | |
278 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
279 | if (cpu_is_davinci_dm365()) |
280 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
281 | else | |
282 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
283 | } else |
284 | bypass = 1; | |
285 | ||
286 | if (pll->flags & PLL_HAS_PREDIV) { | |
287 | prediv = __raw_readl(pll->base + PREDIV); | |
288 | if (prediv & PLLDIV_EN) | |
289 | prediv = (prediv & PLLDIV_RATIO_MASK) + 1; | |
290 | else | |
291 | prediv = 1; | |
292 | } | |
293 | ||
294 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
295 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
296 | prediv = 8; | |
297 | ||
298 | if (pll->flags & PLL_HAS_POSTDIV) { | |
299 | postdiv = __raw_readl(pll->base + POSTDIV); | |
300 | if (postdiv & PLLDIV_EN) | |
301 | postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; | |
302 | else | |
303 | postdiv = 1; | |
304 | } | |
305 | ||
306 | if (!bypass) { | |
de381a91 SN |
307 | rate /= prediv; |
308 | rate *= mult; | |
309 | rate /= postdiv; | |
c5b736d0 KH |
310 | } |
311 | ||
312 | pr_debug("PLL%d: input = %lu MHz [ ", | |
313 | pll->num, clk->parent->rate / 1000000); | |
314 | if (bypass) | |
315 | pr_debug("bypass "); | |
316 | if (prediv > 1) | |
317 | pr_debug("/ %d ", prediv); | |
318 | if (mult > 1) | |
319 | pr_debug("* %d ", mult); | |
320 | if (postdiv > 1) | |
321 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
322 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
323 | ||
324 | return rate; | |
c5b736d0 KH |
325 | } |
326 | ||
d6a61563 SN |
327 | /** |
328 | * davinci_set_pllrate - set the output rate of a given PLL. | |
329 | * | |
330 | * Note: Currently tested to work with OMAP-L138 only. | |
331 | * | |
332 | * @pll: pll whose rate needs to be changed. | |
333 | * @prediv: The pre divider value. Passing 0 disables the pre-divider. | |
334 | * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. | |
335 | * @postdiv: The post divider value. Passing 0 disables the post-divider. | |
336 | */ | |
337 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |
338 | unsigned int mult, unsigned int postdiv) | |
339 | { | |
340 | u32 ctrl; | |
341 | unsigned int locktime; | |
342 | ||
343 | if (pll->base == NULL) | |
344 | return -EINVAL; | |
345 | ||
346 | /* | |
347 | * PLL lock time required per OMAP-L138 datasheet is | |
348 | * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) | |
349 | * as 4 and OSCIN cycle as 25 MHz. | |
350 | */ | |
351 | if (prediv) { | |
352 | locktime = ((2000 * prediv) / 100); | |
353 | prediv = (prediv - 1) | PLLDIV_EN; | |
354 | } else { | |
355 | locktime = 20; | |
356 | } | |
357 | if (postdiv) | |
358 | postdiv = (postdiv - 1) | PLLDIV_EN; | |
359 | if (mult) | |
360 | mult = mult - 1; | |
361 | ||
362 | ctrl = __raw_readl(pll->base + PLLCTL); | |
363 | ||
364 | /* Switch the PLL to bypass mode */ | |
365 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
366 | __raw_writel(ctrl, pll->base + PLLCTL); | |
367 | ||
368 | /* | |
369 | * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched | |
370 | * to bypass mode. Delay of 1us ensures we are good for all > 4MHz | |
371 | * OSCIN/CLKIN inputs. Typically the input is ~25MHz. | |
372 | */ | |
373 | udelay(1); | |
374 | ||
375 | /* Reset and enable PLL */ | |
376 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
377 | __raw_writel(ctrl, pll->base + PLLCTL); | |
378 | ||
379 | if (pll->flags & PLL_HAS_PREDIV) | |
380 | __raw_writel(prediv, pll->base + PREDIV); | |
381 | ||
382 | __raw_writel(mult, pll->base + PLLM); | |
383 | ||
384 | if (pll->flags & PLL_HAS_POSTDIV) | |
385 | __raw_writel(postdiv, pll->base + POSTDIV); | |
386 | ||
387 | /* | |
388 | * Wait for PLL to reset properly, OMAP-L138 datasheet says | |
389 | * 'min' time = 125ns | |
390 | */ | |
391 | udelay(1); | |
392 | ||
393 | /* Bring PLL out of reset */ | |
394 | ctrl |= PLLCTL_PLLRST; | |
395 | __raw_writel(ctrl, pll->base + PLLCTL); | |
396 | ||
397 | udelay(locktime); | |
398 | ||
399 | /* Remove PLL from bypass mode */ | |
400 | ctrl |= PLLCTL_PLLEN; | |
401 | __raw_writel(ctrl, pll->base + PLLCTL); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | EXPORT_SYMBOL(davinci_set_pllrate); | |
406 | ||
c5b736d0 KH |
407 | int __init davinci_clk_init(struct davinci_clk *clocks) |
408 | { | |
409 | struct davinci_clk *c; | |
410 | struct clk *clk; | |
411 | ||
412 | for (c = clocks; c->lk.clk; c++) { | |
413 | clk = c->lk.clk; | |
414 | ||
de381a91 SN |
415 | if (!clk->recalc) { |
416 | ||
417 | /* Check if clock is a PLL */ | |
418 | if (clk->pll_data) | |
419 | clk->recalc = clk_pllclk_recalc; | |
420 | ||
421 | /* Else, if it is a PLL-derived clock */ | |
422 | else if (clk->flags & CLK_PLL) | |
423 | clk->recalc = clk_sysclk_recalc; | |
424 | ||
425 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
426 | else if (clk->parent) | |
427 | clk->recalc = clk_leafclk_recalc; | |
428 | } | |
c5b736d0 | 429 | |
de381a91 SN |
430 | if (clk->recalc) |
431 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
432 | |
433 | if (clk->lpsc) | |
434 | clk->flags |= CLK_PSC; | |
435 | ||
436 | clkdev_add(&c->lk); | |
437 | clk_register(clk); | |
438 | ||
439 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
440 | if (clk->flags & ALWAYS_ENABLED) | |
441 | clk_enable(clk); | |
3e062b07 VB |
442 | } |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | #ifdef CONFIG_PROC_FS | |
448 | #include <linux/proc_fs.h> | |
449 | #include <linux/seq_file.h> | |
450 | ||
451 | static void *davinci_ck_start(struct seq_file *m, loff_t *pos) | |
452 | { | |
453 | return *pos < 1 ? (void *)1 : NULL; | |
454 | } | |
455 | ||
456 | static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) | |
457 | { | |
458 | ++*pos; | |
459 | return NULL; | |
460 | } | |
461 | ||
462 | static void davinci_ck_stop(struct seq_file *m, void *v) | |
463 | { | |
464 | } | |
465 | ||
c5b736d0 KH |
466 | #define CLKNAME_MAX 10 /* longest clock name */ |
467 | #define NEST_DELTA 2 | |
468 | #define NEST_MAX 4 | |
469 | ||
470 | static void | |
471 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 472 | { |
c5b736d0 KH |
473 | char *state; |
474 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
475 | struct clk *clk; | |
476 | unsigned i; | |
477 | ||
478 | if (parent->flags & CLK_PLL) | |
479 | state = "pll"; | |
480 | else if (parent->flags & CLK_PSC) | |
481 | state = "psc"; | |
482 | else | |
483 | state = ""; | |
484 | ||
485 | /* <nest spaces> name <pad to end> */ | |
486 | memset(buf, ' ', sizeof(buf) - 1); | |
487 | buf[sizeof(buf) - 1] = 0; | |
488 | i = strlen(parent->name); | |
489 | memcpy(buf + nest, parent->name, | |
490 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
491 | ||
492 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
493 | buf, parent->usecount, state, clk_get_rate(parent)); | |
494 | /* REVISIT show device associations too */ | |
495 | ||
496 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
497 | list_for_each_entry(clk, &parent->children, childnode) { |
498 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
499 | } |
500 | } | |
3e062b07 | 501 | |
c5b736d0 KH |
502 | static int davinci_ck_show(struct seq_file *m, void *v) |
503 | { | |
504 | /* Show clock tree; we know the main oscillator is first. | |
505 | * We trust nonzero usecounts equate to PSC enables... | |
506 | */ | |
507 | mutex_lock(&clocks_mutex); | |
508 | if (!list_empty(&clocks)) | |
509 | dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); | |
510 | mutex_unlock(&clocks_mutex); | |
3e062b07 VB |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
2ffd6e18 | 515 | static const struct seq_operations davinci_ck_op = { |
3e062b07 VB |
516 | .start = davinci_ck_start, |
517 | .next = davinci_ck_next, | |
518 | .stop = davinci_ck_stop, | |
519 | .show = davinci_ck_show | |
520 | }; | |
521 | ||
522 | static int davinci_ck_open(struct inode *inode, struct file *file) | |
523 | { | |
524 | return seq_open(file, &davinci_ck_op); | |
525 | } | |
526 | ||
2ffd6e18 | 527 | static const struct file_operations proc_davinci_ck_operations = { |
3e062b07 VB |
528 | .open = davinci_ck_open, |
529 | .read = seq_read, | |
530 | .llseek = seq_lseek, | |
531 | .release = seq_release, | |
532 | }; | |
533 | ||
534 | static int __init davinci_ck_proc_init(void) | |
535 | { | |
40ad35d3 | 536 | proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations); |
3e062b07 VB |
537 | return 0; |
538 | ||
539 | } | |
540 | __initcall(davinci_ck_proc_init); | |
c5b736d0 | 541 | #endif /* CONFIG_DEBUG_PROC_FS */ |