[net-next-2.6.git] / arch / arm / mach-davinci / board-mityomapl138.c

/*
 * Critical Link MityOMAP-L138 SoM
 *
 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of
 * any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <mach/nand.h>
#include <mach/mux.h>

#define MITYOMAPL138_PHY_MASK		0x08 /* hardcoded for now */
#define MITYOMAPL138_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */

static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/* TPS65023 voltage regulator support */
/* 1.2V Core */
struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	{
		.supply = "cvdd",
	},
};

/* 1.8V */
struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	{
		.supply = "usb0_vdda18",
	},
	{
		.supply = "usb1_vdda18",
	},
	{
		.supply = "ddr_dvdd18",
	},
	{
		.supply = "sata_vddr",
	},
};

/* 1.2V */
struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	{
		.supply = "sata_vdd",
	},
	{
		.supply = "usb_cvdd",
	},
	{
		.supply = "pll0_vdda",
	},
	{
		.supply = "pll1_vdda",
	},
};

/* 1.8V Aux LDO, not used */
struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	{
		.supply = "1.8v_aux",
	},
};

/* FPGA VCC Aux (2.5 or 3.3) LDO */
struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	{
		.supply = "vccaux",
	},
};

struct regulator_init_data tps65023_regulator_data[] = {
	/* dcdc1 */
	{
		.constraints = {
			.min_uV = 1150000,
			.max_uV = 1350000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
		.consumer_supplies = tps65023_dcdc1_consumers,
	},
	/* dcdc2 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
		.consumer_supplies = tps65023_dcdc2_consumers,
	},
	/* dcdc3 */
	{
		.constraints = {
			.min_uV = 1200000,
			.max_uV = 1200000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
		.consumer_supplies = tps65023_dcdc3_consumers,
	},
	/* ldo1 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
		.consumer_supplies = tps65023_ldo1_consumers,
	},
	/* ldo2 */
	{
		.constraints = {
			.min_uV = 2500000,
			.max_uV = 3300000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
		.consumer_supplies = tps65023_ldo2_consumers,
	},
};

static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	{
		I2C_BOARD_INFO("tps65023", 0x48),
		.platform_data = &tps65023_regulator_data[0],
	},
	{
		I2C_BOARD_INFO("24c02", 0x50),
	},
};

static int __init pmic_tps65023_init(void)
{
	return i2c_register_board_info(1, mityomap_tps65023_info,
					ARRAY_SIZE(mityomap_tps65023_info));
}

/*
 * MityDSP-L138 includes a 256 MByte large-page NAND flash
 * (128K blocks).
 */
struct mtd_partition mityomapl138_nandflash_partition[] = {
	{
		.name		= "rootfs",
		.offset		= 0,
		.size		= SZ_128M,
		.mask_flags	= 0, /* MTD_WRITEABLE, */
	},
	{
		.name		= "homefs",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	},
};

static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	.parts		= mityomapl138_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(mityomapl138_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.options	= NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
	.ecc_bits	= 1, /* 4 bit mode is not supported with 16 bit NAND */
};

static struct resource mityomapl138_nandflash_resource[] = {
	{
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mityomapl138_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &mityomapl138_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(mityomapl138_nandflash_resource),
	.resource	= mityomapl138_nandflash_resource,
};

static struct platform_device *mityomapl138_devices[] __initdata = {
	&mityomapl138_nandflash_device,
};

static void __init mityomapl138_setup_nand(void)
{
	platform_add_devices(mityomapl138_devices,
				 ARRAY_SIZE(mityomapl138_devices));
}

static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	.enabled_uarts = 0x7,
};

static const short mityomap_mii_pins[] = {
	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static const short mityomap_rmii_pins[] = {
	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static void __init mityomapl138_config_emac(void)
{
	void __iomem *cfg_chip3_base;
	int ret;
	u32 val;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */

	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	val = __raw_readl(cfg_chip3_base);

	if (soc_info->emac_pdata->rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(mityomap_rmii_pins);
		pr_info("RMII PHY configured\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(mityomap_mii_pins);
		pr_info("MII PHY configured\n");
	}

	if (ret) {
		pr_warning("mii/rmii mux setup failed: %d\n", ret);
		return;
	}

	/* configure the CFGCHIP3 register for RMII or MII */
	__raw_writel(val, cfg_chip3_base);

	soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK;
	pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask);
	soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY;

	ret = da8xx_register_emac();
	if (ret)
		pr_warning("emac registration failed: %d\n", ret);
}

static struct davinci_pm_config da850_pm_pdata = {
	.sleepcount = 128,
};

static struct platform_device da850_pm_device = {
	.name	= "pm-davinci",
	.dev = {
		.platform_data  = &da850_pm_pdata,
	},
	.id	= -1,
};

static void __init mityomapl138_init(void)
{
	int ret;

	/* for now, no special EDMA channels are reserved */
	ret = da850_register_edma(NULL);
	if (ret)
		pr_warning("edma registration failed: %d\n", ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warning("watchdog registration failed: %d\n", ret);

	davinci_serial_init(&mityomapl138_uart_config);

	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	if (ret)
		pr_warning("i2c0 registration failed: %d\n", ret);

	ret = pmic_tps65023_init();
	if (ret)
		pr_warning("TPS65023 PMIC init failed: %d\n", ret);

	mityomapl138_setup_nand();

	mityomapl138_config_emac();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warning("rtc setup failed: %d\n", ret);

	ret = da850_register_cpufreq("pll0_sysclk3");
	if (ret)
		pr_warning("cpufreq registration failed: %d\n", ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warning("cpuidle registration failed: %d\n", ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warning("da850_evm_init: suspend registration failed: %d\n",
				ret);
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init mityomapl138_console_init(void)
{
	if (!machine_is_mityomapl138())
		return 0;

	return add_preferred_console("ttyS", 1, "115200");
}
console_initcall(mityomapl138_console_init);
#endif

static void __init mityomapl138_map_io(void)
{
	da850_init();
}

MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (DA8XX_DDR_BASE + 0x100),
	.map_io		= mityomapl138_map_io,
	.init_irq	= cp_intc_init,
	.timer		= &davinci_timer,
	.init_machine	= mityomapl138_init,
MACHINE_END
Commit	Line	Data
f2dbb6d9 MW	1	/*
	2	* Critical Link MityOMAP-L138 SoM
	3	*
	4	* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of
	8	* any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/console.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/mtd/partitions.h>
87748823 MW	16	#include <linux/regulator/machine.h>
87748823 MW	17	#include <linux/i2c.h>
f2dbb6d9 MW	18
	19	#include <asm/mach-types.h>
	20	#include <asm/mach/arch.h>
	21	#include <mach/common.h>
	22	#include <mach/cp_intc.h>
	23	#include <mach/da8xx.h>
	24	#include <mach/nand.h>
	25	#include <mach/mux.h>
	26
	27	#define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */
	28	#define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
	29
87748823 MW	30	static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	31	.bus_freq = 100, /* kHz */
	32	.bus_delay = 0, /* usec */
	33	};
	34
	35	/* TPS65023 voltage regulator support */
	36	/* 1.2V Core */
	37	struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	38	{
	39	.supply = "cvdd",
	40	},
	41	};
	42
	43	/* 1.8V */
	44	struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	45	{
	46	.supply = "usb0_vdda18",
	47	},
	48	{
	49	.supply = "usb1_vdda18",
	50	},
	51	{
	52	.supply = "ddr_dvdd18",
	53	},
	54	{
	55	.supply = "sata_vddr",
	56	},
	57	};
	58
	59	/* 1.2V */
	60	struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	61	{
	62	.supply = "sata_vdd",
	63	},
	64	{
	65	.supply = "usb_cvdd",
	66	},
	67	{
	68	.supply = "pll0_vdda",
	69	},
	70	{
	71	.supply = "pll1_vdda",
	72	},
	73	};
	74
	75	/* 1.8V Aux LDO, not used */
	76	struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	77	{
	78	.supply = "1.8v_aux",
	79	},
	80	};
	81
	82	/* FPGA VCC Aux (2.5 or 3.3) LDO */
	83	struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	84	{
	85	.supply = "vccaux",
	86	},
	87	};
	88
	89	struct regulator_init_data tps65023_regulator_data[] = {
	90	/* dcdc1 */
	91	{
	92	.constraints = {
	93	.min_uV = 1150000,
94	.max_uV = 1350000,
95	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
96	REGULATOR_CHANGE_STATUS,
97	.boot_on = 1,
98	},
99	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
100	.consumer_supplies = tps65023_dcdc1_consumers,
101	},
102	/* dcdc2 */
103	{
104	.constraints = {
105	.min_uV = 1800000,
106	.max_uV = 1800000,
107	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
108	.boot_on = 1,
109	},
110	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
111	.consumer_supplies = tps65023_dcdc2_consumers,
112	},
113	/* dcdc3 */
114	{
115	.constraints = {
116	.min_uV = 1200000,
117	.max_uV = 1200000,
118	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
119	.boot_on = 1,
120	},
121	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
122	.consumer_supplies = tps65023_dcdc3_consumers,
123	},
124	/* ldo1 */
125	{
126	.constraints = {
127	.min_uV = 1800000,
128	.max_uV = 1800000,
129	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
130	.boot_on = 1,
131	},
132	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
133	.consumer_supplies = tps65023_ldo1_consumers,
134	},
135	/* ldo2 */
136	{
137	.constraints = {
138	.min_uV = 2500000,
139	.max_uV = 3300000,
140	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
141	REGULATOR_CHANGE_STATUS,
142	.boot_on = 1,
143	},
144	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
145	.consumer_supplies = tps65023_ldo2_consumers,
146	},
147	};
148
149	static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
150	{
151	I2C_BOARD_INFO("tps65023", 0x48),
152	.platform_data = &tps65023_regulator_data[0],
153	},
154	{
155	I2C_BOARD_INFO("24c02", 0x50),
156	},
157	};
158
159	static int __init pmic_tps65023_init(void)
160	{
161	return i2c_register_board_info(1, mityomap_tps65023_info,
162	ARRAY_SIZE(mityomap_tps65023_info));
163	}
164
f2dbb6d9 MW	165	/*
	166	* MityDSP-L138 includes a 256 MByte large-page NAND flash
	167	* (128K blocks).
	168	*/
	169	struct mtd_partition mityomapl138_nandflash_partition[] = {
	170	{
	171	.name = "rootfs",
	172	.offset = 0,
	173	.size = SZ_128M,
	174	.mask_flags = 0, /* MTD_WRITEABLE, */
	175	},
	176	{
	177	.name = "homefs",
	178	.offset = MTDPART_OFS_APPEND,
	179	.size = MTDPART_SIZ_FULL,
	180	.mask_flags = 0,
	181	},
	182	};
	183
	184	static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	185	.parts = mityomapl138_nandflash_partition,
	186	.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
	187	.ecc_mode = NAND_ECC_HW,
	188	.options = NAND_USE_FLASH_BBT \| NAND_BUSWIDTH_16,
	189	.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
	190	};
	191
	192	static struct resource mityomapl138_nandflash_resource[] = {
	193	{
	194	.start = DA8XX_AEMIF_CS3_BASE,
	195	.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
	196	.flags = IORESOURCE_MEM,
	197	},
	198	{
	199	.start = DA8XX_AEMIF_CTL_BASE,
	200	.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
	201	.flags = IORESOURCE_MEM,
	202	},
	203	};
	204
	205	static struct platform_device mityomapl138_nandflash_device = {
	206	.name = "davinci_nand",
	207	.id = 0,
	208	.dev = {
	209	.platform_data = &mityomapl138_nandflash_data,
	210	},
	211	.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
	212	.resource = mityomapl138_nandflash_resource,
	213	};
	214
	215	static struct platform_device *mityomapl138_devices[] __initdata = {
	216	&mityomapl138_nandflash_device,
	217	};
	218
	219	static void __init mityomapl138_setup_nand(void)
	220	{
	221	platform_add_devices(mityomapl138_devices,
	222	ARRAY_SIZE(mityomapl138_devices));
	223	}
	224
	225	static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	226	.enabled_uarts = 0x7,
	227	};
	228
229	static const short mityomap_mii_pins[] = {
230	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
231	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
232	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
233	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
234	DA850_MDIO_D,
235	-1
236	};
237
238	static const short mityomap_rmii_pins[] = {
239	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
240	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
241	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
242	DA850_MDIO_D,
243	-1
244	};
245
246	static void __init mityomapl138_config_emac(void)
247	{
248	void __iomem *cfg_chip3_base;
249	int ret;
250	u32 val;
251	struct davinci_soc_info *soc_info = &davinci_soc_info;
252
253	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
254
255	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
256	val = __raw_readl(cfg_chip3_base);
257
258	if (soc_info->emac_pdata->rmii_en) {
259	val \|= BIT(8);
260	ret = davinci_cfg_reg_list(mityomap_rmii_pins);
261	pr_info("RMII PHY configured\n");
262	} else {
263	val &= ~BIT(8);
264	ret = davinci_cfg_reg_list(mityomap_mii_pins);
265	pr_info("MII PHY configured\n");
266	}
267
268	if (ret) {
269	pr_warning("mii/rmii mux setup failed: %d\n", ret);
270	return;
271	}
272
273	/* configure the CFGCHIP3 register for RMII or MII */
274	__raw_writel(val, cfg_chip3_base);
275
276	soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK;
277	pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask);
278	soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY;
279
280	ret = da8xx_register_emac();
281	if (ret)
282	pr_warning("emac registration failed: %d\n", ret);
283	}
284
285	static struct davinci_pm_config da850_pm_pdata = {
286	.sleepcount = 128,
287	};
288
289	static struct platform_device da850_pm_device = {
290	.name = "pm-davinci",
291	.dev = {
292	.platform_data = &da850_pm_pdata,
293	},
294	.id = -1,
295	};
296
297	static void __init mityomapl138_init(void)
298	{
299	int ret;
300
301	/* for now, no special EDMA channels are reserved */
302	ret = da850_register_edma(NULL);
303	if (ret)
304	pr_warning("edma registration failed: %d\n", ret);
305
306	ret = da8xx_register_watchdog();
307	if (ret)
308	pr_warning("watchdog registration failed: %d\n", ret);
309
310	davinci_serial_init(&mityomapl138_uart_config);
311
87748823 MW	312	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	313	if (ret)
	314	pr_warning("i2c0 registration failed: %d\n", ret);
	315
	316	ret = pmic_tps65023_init();
	317	if (ret)
	318	pr_warning("TPS65023 PMIC init failed: %d\n", ret);
	319
f2dbb6d9 MW	320	mityomapl138_setup_nand();
	321
	322	mityomapl138_config_emac();
	323
	324	ret = da8xx_register_rtc();
	325	if (ret)
	326	pr_warning("rtc setup failed: %d\n", ret);
	327
	328	ret = da850_register_cpufreq("pll0_sysclk3");
	329	if (ret)
	330	pr_warning("cpufreq registration failed: %d\n", ret);
	331
	332	ret = da8xx_register_cpuidle();
	333	if (ret)
	334	pr_warning("cpuidle registration failed: %d\n", ret);
	335
	336	ret = da850_register_pm(&da850_pm_device);
	337	if (ret)
	338	pr_warning("da850_evm_init: suspend registration failed: %d\n",
	339	ret);
	340	}
	341
	342	#ifdef CONFIG_SERIAL_8250_CONSOLE
	343	static int __init mityomapl138_console_init(void)
	344	{
	345	if (!machine_is_mityomapl138())
	346	return 0;
	347
	348	return add_preferred_console("ttyS", 1, "115200");
	349	}
	350	console_initcall(mityomapl138_console_init);
	351	#endif
	352
	353	static void __init mityomapl138_map_io(void)
	354	{
	355	da850_init();
	356	}
	357
	358	MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	359	.phys_io = IO_PHYS,
	360	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	361	.boot_params = (DA8XX_DDR_BASE + 0x100),
	362	.map_io = mityomapl138_map_io,
	363	.init_irq = cp_intc_init,
	364	.timer = &davinci_timer,
	365	.init_machine = mityomapl138_init,
	366	MACHINE_END