[net-next-2.6.git] / arch / arm / mach-davinci / board-dm365-evm.c

/*
 * TI DaVinci DM365 EVM board support
 *
 * Copyright (C) 2009 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/i2c/at24.h>
#include <linux/leds.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/mux.h>
#include <mach/hardware.h>
#include <mach/dm365.h>
#include <mach/psc.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/nand.h>


static inline int have_imager(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}

static inline int have_tvp7002(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}


#define DM365_ASYNC_EMIF_CONTROL_BASE	0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE	0x04000000

#define DM365_EVM_PHY_MASK		(0x2)
#define DM365_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */

/*
 * A MAX-II CPLD is used for various board control functions.
 */
#define CPLD_OFFSET(a13a8,a2a1)		(((a13a8) << 10) + ((a2a1) << 3))

#define CPLD_VERSION	CPLD_OFFSET(0,0)	/* r/o */
#define CPLD_TEST	CPLD_OFFSET(0,1)
#define CPLD_LEDS	CPLD_OFFSET(0,2)
#define CPLD_MUX	CPLD_OFFSET(0,3)
#define CPLD_SWITCH	CPLD_OFFSET(1,0)	/* r/o */
#define CPLD_POWER	CPLD_OFFSET(1,1)
#define CPLD_VIDEO	CPLD_OFFSET(1,2)
#define CPLD_CARDSTAT	CPLD_OFFSET(1,3)	/* r/o */

#define CPLD_DILC_OUT	CPLD_OFFSET(2,0)
#define CPLD_DILC_IN	CPLD_OFFSET(2,1)	/* r/o */

#define CPLD_IMG_DIR0	CPLD_OFFSET(2,2)
#define CPLD_IMG_MUX0	CPLD_OFFSET(2,3)
#define CPLD_IMG_MUX1	CPLD_OFFSET(3,0)
#define CPLD_IMG_DIR1	CPLD_OFFSET(3,1)
#define CPLD_IMG_MUX2	CPLD_OFFSET(3,2)
#define CPLD_IMG_MUX3	CPLD_OFFSET(3,3)
#define CPLD_IMG_DIR2	CPLD_OFFSET(4,0)
#define CPLD_IMG_MUX4	CPLD_OFFSET(4,1)
#define CPLD_IMG_MUX5	CPLD_OFFSET(4,2)

#define CPLD_RESETS	CPLD_OFFSET(4,3)

#define CPLD_CCD_DIR1	CPLD_OFFSET(0x3e,0)
#define CPLD_CCD_IO1	CPLD_OFFSET(0x3e,1)
#define CPLD_CCD_DIR2	CPLD_OFFSET(0x3e,2)
#define CPLD_CCD_IO2	CPLD_OFFSET(0x3e,3)
#define CPLD_CCD_DIR3	CPLD_OFFSET(0x3f,0)
#define CPLD_CCD_IO3	CPLD_OFFSET(0x3f,1)

static void __iomem *cpld;


/* NOTE:  this is geared for the standard config, with a socketed
 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 * swap chips with a different block size, partitioning will
 * need to be changed. This NAND chip MT29F16G08FAA is the default
 * NAND shipped with the Spectrum Digital DM365 EVM
 */
#define NAND_BLOCK_SIZE		SZ_128K

static struct mtd_partition davinci_nand_partitions[] = {
	{
		/* UBL (a few copies) plus U-Boot */
		.name		= "bootloader",
		.offset		= 0,
		.size		= 28 * NAND_BLOCK_SIZE,
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	}, {
		/* U-Boot environment */
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 2 * NAND_BLOCK_SIZE,
		.mask_flags	= 0,
	}, {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem1",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_512M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
	/* two blocks with bad block table (and mirror) at the end */
};

static struct davinci_nand_pdata davinci_nand_data = {
	.mask_chipsel		= BIT(14),
	.parts			= davinci_nand_partitions,
	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
	.ecc_mode		= NAND_ECC_HW,
	.options		= NAND_USE_FLASH_BBT,
};

static struct resource davinci_nand_resources[] = {
	{
		.start		= DM365_ASYNC_EMIF_DATA_CE0_BASE,
		.end		= DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DM365_ASYNC_EMIF_CONTROL_BASE,
		.end		= DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_nand_device = {
	.name			= "davinci_nand",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
	.resource		= davinci_nand_resources,
	.dev			= {
		.platform_data	= &davinci_nand_data,
	},
};

static struct at24_platform_data eeprom_info = {
	.byte_len       = (256*1024) / 8,
	.page_size      = 64,
	.flags          = AT24_FLAG_ADDR16,
	.setup          = davinci_get_mac_addr,
	.context	= (void *)0x7f00,
};

static struct i2c_board_info i2c_info[] = {
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.platform_data	= &eeprom_info,
	},
};

static struct davinci_i2c_platform_data i2c_pdata = {
	.bus_freq	= 400	/* kHz */,
	.bus_delay	= 0	/* usec */,
};

static int cpld_mmc_get_cd(int module)
{
	if (!cpld)
		return -ENXIO;

	/* low == card present */
	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
}

static int cpld_mmc_get_ro(int module)
{
	if (!cpld)
		return -ENXIO;

	/* high == card's write protect switch active */
	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
}

static struct davinci_mmc_config dm365evm_mmc_config = {
	.get_cd		= cpld_mmc_get_cd,
	.get_ro		= cpld_mmc_get_ro,
	.wires		= 4,
	.max_freq	= 50000000,
	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
	.version	= MMC_CTLR_VERSION_2,
};

static void dm365evm_emac_configure(void)
{
	/*
	 * EMAC pins are multiplexed with GPIO and UART
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	 */
	davinci_cfg_reg(DM365_EMAC_TX_EN);
	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	davinci_cfg_reg(DM365_EMAC_COL);
	davinci_cfg_reg(DM365_EMAC_TXD3);
	davinci_cfg_reg(DM365_EMAC_TXD2);
	davinci_cfg_reg(DM365_EMAC_TXD1);
	davinci_cfg_reg(DM365_EMAC_TXD0);
	davinci_cfg_reg(DM365_EMAC_RXD3);
	davinci_cfg_reg(DM365_EMAC_RXD2);
	davinci_cfg_reg(DM365_EMAC_RXD1);
	davinci_cfg_reg(DM365_EMAC_RXD0);
	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	davinci_cfg_reg(DM365_EMAC_RX_DV);
	davinci_cfg_reg(DM365_EMAC_RX_ER);
	davinci_cfg_reg(DM365_EMAC_CRS);
	davinci_cfg_reg(DM365_EMAC_MDIO);
	davinci_cfg_reg(DM365_EMAC_MDCLK);

	/*
	 * EMAC interrupts are multiplexed with GPIO interrupts
	 * Details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	 */
	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
}

static void dm365evm_mmc_configure(void)
{
	/*
	 * MMC/SD pins are multiplexed with GPIO and EMIF
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	 */
	davinci_cfg_reg(DM365_SD1_CLK);
	davinci_cfg_reg(DM365_SD1_CMD);
	davinci_cfg_reg(DM365_SD1_DATA3);
	davinci_cfg_reg(DM365_SD1_DATA2);
	davinci_cfg_reg(DM365_SD1_DATA1);
	davinci_cfg_reg(DM365_SD1_DATA0);
}

static void __init evm_init_i2c(void)
{
	davinci_init_i2c(&i2c_pdata);
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}

static struct platform_device *dm365_evm_nand_devices[] __initdata = {
	&davinci_nand_device,
};

static inline int have_leds(void)
{
#ifdef CONFIG_LEDS_CLASS
	return 1;
#else
	return 0;
#endif
}

struct cpld_led {
	struct led_classdev	cdev;
	u8			mask;
};

static const struct {
	const char *name;
	const char *trigger;
} cpld_leds[] = {
	{ "dm365evm::ds2", },
	{ "dm365evm::ds3", },
	{ "dm365evm::ds4", },
	{ "dm365evm::ds5", },
	{ "dm365evm::ds6", "nand-disk", },
	{ "dm365evm::ds7", "mmc1", },
	{ "dm365evm::ds8", "mmc0", },
	{ "dm365evm::ds9", "heartbeat", },
};

static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	if (b != LED_OFF)
		reg &= ~led->mask;
	else
		reg |= led->mask;
	__raw_writeb(reg, cpld + CPLD_LEDS);
}

static enum led_brightness cpld_led_get(struct led_classdev *cdev)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	return (reg & led->mask) ? LED_OFF : LED_FULL;
}

static int __init cpld_leds_init(void)
{
	int	i;

	if (!have_leds() ||  !cpld)
		return 0;

	/* setup LEDs */
	__raw_writeb(0xff, cpld + CPLD_LEDS);
	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
		struct cpld_led *led;

		led = kzalloc(sizeof(*led), GFP_KERNEL);
		if (!led)
			break;

		led->cdev.name = cpld_leds[i].name;
		led->cdev.brightness_set = cpld_led_set;
		led->cdev.brightness_get = cpld_led_get;
		led->cdev.default_trigger = cpld_leds[i].trigger;
		led->mask = BIT(i);

		if (led_classdev_register(NULL, &led->cdev) < 0) {
			kfree(led);
			break;
		}
	}

	return 0;
}
/* run after subsys_initcall() for LEDs */
fs_initcall(cpld_leds_init);


static void __init evm_init_cpld(void)
{
	u8 mux, resets;
	const char *label;
	struct clk *aemif_clk;

	/* Make sure we can configure the CPLD through CS1.  Then
	 * leave it on for later access to MMC and LED registers.
	 */
	aemif_clk = clk_get(NULL, "aemif");
	if (IS_ERR(aemif_clk))
		return;
	clk_enable(aemif_clk);

	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
			"cpld") == NULL)
		goto fail;
	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
	if (!cpld) {
		release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
				SECTION_SIZE);
fail:
		pr_err("ERROR: can't map CPLD\n");
		clk_disable(aemif_clk);
		return;
	}

	/* External muxing for some signals */
	mux = 0;

	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
	 * NOTE:  SW4 bus width setting must match!
	 */
	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
		/* external keypad mux */
		mux |= BIT(7);

		platform_add_devices(dm365_evm_nand_devices,
				ARRAY_SIZE(dm365_evm_nand_devices));
	} else {
		/* no OneNAND support yet */
	}

	/* Leave external chips in reset when unused. */
	resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);

	/* Static video input config with SN74CBT16214 1-of-3 mux:
	 *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
	 *  - port b2 == imager (mux lowbits == 2 or 7)
	 *  - port b3 == tvp5146 (mux lowbits == 5)
	 *
	 * Runtime switching could work too, with limitations.
	 */
	if (have_imager()) {
		label = "HD imager";
		mux |= 1;

		/* externally mux MMC1/ENET/AIC33 to imager */
		mux |= BIT(6) | BIT(5) | BIT(3);
	} else {
		struct davinci_soc_info *soc_info = &davinci_soc_info;

		/* we can use MMC1 ... */
		dm365evm_mmc_configure();
		davinci_setup_mmc(1, &dm365evm_mmc_config);

		/* ... and ENET ... */
		dm365evm_emac_configure();
		soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
		soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
		resets &= ~BIT(3);

		/* ... and AIC33 */
		resets &= ~BIT(1);

		if (have_tvp7002()) {
			mux |= 2;
			resets &= ~BIT(2);
			label = "tvp7002 HD";
		} else {
			/* default to tvp5146 */
			mux |= 5;
			resets &= ~BIT(0);
			label = "tvp5146 SD";
		}
	}
	__raw_writeb(mux, cpld + CPLD_MUX);
	__raw_writeb(resets, cpld + CPLD_RESETS);
	pr_info("EVM: %s video input\n", label);

	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
}

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

static void __init dm365_evm_map_io(void)
{
	dm365_init();
}

static __init void dm365_evm_init(void)
{
	evm_init_i2c();
	davinci_serial_init(&uart_config);

	dm365evm_emac_configure();
	dm365evm_mmc_configure();

	davinci_setup_mmc(0, &dm365evm_mmc_config);

	/* maybe setup mmc1/etc ... _after_ mmc0 */
	evm_init_cpld();
}

static __init void dm365_evm_irq_init(void)
{
	davinci_irq_init();
}

MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (0x80000100),
	.map_io		= dm365_evm_map_io,
	.init_irq	= dm365_evm_irq_init,
	.timer		= &davinci_timer,
	.init_machine	= dm365_evm_init,
MACHINE_END
Commit	Line	Data
37dd0095 SP	1	/*
	2	* TI DaVinci DM365 EVM board support
	3	*
	4	* Copyright (C) 2009 Texas Instruments Incorporated
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/init.h>
	18	#include <linux/dma-mapping.h>
	19	#include <linux/i2c.h>
	20	#include <linux/io.h>
	21	#include <linux/clk.h>
8ed0a9d4	22	#include <linux/i2c/at24.h>
ff255c6c	23	#include <linux/leds.h>
37b798da SP	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
	26	#include <linux/mtd/nand.h>
37dd0095 SP	27	#include <asm/setup.h>
	28	#include <asm/mach-types.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/map.h>
8ed0a9d4	31	#include <mach/mux.h>
37dd0095 SP	32	#include <mach/hardware.h>
	33	#include <mach/dm365.h>
	34	#include <mach/psc.h>
	35	#include <mach/common.h>
	36	#include <mach/i2c.h>
37dd0095 SP	37	#include <mach/serial.h>
37dd0095 SP	38	#include <mach/common.h>
a45c8ba3	39	#include <mach/mmc.h>
37b798da SP	40	#include <mach/nand.h>
37b798da SP	41
ff255c6c DB	42
	43	static inline int have_imager(void)
	44	{
	45	/* REVISIT when it's supported, trigger via Kconfig */
	46	return 0;
	47	}
	48
	49	static inline int have_tvp7002(void)
	50	{
	51	/* REVISIT when it's supported, trigger via Kconfig */
	52	return 0;
	53	}
	54
	55
37b798da SP	56	#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
37b798da SP	57	#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
ff255c6c	58	#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
37dd0095	59
8ed0a9d4 SP	60	#define DM365_EVM_PHY_MASK (0x2)
	61	#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
	62
ff255c6c DB	63	/*
	64	* A MAX-II CPLD is used for various board control functions.
	65	*/
	66	#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
	67
	68	#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
	69	#define CPLD_TEST CPLD_OFFSET(0,1)
	70	#define CPLD_LEDS CPLD_OFFSET(0,2)
	71	#define CPLD_MUX CPLD_OFFSET(0,3)
	72	#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
	73	#define CPLD_POWER CPLD_OFFSET(1,1)
	74	#define CPLD_VIDEO CPLD_OFFSET(1,2)
	75	#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
	76
	77	#define CPLD_DILC_OUT CPLD_OFFSET(2,0)
	78	#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
	79
	80	#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
	81	#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
	82	#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
	83	#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
	84	#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
	85	#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
	86	#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
	87	#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
	88	#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
	89
	90	#define CPLD_RESETS CPLD_OFFSET(4,3)
	91
	92	#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
	93	#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
	94	#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
	95	#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
	96	#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
	97	#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
	98
	99	static void __iomem *cpld;
	100
	101
37b798da SP	102	/* NOTE: this is geared for the standard config, with a socketed
	103	* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
	104	* swap chips with a different block size, partitioning will
	105	* need to be changed. This NAND chip MT29F16G08FAA is the default
	106	* NAND shipped with the Spectrum Digital DM365 EVM
	107	*/
	108	#define NAND_BLOCK_SIZE SZ_128K
	109
	110	static struct mtd_partition davinci_nand_partitions[] = {
	111	{
	112	/* UBL (a few copies) plus U-Boot */
	113	.name = "bootloader",
	114	.offset = 0,
	115	.size = 28 * NAND_BLOCK_SIZE,
	116	.mask_flags = MTD_WRITEABLE, /* force read-only */
	117	}, {
	118	/* U-Boot environment */
	119	.name = "params",
	120	.offset = MTDPART_OFS_APPEND,
	121	.size = 2 * NAND_BLOCK_SIZE,
	122	.mask_flags = 0,
	123	}, {
	124	.name = "kernel",
	125	.offset = MTDPART_OFS_APPEND,
	126	.size = SZ_4M,
	127	.mask_flags = 0,
	128	}, {
	129	.name = "filesystem1",
	130	.offset = MTDPART_OFS_APPEND,
	131	.size = SZ_512M,
	132	.mask_flags = 0,
	133	}, {
	134	.name = "filesystem2",
	135	.offset = MTDPART_OFS_APPEND,
	136	.size = MTDPART_SIZ_FULL,
	137	.mask_flags = 0,
	138	}
	139	/* two blocks with bad block table (and mirror) at the end */
	140	};
	141
	142	static struct davinci_nand_pdata davinci_nand_data = {
	143	.mask_chipsel = BIT(14),
	144	.parts = davinci_nand_partitions,
	145	.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
	146	.ecc_mode = NAND_ECC_HW,
	147	.options = NAND_USE_FLASH_BBT,
	148	};
	149
	150	static struct resource davinci_nand_resources[] = {
	151	{
	152	.start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
	153	.end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
	154	.flags = IORESOURCE_MEM,
	155	}, {
	156	.start = DM365_ASYNC_EMIF_CONTROL_BASE,
	157	.end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
	158	.flags = IORESOURCE_MEM,
	159	},
	160	};
	161
	162	static struct platform_device davinci_nand_device = {
	163	.name = "davinci_nand",
	164	.id = 0,
	165	.num_resources = ARRAY_SIZE(davinci_nand_resources),
166	.resource = davinci_nand_resources,
167	.dev = {
168	.platform_data = &davinci_nand_data,
169	},
170	};
171
8ed0a9d4 SP	172	static struct at24_platform_data eeprom_info = {
	173	.byte_len = (256*1024) / 8,
	174	.page_size = 64,
	175	.flags = AT24_FLAG_ADDR16,
	176	.setup = davinci_get_mac_addr,
	177	.context = (void *)0x7f00,
	178	};
	179
	180	static struct i2c_board_info i2c_info[] = {
	181	{
	182	I2C_BOARD_INFO("24c256", 0x50),
	183	.platform_data = &eeprom_info,
	184	},
	185	};
	186
37dd0095 SP	187	static struct davinci_i2c_platform_data i2c_pdata = {
	188	.bus_freq = 400 /* kHz */,
	189	.bus_delay = 0 /* usec */,
	190	};
	191
ff255c6c DB	192	static int cpld_mmc_get_cd(int module)
	193	{
	194	if (!cpld)
	195	return -ENXIO;
	196
	197	/* low == card present */
	198	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
	199	}
	200
	201	static int cpld_mmc_get_ro(int module)
	202	{
	203	if (!cpld)
	204	return -ENXIO;
	205
	206	/* high == card's write protect switch active */
	207	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
	208	}
	209
a45c8ba3	210	static struct davinci_mmc_config dm365evm_mmc_config = {
ff255c6c DB	211	.get_cd = cpld_mmc_get_cd,
ff255c6c DB	212	.get_ro = cpld_mmc_get_ro,
a45c8ba3 SP	213	.wires = 4,
	214	.max_freq = 50000000,
	215	.caps = MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED,
	216	.version = MMC_CTLR_VERSION_2,
	217	};
	218
8ed0a9d4 SP	219	static void dm365evm_emac_configure(void)
	220	{
	221	/*
	222	* EMAC pins are multiplexed with GPIO and UART
	223	* Further details are available at the DM365 ARM
	224	* Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	225	*/
	226	davinci_cfg_reg(DM365_EMAC_TX_EN);
	227	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	228	davinci_cfg_reg(DM365_EMAC_COL);
	229	davinci_cfg_reg(DM365_EMAC_TXD3);
	230	davinci_cfg_reg(DM365_EMAC_TXD2);
	231	davinci_cfg_reg(DM365_EMAC_TXD1);
	232	davinci_cfg_reg(DM365_EMAC_TXD0);
	233	davinci_cfg_reg(DM365_EMAC_RXD3);
	234	davinci_cfg_reg(DM365_EMAC_RXD2);
	235	davinci_cfg_reg(DM365_EMAC_RXD1);
	236	davinci_cfg_reg(DM365_EMAC_RXD0);
	237	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	238	davinci_cfg_reg(DM365_EMAC_RX_DV);
	239	davinci_cfg_reg(DM365_EMAC_RX_ER);
	240	davinci_cfg_reg(DM365_EMAC_CRS);
	241	davinci_cfg_reg(DM365_EMAC_MDIO);
	242	davinci_cfg_reg(DM365_EMAC_MDCLK);
	243
	244	/*
	245	* EMAC interrupts are multiplexed with GPIO interrupts
	246	* Details are available at the DM365 ARM
	247	* Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	248	*/
	249	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	250	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	251	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	252	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
	253	}
	254
a45c8ba3 SP	255	static void dm365evm_mmc_configure(void)
	256	{
	257	/*
	258	* MMC/SD pins are multiplexed with GPIO and EMIF
	259	* Further details are available at the DM365 ARM
	260	* Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	261	*/
	262	davinci_cfg_reg(DM365_SD1_CLK);
	263	davinci_cfg_reg(DM365_SD1_CMD);
	264	davinci_cfg_reg(DM365_SD1_DATA3);
	265	davinci_cfg_reg(DM365_SD1_DATA2);
	266	davinci_cfg_reg(DM365_SD1_DATA1);
	267	davinci_cfg_reg(DM365_SD1_DATA0);
	268	}
	269
37dd0095 SP	270	static void __init evm_init_i2c(void)
	271	{
	272	davinci_init_i2c(&i2c_pdata);
8ed0a9d4	273	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
37dd0095 SP	274	}
37dd0095 SP	275
ff255c6c	276	static struct platform_device *dm365_evm_nand_devices[] __initdata = {
37b798da SP	277	&davinci_nand_device,
	278	};
	279
ff255c6c DB	280	static inline int have_leds(void)
	281	{
	282	#ifdef CONFIG_LEDS_CLASS
	283	return 1;
	284	#else
	285	return 0;
	286	#endif
	287	}
	288
	289	struct cpld_led {
	290	struct led_classdev cdev;
	291	u8 mask;
	292	};
	293
	294	static const struct {
	295	const char *name;
	296	const char *trigger;
	297	} cpld_leds[] = {
	298	{ "dm365evm::ds2", },
	299	{ "dm365evm::ds3", },
	300	{ "dm365evm::ds4", },
	301	{ "dm365evm::ds5", },
	302	{ "dm365evm::ds6", "nand-disk", },
	303	{ "dm365evm::ds7", "mmc1", },
	304	{ "dm365evm::ds8", "mmc0", },
	305	{ "dm365evm::ds9", "heartbeat", },
	306	};
	307
	308	static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
	309	{
	310	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	311	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	312
	313	if (b != LED_OFF)
	314	reg &= ~led->mask;
	315	else
	316	reg \|= led->mask;
	317	__raw_writeb(reg, cpld + CPLD_LEDS);
	318	}
	319
	320	static enum led_brightness cpld_led_get(struct led_classdev *cdev)
	321	{
	322	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	323	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	324
	325	return (reg & led->mask) ? LED_OFF : LED_FULL;
	326	}
	327
	328	static int __init cpld_leds_init(void)
	329	{
	330	int i;
	331
	332	if (!have_leds() \|\| !cpld)
	333	return 0;
	334
	335	/* setup LEDs */
	336	__raw_writeb(0xff, cpld + CPLD_LEDS);
	337	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
	338	struct cpld_led *led;
	339
	340	led = kzalloc(sizeof(*led), GFP_KERNEL);
	341	if (!led)
	342	break;
	343
344	led->cdev.name = cpld_leds[i].name;
345	led->cdev.brightness_set = cpld_led_set;
346	led->cdev.brightness_get = cpld_led_get;
347	led->cdev.default_trigger = cpld_leds[i].trigger;
348	led->mask = BIT(i);
349
350	if (led_classdev_register(NULL, &led->cdev) < 0) {
351	kfree(led);
352	break;
353	}
354	}
355
356	return 0;
357	}
358	/* run after subsys_initcall() for LEDs */
359	fs_initcall(cpld_leds_init);
360
361
362	static void __init evm_init_cpld(void)
363	{
364	u8 mux, resets;
365	const char *label;
366	struct clk *aemif_clk;
367
368	/* Make sure we can configure the CPLD through CS1. Then
369	* leave it on for later access to MMC and LED registers.
370	*/
371	aemif_clk = clk_get(NULL, "aemif");
372	if (IS_ERR(aemif_clk))
373	return;
374	clk_enable(aemif_clk);
375
376	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
377	"cpld") == NULL)
378	goto fail;
379	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
380	if (!cpld) {
381	release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
382	SECTION_SIZE);
383	fail:
384	pr_err("ERROR: can't map CPLD\n");
385	clk_disable(aemif_clk);
386	return;
387	}
388
389	/* External muxing for some signals */
390	mux = 0;
391
392	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
393	* NOTE: SW4 bus width setting must match!
394	*/
395	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
396	/* external keypad mux */
397	mux \|= BIT(7);
398
399	platform_add_devices(dm365_evm_nand_devices,
400	ARRAY_SIZE(dm365_evm_nand_devices));
401	} else {
402	/* no OneNAND support yet */
403	}
404
405	/* Leave external chips in reset when unused. */
406	resets = BIT(3) \| BIT(2) \| BIT(1) \| BIT(0);
407
408	/* Static video input config with SN74CBT16214 1-of-3 mux:
409	* - port b1 == tvp7002 (mux lowbits == 1 or 6)
410	* - port b2 == imager (mux lowbits == 2 or 7)
411	* - port b3 == tvp5146 (mux lowbits == 5)
412	*
413	* Runtime switching could work too, with limitations.
414	*/
415	if (have_imager()) {
416	label = "HD imager";
417	mux \|= 1;
418
419	/* externally mux MMC1/ENET/AIC33 to imager */
420	mux \|= BIT(6) \| BIT(5) \| BIT(3);
421	} else {
422	struct davinci_soc_info *soc_info = &davinci_soc_info;
423
424	/* we can use MMC1 ... */
425	dm365evm_mmc_configure();
426	davinci_setup_mmc(1, &dm365evm_mmc_config);
427
428	/* ... and ENET ... */
429	dm365evm_emac_configure();
430	soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
431	soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
432	resets &= ~BIT(3);
433
434	/* ... and AIC33 */
435	resets &= ~BIT(1);
436
437	if (have_tvp7002()) {
438	mux \|= 2;
439	resets &= ~BIT(2);
440	label = "tvp7002 HD";
441	} else {
442	/* default to tvp5146 */
443	mux \|= 5;
444	resets &= ~BIT(0);
445	label = "tvp5146 SD";
446	}
447	}
448	__raw_writeb(mux, cpld + CPLD_MUX);
449	__raw_writeb(resets, cpld + CPLD_RESETS);
450	pr_info("EVM: %s video input\n", label);
451
452	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
453	}
454
37dd0095 SP	455	static struct davinci_uart_config uart_config __initdata = {
	456	.enabled_uarts = (1 << 0),
	457	};
	458
	459	static void __init dm365_evm_map_io(void)
	460	{
	461	dm365_init();
	462	}
	463
	464	static __init void dm365_evm_init(void)
	465	{
	466	evm_init_i2c();
	467	davinci_serial_init(&uart_config);
8ed0a9d4 SP	468
8ed0a9d4 SP	469	dm365evm_emac_configure();
a45c8ba3 SP	470	dm365evm_mmc_configure();
	471
	472	davinci_setup_mmc(0, &dm365evm_mmc_config);
8ed0a9d4	473
ff255c6c DB	474	/* maybe setup mmc1/etc ... _after_ mmc0 */
ff255c6c DB	475	evm_init_cpld();
37dd0095 SP	476	}
	477
	478	static __init void dm365_evm_irq_init(void)
	479	{
	480	davinci_irq_init();
	481	}
	482
	483	MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	484	.phys_io = IO_PHYS,
	485	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	486	.boot_params = (0x80000100),
	487	.map_io = dm365_evm_map_io,
	488	.init_irq = dm365_evm_irq_init,
	489	.timer = &davinci_timer,
	490	.init_machine = dm365_evm_init,
	491	MACHINE_END
	492