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CommitLineData
0fbc5592
SR		 1/*
2 * TI DA850/OMAP-L138 EVM board
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7 * Original Copyrights follow:
8 *
9 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/kernel.h>
0fbc5592
SR		 15#include <linux/init.h>
16#include <linux/console.h>
17#include <linux/i2c.h>
18#include <linux/i2c/at24.h>
75e2ea64 19#include <linux/i2c/pca953x.h>
0bc20bba 20#include <linux/mfd/tps6507x.h>
5cbdf276 21#include <linux/gpio.h>
38beb929
SR		 22#include <linux/platform_device.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h>
7c5ec609 26#include <linux/mtd/physmap.h>
a9eb1f67 27#include <linux/regulator/machine.h>
8b24599e 28#include <linux/regulator/tps6507x.h>
da1e3680 29#include <linux/input/tps6507x-ts.h>
0fbc5592
SR		 30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33
0fbc5592
SR		 34#include <mach/cp_intc.h>
35#include <mach/da8xx.h>
38beb929 36#include <mach/nand.h>
7761ef67 37#include <mach/mux.h>
18a8505c 38#include <mach/aemif.h>
0fbc5592 39
782f2d78 40#define DA850_EVM_PHY_ID "0:00"
7761ef67 41#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
5cbdf276 42#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
5cbdf276 43
700691f2
SR		 44#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
45#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
46
2206771c
C		 47#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
48
7c5ec609
SR		 49static struct mtd_partition da850_evm_norflash_partition[] = {
50 {
e2abd5a2 51 .name = "bootloaders + env",
7c5ec609 52 .offset = 0,
e2abd5a2
SR		 53 .size = SZ_512K,
54 .mask_flags = MTD_WRITEABLE,
55 },
56 {
57 .name = "kernel",
58 .offset = MTDPART_OFS_APPEND,
59 .size = SZ_2M,
60 .mask_flags = 0,
61 },
62 {
63 .name = "filesystem",
64 .offset = MTDPART_OFS_APPEND,
7c5ec609
SR		 65 .size = MTDPART_SIZ_FULL,
66 .mask_flags = 0,
67 },
68};
69
70static struct physmap_flash_data da850_evm_norflash_data = {
71 .width = 2,
72 .parts = da850_evm_norflash_partition,
73 .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
74};
75
76static struct resource da850_evm_norflash_resource[] = {
77 {
78 .start = DA8XX_AEMIF_CS2_BASE,
79 .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
80 .flags = IORESOURCE_MEM,
81 },
82};
83
84static struct platform_device da850_evm_norflash_device = {
85 .name = "physmap-flash",
86 .id = 0,
87 .dev = {
88 .platform_data = &da850_evm_norflash_data,
89 },
90 .num_resources = 1,
91 .resource = da850_evm_norflash_resource,
92};
93
63534443
SN		 94static struct davinci_pm_config da850_pm_pdata = {
95 .sleepcount = 128,
96};
97
98static struct platform_device da850_pm_device = {
99 .name = "pm-davinci",
100 .dev = {
101 .platform_data = &da850_pm_pdata,
102 },
103 .id = -1,
104};
105
38beb929
SR		 106/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
107 * (128K blocks). It may be used instead of the (default) SPI flash
108 * to boot, using TI's tools to install the secondary boot loader
109 * (UBL) and U-Boot.
110 */
db549d22 111static struct mtd_partition da850_evm_nandflash_partition[] = {
38beb929
SR		 112 {
113 .name = "u-boot env",
114 .offset = 0,
115 .size = SZ_128K,
116 .mask_flags = MTD_WRITEABLE,
117 },
118 {
119 .name = "UBL",
120 .offset = MTDPART_OFS_APPEND,
121 .size = SZ_128K,
122 .mask_flags = MTD_WRITEABLE,
123 },
124 {
125 .name = "u-boot",
126 .offset = MTDPART_OFS_APPEND,
127 .size = 4 * SZ_128K,
128 .mask_flags = MTD_WRITEABLE,
129 },
130 {
131 .name = "kernel",
132 .offset = 0x200000,
133 .size = SZ_2M,
134 .mask_flags = 0,
135 },
136 {
137 .name = "filesystem",
138 .offset = MTDPART_OFS_APPEND,
139 .size = MTDPART_SIZ_FULL,
140 .mask_flags = 0,
141 },
142};
143
18a8505c
SN		 144static struct davinci_aemif_timing da850_evm_nandflash_timing = {
145 .wsetup = 24,
146 .wstrobe = 21,
147 .whold = 14,
148 .rsetup = 19,
149 .rstrobe = 50,
150 .rhold = 0,
151 .ta = 20,
152};
153
38beb929
SR		 154static struct davinci_nand_pdata da850_evm_nandflash_data = {
155 .parts = da850_evm_nandflash_partition,
156 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
157 .ecc_mode = NAND_ECC_HW,
fc42e335 158 .ecc_bits = 4,
38beb929 159 .options = NAND_USE_FLASH_BBT,
18a8505c 160 .timing = &da850_evm_nandflash_timing,
38beb929
SR		 161};
162
163static struct resource da850_evm_nandflash_resource[] = {
164 {
165 .start = DA8XX_AEMIF_CS3_BASE,
166 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
167 .flags = IORESOURCE_MEM,
168 },
169 {
170 .start = DA8XX_AEMIF_CTL_BASE,
171 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174};
175
176static struct platform_device da850_evm_nandflash_device = {
177 .name = "davinci_nand",
178 .id = 1,
179 .dev = {
180 .platform_data = &da850_evm_nandflash_data,
181 },
182 .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
183 .resource = da850_evm_nandflash_resource,
184};
185
039c5ee3
SR		 186static struct platform_device *da850_evm_devices[] __initdata = {
187 &da850_evm_nandflash_device,
188 &da850_evm_norflash_device,
189};
190
191#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
192#define DA8XX_AEMIF_ASIZE_16BIT 0x1
193
194static void __init da850_evm_init_nor(void)
195{
196 void __iomem *aemif_addr;
197
198 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
199
200 /* Configure data bus width of CS2 to 16 bit */
201 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
202 DA8XX_AEMIF_ASIZE_16BIT,
203 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
204
205 iounmap(aemif_addr);
206}
207
f48ecc2f
SS		 208static const short da850_evm_nand_pins[] = {
209 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
210 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
211 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
212 DA850_NEMA_WE, DA850_NEMA_OE,
213 -1
214};
215
216static const short da850_evm_nor_pins[] = {
217 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
218 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
219 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
220 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
221 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
222 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
223 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
224 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
225 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
226 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
227 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
228 DA850_EMA_A_22, DA850_EMA_A_23,
229 -1
230};
231
75e2ea64 232static u32 ui_card_detected;
039c5ee3
SR		 233
234#if defined(CONFIG_MMC_DAVINCI) || \
235 defined(CONFIG_MMC_DAVINCI_MODULE)
236#define HAS_MMC 1
237#else
238#define HAS_MMC 0
239#endif
240
f48ecc2f 241static inline void da850_evm_setup_nor_nand(void)
039c5ee3
SR		 242{
243 int ret = 0;
244
245 if (ui_card_detected & !HAS_MMC) {
f48ecc2f 246 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
039c5ee3
SR		 247 if (ret)
248 pr_warning("da850_evm_init: nand mux setup failed: "
249 "%d\n", ret);
250
f48ecc2f 251 ret = davinci_cfg_reg_list(da850_evm_nor_pins);
039c5ee3
SR		 252 if (ret)
253 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
254 ret);
255
256 da850_evm_init_nor();
257
258 platform_add_devices(da850_evm_devices,
259 ARRAY_SIZE(da850_evm_devices));
260 }
261}
75e2ea64 262
bae10587
SN		 263#ifdef CONFIG_DA850_UI_RMII
264static inline void da850_evm_setup_emac_rmii(int rmii_sel)
265{
266 struct davinci_soc_info *soc_info = &davinci_soc_info;
267
268 soc_info->emac_pdata->rmii_en = 1;
269 gpio_set_value(rmii_sel, 0);
270}
271#else
272static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
273#endif
274
75e2ea64
C		 275static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
276 unsigned ngpio, void *c)
277{
278 int sel_a, sel_b, sel_c, ret;
279
280 sel_a = gpio + 7;
281 sel_b = gpio + 6;
282 sel_c = gpio + 5;
283
284 ret = gpio_request(sel_a, "sel_a");
285 if (ret) {
286 pr_warning("Cannot open UI expander pin %d\n", sel_a);
287 goto exp_setup_sela_fail;
288 }
289
290 ret = gpio_request(sel_b, "sel_b");
291 if (ret) {
292 pr_warning("Cannot open UI expander pin %d\n", sel_b);
293 goto exp_setup_selb_fail;
294 }
295
296 ret = gpio_request(sel_c, "sel_c");
297 if (ret) {
298 pr_warning("Cannot open UI expander pin %d\n", sel_c);
299 goto exp_setup_selc_fail;
300 }
301
302 /* deselect all functionalities */
303 gpio_direction_output(sel_a, 1);
304 gpio_direction_output(sel_b, 1);
305 gpio_direction_output(sel_c, 1);
306
307 ui_card_detected = 1;
308 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
309
310 da850_evm_setup_nor_nand();
311
bae10587 312 da850_evm_setup_emac_rmii(sel_a);
2206771c 313
75e2ea64
C		 314 return 0;
315
316exp_setup_selc_fail:
317 gpio_free(sel_b);
318exp_setup_selb_fail:
319 gpio_free(sel_a);
320exp_setup_sela_fail:
321 return ret;
322}
323
324static int da850_evm_ui_expander_teardown(struct i2c_client *client,
325 unsigned gpio, unsigned ngpio, void *c)
326{
327 /* deselect all functionalities */
328 gpio_set_value(gpio + 5, 1);
329 gpio_set_value(gpio + 6, 1);
330 gpio_set_value(gpio + 7, 1);
331
332 gpio_free(gpio + 5);
333 gpio_free(gpio + 6);
334 gpio_free(gpio + 7);
335
336 return 0;
337}
338
339static struct pca953x_platform_data da850_evm_ui_expander_info = {
340 .gpio_base = DAVINCI_N_GPIO,
341 .setup = da850_evm_ui_expander_setup,
342 .teardown = da850_evm_ui_expander_teardown,
343};
344
1a7ff8ff
C		 345static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
346 {
347 I2C_BOARD_INFO("tlv320aic3x", 0x18),
75e2ea64
C		 348 },
349 {
350 I2C_BOARD_INFO("tca6416", 0x20),
351 .platform_data = &da850_evm_ui_expander_info,
352 },
1a7ff8ff
C		 353};
354
0fbc5592
SR		 355static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
356 .bus_freq = 100, /* kHz */
357 .bus_delay = 0, /* usec */
358};
359
360static struct davinci_uart_config da850_evm_uart_config __initdata = {
361 .enabled_uarts = 0x7,
362};
363
491214e1
C		 364/* davinci da850 evm audio machine driver */
365static u8 da850_iis_serializer_direction[] = {
366 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
367 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
368 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
369 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
370};
371
372static struct snd_platform_data da850_evm_snd_data = {
373 .tx_dma_offset = 0x2000,
374 .rx_dma_offset = 0x2000,
375 .op_mode = DAVINCI_MCASP_IIS_MODE,
376 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
377 .tdm_slots = 2,
378 .serial_dir = da850_iis_serializer_direction,
48519f0a 379 .asp_chan_q = EVENTQ_1,
491214e1
C		 380 .version = MCASP_VERSION_2,
381 .txnumevt = 1,
382 .rxnumevt = 1,
383};
384
700691f2
SR		 385static int da850_evm_mmc_get_ro(int index)
386{
387 return gpio_get_value(DA850_MMCSD_WP_PIN);
388}
389
390static int da850_evm_mmc_get_cd(int index)
391{
392 return !gpio_get_value(DA850_MMCSD_CD_PIN);
393}
394
395static struct davinci_mmc_config da850_mmc_config = {
396 .get_ro = da850_evm_mmc_get_ro,
397 .get_cd = da850_evm_mmc_get_cd,
398 .wires = 4,
0046d0bf
C		 399 .max_freq = 50000000,
400 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
700691f2
SR		 401 .version = MMC_CTLR_VERSION_2,
402};
403
d52f235f
C		 404static void da850_panel_power_ctrl(int val)
405{
406 /* lcd backlight */
407 gpio_set_value(DA850_LCD_BL_PIN, val);
408
409 /* lcd power */
410 gpio_set_value(DA850_LCD_PWR_PIN, val);
411}
412
5cbdf276
SR		 413static int da850_lcd_hw_init(void)
414{
415 int status;
416
417 status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n");
418 if (status < 0)
419 return status;
420
421 status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n");
422 if (status < 0) {
423 gpio_free(DA850_LCD_BL_PIN);
424 return status;
425 }
426
427 gpio_direction_output(DA850_LCD_BL_PIN, 0);
428 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
429
d52f235f
C		 430 /* Switch off panel power and backlight */
431 da850_panel_power_ctrl(0);
5cbdf276 432
d52f235f
C		 433 /* Switch on panel power and backlight */
434 da850_panel_power_ctrl(1);
5cbdf276
SR		 435
436 return 0;
437}
491214e1 438
a9eb1f67
SN		 439/* TPS65070 voltage regulator support */
440
441/* 3.3V */
db549d22 442static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
a9eb1f67
SN		 443 {
444 .supply = "usb0_vdda33",
445 },
446 {
447 .supply = "usb1_vdda33",
448 },
449};
450
451/* 3.3V or 1.8V */
db549d22 452static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
a9eb1f67
SN		 453 {
454 .supply = "dvdd3318_a",
455 },
456 {
457 .supply = "dvdd3318_b",
458 },
459 {
460 .supply = "dvdd3318_c",
461 },
462};
463
464/* 1.2V */
db549d22 465static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
a9eb1f67
SN		 466 {
467 .supply = "cvdd",
468 },
469};
470
471/* 1.8V LDO */
db549d22 472static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
a9eb1f67
SN		 473 {
474 .supply = "sata_vddr",
475 },
476 {
477 .supply = "usb0_vdda18",
478 },
479 {
480 .supply = "usb1_vdda18",
481 },
482 {
483 .supply = "ddr_dvdd18",
484 },
485};
486
487/* 1.2V LDO */
db549d22 488static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
a9eb1f67
SN		 489 {
490 .supply = "sata_vdd",
491 },
492 {
493 .supply = "pll0_vdda",
494 },
495 {
496 .supply = "pll1_vdda",
497 },
498 {
499 .supply = "usbs_cvdd",
500 },
501 {
502 .supply = "vddarnwa1",
503 },
504};
505
8b24599e
SN		 506/* We take advantage of the fact that both defdcdc{2,3} are tied high */
507static struct tps6507x_reg_platform_data tps6507x_platform_data = {
508 .defdcdc_default = true,
509};
510
db549d22 511static struct regulator_init_data tps65070_regulator_data[] = {
a9eb1f67
SN		 512 /* dcdc1 */
513 {
514 .constraints = {
515 .min_uV = 3150000,
516 .max_uV = 3450000,
517 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
518 REGULATOR_CHANGE_STATUS),
519 .boot_on = 1,
520 },
521 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
522 .consumer_supplies = tps65070_dcdc1_consumers,
523 },
524
525 /* dcdc2 */
526 {
527 .constraints = {
528 .min_uV = 1710000,
529 .max_uV = 3450000,
530 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
531 REGULATOR_CHANGE_STATUS),
532 .boot_on = 1,
533 },
534 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
535 .consumer_supplies = tps65070_dcdc2_consumers,
8b24599e 536 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 537 },
538
539 /* dcdc3 */
540 {
541 .constraints = {
542 .min_uV = 950000,
543 .max_uV = 1320000,
544 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
545 REGULATOR_CHANGE_STATUS),
546 .boot_on = 1,
547 },
548 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
549 .consumer_supplies = tps65070_dcdc3_consumers,
8b24599e 550 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 551 },
552
553 /* ldo1 */
554 {
555 .constraints = {
556 .min_uV = 1710000,
557 .max_uV = 1890000,
558 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
559 REGULATOR_CHANGE_STATUS),
560 .boot_on = 1,
561 },
562 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
563 .consumer_supplies = tps65070_ldo1_consumers,
564 },
565
566 /* ldo2 */
567 {
568 .constraints = {
569 .min_uV = 1140000,
570 .max_uV = 1320000,
571 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
572 REGULATOR_CHANGE_STATUS),
573 .boot_on = 1,
574 },
575 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
576 .consumer_supplies = tps65070_ldo2_consumers,
577 },
578};
579
da1e3680
TF		 580static struct touchscreen_init_data tps6507x_touchscreen_data = {
581 .poll_period = 30, /* ms between touch samples */
582 .min_pressure = 0x30, /* minimum pressure to trigger touch */
583 .vref = 0, /* turn off vref when not using A/D */
584 .vendor = 0, /* /sys/class/input/input?/id/vendor */
585 .product = 65070, /* /sys/class/input/input?/id/product */
586 .version = 0x100, /* /sys/class/input/input?/id/version */
587};
588
0bc20bba
TF		 589static struct tps6507x_board tps_board = {
590 .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
da1e3680 591 .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
0bc20bba
TF		 592};
593
a9eb1f67
SN		 594static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
595 {
596 I2C_BOARD_INFO("tps6507x", 0x48),
0bc20bba 597 .platform_data = &tps_board,
a9eb1f67
SN		 598 },
599};
600
601static int __init pmic_tps65070_init(void)
602{
603 return i2c_register_board_info(1, da850evm_tps65070_info,
604 ARRAY_SIZE(da850evm_tps65070_info));
605}
606
7761ef67
SR		 607static const short da850_evm_lcdc_pins[] = {
608 DA850_GPIO2_8, DA850_GPIO2_15,
609 -1
610};
611
85b8307f
SS		 612static const short da850_evm_mii_pins[] = {
613 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
614 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
615 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
616 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
617 DA850_MDIO_D,
618 -1
619};
620
621static const short da850_evm_rmii_pins[] = {
622 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
623 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
624 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
625 DA850_MDIO_D,
626 -1
627};
628
bae10587 629static int __init da850_evm_config_emac(void)
2206771c
C		 630{
631 void __iomem *cfg_chip3_base;
632 int ret;
633 u32 val;
bae10587
SN		 634 struct davinci_soc_info *soc_info = &davinci_soc_info;
635 u8 rmii_en = soc_info->emac_pdata->rmii_en;
636
637 if (!machine_is_davinci_da850_evm())
638 return 0;
2206771c 639
d2de0582 640 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
2206771c 641
2206771c 642 val = __raw_readl(cfg_chip3_base);
17fadd9a
SN		 643
644 if (rmii_en) {
2206771c 645 val |= BIT(8);
85b8307f 646 ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
17fadd9a
SN		 647 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
648 " functional\n");
649 } else {
2206771c 650 val &= ~BIT(8);
85b8307f 651 ret = davinci_cfg_reg_list(da850_evm_mii_pins);
17fadd9a
SN		 652 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
653 " functional\n");
654 }
655
2206771c
C		 656 if (ret)
657 pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
658 ret);
659
17fadd9a
SN		 660 /* configure the CFGCHIP3 register for RMII or MII */
661 __raw_writel(val, cfg_chip3_base);
662
2206771c
C		 663 ret = davinci_cfg_reg(DA850_GPIO2_6);
664 if (ret)
665 pr_warning("da850_evm_init:GPIO(2,6) mux setup "
666 "failed\n");
667
668 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
669 if (ret) {
670 pr_warning("Cannot open GPIO %d\n",
671 DA850_MII_MDIO_CLKEN_PIN);
672 return ret;
673 }
674
17fadd9a
SN		 675 /* Enable/Disable MII MDIO clock */
676 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
2206771c 677
782f2d78 678 soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
bae10587
SN		 679
680 ret = da8xx_register_emac();
681 if (ret)
682 pr_warning("da850_evm_init: emac registration failed: %d\n",
683 ret);
684
2206771c
C		 685 return 0;
686}
bae10587 687device_initcall(da850_evm_config_emac);
2206771c 688
a941c503
RS		 689/*
690 * The following EDMA channels/slots are not being used by drivers (for
691 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
692 * they are being reserved for codecs on the DSP side.
693 */
694static const s16 da850_dma0_rsv_chans[][2] = {
695 /* (offset, number) */
696 { 8, 6},
697 {24, 4},
698 {30, 2},
699 {-1, -1}
700};
701
702static const s16 da850_dma0_rsv_slots[][2] = {
703 /* (offset, number) */
704 { 8, 6},
705 {24, 4},
706 {30, 50},
707 {-1, -1}
708};
709
710static const s16 da850_dma1_rsv_chans[][2] = {
711 /* (offset, number) */
712 { 0, 28},
713 {30, 2},
714 {-1, -1}
715};
716
717static const s16 da850_dma1_rsv_slots[][2] = {
718 /* (offset, number) */
719 { 0, 28},
720 {30, 90},
721 {-1, -1}
722};
723
724static struct edma_rsv_info da850_edma_cc0_rsv = {
725 .rsv_chans = da850_dma0_rsv_chans,
726 .rsv_slots = da850_dma0_rsv_slots,
727};
728
729static struct edma_rsv_info da850_edma_cc1_rsv = {
730 .rsv_chans = da850_dma1_rsv_chans,
731 .rsv_slots = da850_dma1_rsv_slots,
732};
733
734static struct edma_rsv_info *da850_edma_rsv[2] = {
735 &da850_edma_cc0_rsv,
736 &da850_edma_cc1_rsv,
737};
738
0fbc5592
SR		 739static __init void da850_evm_init(void)
740{
741 int ret;
742
a9eb1f67
SN		 743 ret = pmic_tps65070_init();
744 if (ret)
745 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
746 ret);
747
a941c503 748 ret = da850_register_edma(da850_edma_rsv);
0fbc5592
SR		 749 if (ret)
750 pr_warning("da850_evm_init: edma registration failed: %d\n",
751 ret);
752
3821d10a 753 ret = davinci_cfg_reg_list(da850_i2c0_pins);
0fbc5592
SR		 754 if (ret)
755 pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
756 ret);
757
758 ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
759 if (ret)
760 pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
761 ret);
762
5a4b1315 763
0fbc5592
SR		 764 ret = da8xx_register_watchdog();
765 if (ret)
766 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
767 ret);
768
820c4fe3 769 if (HAS_MMC) {
3821d10a 770 ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
820c4fe3
SR		 771 if (ret)
772 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
773 " %d\n", ret);
774
775 ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
776 if (ret)
777 pr_warning("da850_evm_init: can not open GPIO %d\n",
778 DA850_MMCSD_CD_PIN);
779 gpio_direction_input(DA850_MMCSD_CD_PIN);
780
781 ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
782 if (ret)
783 pr_warning("da850_evm_init: can not open GPIO %d\n",
784 DA850_MMCSD_WP_PIN);
785 gpio_direction_input(DA850_MMCSD_WP_PIN);
786
787 ret = da8xx_register_mmcsd0(&da850_mmc_config);
788 if (ret)
789 pr_warning("da850_evm_init: mmcsd0 registration failed:"
790 " %d\n", ret);
791 }
700691f2 792
0fbc5592
SR		 793 davinci_serial_init(&da850_evm_uart_config);
794
1a7ff8ff
C		 795 i2c_register_board_info(1, da850_evm_i2c_devices,
796 ARRAY_SIZE(da850_evm_i2c_devices));
797
0fbc5592
SR		 798 /*
799 * shut down uart 0 and 1; they are not used on the board and
800 * accessing them causes endless "too much work in irq53" messages
801 * with arago fs
802 */
803 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
804 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
491214e1 805
3821d10a 806 ret = davinci_cfg_reg_list(da850_mcasp_pins);
491214e1
C		 807 if (ret)
808 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
809 ret);
810
b8864aa4 811 da8xx_register_mcasp(0, &da850_evm_snd_data);
5cbdf276 812
3821d10a 813 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
5cbdf276
SR		 814 if (ret)
815 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
816 ret);
817
7761ef67 818 /* Handle board specific muxing for LCD here */
3821d10a 819 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
7761ef67
SR		 820 if (ret)
821 pr_warning("da850_evm_init: evm specific lcd mux setup "
822 "failed: %d\n", ret);
823
5cbdf276
SR		 824 ret = da850_lcd_hw_init();
825 if (ret)
826 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
827 ret);
828
d52f235f 829 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
b9e6342b 830 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
5cbdf276
SR		 831 if (ret)
832 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
833 ret);
c51df70b
MG		 834
835 ret = da8xx_register_rtc();
836 if (ret)
837 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
09dc2d45 838
b987c4b2 839 ret = da850_register_cpufreq("pll0_sysclk3");
09dc2d45
SN		 840 if (ret)
841 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
842 ret);
5aeb15aa
SN		 843
844 ret = da8xx_register_cpuidle();
845 if (ret)
846 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
847 ret);
63534443
SN		 848
849 ret = da850_register_pm(&da850_pm_device);
850 if (ret)
851 pr_warning("da850_evm_init: suspend registration failed: %d\n",
852 ret);
0fbc5592
SR		 853}
854
855#ifdef CONFIG_SERIAL_8250_CONSOLE
856static int __init da850_evm_console_init(void)
857{
1aa5f2a9
MW		 858 if (!machine_is_davinci_da850_evm())
859 return 0;
860
0fbc5592
SR		 861 return add_preferred_console("ttyS", 2, "115200");
862}
863console_initcall(da850_evm_console_init);
864#endif
865
0fbc5592
SR		 866static void __init da850_evm_map_io(void)
867{
868 da850_init();
869}
870
48ea89ea 871MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
0fbc5592
SR		 872 .boot_params = (DA8XX_DDR_BASE + 0x100),
873 .map_io = da850_evm_map_io,
bd808947 874 .init_irq = cp_intc_init,
0fbc5592
SR		 875 .timer = &davinci_timer,
876 .init_machine = da850_evm_init,
877MACHINE_END
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