[net-next-2.6.git] / arch / arm / mach-at91 / clock.c

/*
 * linux/arch/arm/mach-at91/clock.c
 *
 * Copyright (C) 2005 David Brownell
 * Copyright (C) 2005 Ivan Kokshaysky
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/mach-types.h>

#include <asm/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/cpu.h>

#include "clock.h"


/*
 * There's a lot more which can be done with clocks, including cpufreq
 * integration, slow clock mode support (for system suspend), letting
 * PLLB be used at other rates (on boards that don't need USB), etc.
 */

#define clk_is_primary(x)	((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_programmable(x)	((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_peripheral(x)	((x)->type & CLK_TYPE_PERIPHERAL)
#define clk_is_sys(x)		((x)->type & CLK_TYPE_SYSTEM)


static LIST_HEAD(clocks);
static DEFINE_SPINLOCK(clk_lock);

static u32 at91_pllb_usb_init;

/*
 * Four primary clock sources:  two crystal oscillators (32K, main), and
 * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 * 48 MHz (unless no USB function clocks are needed).  The main clock and
 * both PLLs are turned off to run in "slow clock mode" (system suspend).
 */
static struct clk clk32k = {
	.name		= "clk32k",
	.rate_hz	= AT91_SLOW_CLOCK,
	.users		= 1,		/* always on */
	.id		= 0,
	.type		= CLK_TYPE_PRIMARY,
};
static struct clk main_clk = {
	.name		= "main",
	.pmc_mask	= AT91_PMC_MOSCS,	/* in PMC_SR */
	.id		= 1,
	.type		= CLK_TYPE_PRIMARY,
};
static struct clk plla = {
	.name		= "plla",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKA,	/* in PMC_SR */
	.id		= 2,
	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};

static void pllb_mode(struct clk *clk, int is_on)
{
	u32	value;

	if (is_on) {
		is_on = AT91_PMC_LOCKB;
		value = at91_pllb_usb_init;
	} else
		value = 0;

	// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
	at91_sys_write(AT91_CKGR_PLLBR, value);

	do {
		cpu_relax();
	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}

static struct clk pllb = {
	.name		= "pllb",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKB,	/* in PMC_SR */
	.mode		= pllb_mode,
	.id		= 3,
	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};

static void pmc_sys_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
}

/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
	.name		= "udpck",
	.parent		= &pllb,
	.mode		= pmc_sys_mode,
};
static struct clk uhpck = {
	.name		= "uhpck",
	.parent		= &pllb,
	.mode		= pmc_sys_mode,
};


/*
 * The master clock is divided from the CPU clock (by 1-4).  It's used for
 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 */
static struct clk mck = {
	.name		= "mck",
	.pmc_mask	= AT91_PMC_MCKRDY,	/* in PMC_SR */
};

static void pmc_periph_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
}

static struct clk __init *at91_css_to_clk(unsigned long css)
{
	switch (css) {
		case AT91_PMC_CSS_SLOW:
			return &clk32k;
		case AT91_PMC_CSS_MAIN:
			return &main_clk;
		case AT91_PMC_CSS_PLLA:
			return &plla;
		case AT91_PMC_CSS_PLLB:
			return &pllb;
	}

	return NULL;
}

/*
 * Associate a particular clock with a function (eg, "uart") and device.
 * The drivers can then request the same 'function' with several different
 * devices and not care about which clock name to use.
 */
void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
{
	struct clk *clk = clk_get(NULL, id);

	if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
		return;

	clk->function = func;
	clk->dev = dev;
}

/* clocks cannot be de-registered no refcounting necessary */
struct clk *clk_get(struct device *dev, const char *id)
{
	struct clk *clk;

	list_for_each_entry(clk, &clocks, node) {
		if (strcmp(id, clk->name) == 0)
			return clk;
		if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
			return clk;
	}

	return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);

void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

static void __clk_enable(struct clk *clk)
{
	if (clk->parent)
		__clk_enable(clk->parent);
	if (clk->users++ == 0 && clk->mode)
		clk->mode(clk, 1);
}

int clk_enable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	BUG_ON(clk->users == 0);
	if (--clk->users == 0 && clk->mode)
		clk->mode(clk, 0);
	if (clk->parent)
		__clk_disable(clk->parent);
}

void clk_disable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	unsigned long	flags;
	unsigned long	rate;

	spin_lock_irqsave(&clk_lock, flags);
	for (;;) {
		rate = clk->rate_hz;
		if (rate || !clk->parent)
			break;
		clk = clk->parent;
	}
	spin_unlock_irqrestore(&clk_lock, flags);
	return rate;
}
EXPORT_SYMBOL(clk_get_rate);

/*------------------------------------------------------------------------*/

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS

/*
 * For now, only the programmable clocks support reparenting (MCK could
 * do this too, with care) or rate changing (the PLLs could do this too,
 * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 * a better rate match; we don't.
 */

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk_is_programmable(clk))
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate)
			break;
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk_is_programmable(clk))
		return -EINVAL;
	if (clk->users)
		return -EBUSY;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate) {
			u32	pckr;

			pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
			pckr &= AT91_PMC_CSS_PLLB;	/* clock selection */
			pckr |= prescale << 2;
			at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
			clk->rate_hz = actual;
			break;
		}
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long	flags;

	if (clk->users)
		return -EBUSY;
	if (!clk_is_primary(parent) || !clk_is_programmable(clk))
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	clk->rate_hz = parent->rate_hz;
	clk->parent = parent;
	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);

	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

/* establish PCK0..PCK3 parentage and rate */
static void init_programmable_clock(struct clk *clk)
{
	struct clk	*parent;
	u32		pckr;

	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
	parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
	clk->parent = parent;
	clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
}

#endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */

/*------------------------------------------------------------------------*/

#ifdef CONFIG_DEBUG_FS

static int at91_clk_show(struct seq_file *s, void *unused)
{
	u32		scsr, pcsr, sr;
	struct clk	*clk;
	unsigned	i;

	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));

	seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
	seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));

	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
	for (i = 0; i < 4; i++)
		seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
	seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));

	seq_printf(s, "\n");

	list_for_each_entry(clk, &clocks, node) {
		char	*state;

		if (clk->mode == pmc_sys_mode)
			state = (scsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->mode == pmc_periph_mode)
			state = (pcsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->pmc_mask)
			state = (sr & clk->pmc_mask) ? "on" : "off";
		else if (clk == &clk32k || clk == &main_clk)
			state = "on";
		else
			state = "";

		seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
			clk->name, clk->users, state, clk_get_rate(clk),
			clk->parent ? clk->parent->name : "");
	}
	return 0;
}

static int at91_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, at91_clk_show, NULL);
}

static struct file_operations at91_clk_operations = {
	.open		= at91_clk_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init at91_clk_debugfs_init(void)
{
	/* /sys/kernel/debug/at91_clk */
	(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);

	return 0;
}
postcore_initcall(at91_clk_debugfs_init);

#endif

/*------------------------------------------------------------------------*/

/* Register a new clock */
int __init clk_register(struct clk *clk)
{
	if (clk_is_peripheral(clk)) {
		clk->parent = &mck;
		clk->mode = pmc_periph_mode;
		list_add_tail(&clk->node, &clocks);
	}
	else if (clk_is_sys(clk)) {
		clk->parent = &mck;
		clk->mode = pmc_sys_mode;

		list_add_tail(&clk->node, &clocks);
	}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	else if (clk_is_programmable(clk)) {
		clk->mode = pmc_sys_mode;
		init_programmable_clock(clk);
		list_add_tail(&clk->node, &clocks);
	}
#endif

	return 0;
}


/*------------------------------------------------------------------------*/

static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
	unsigned mul, div;

	div = reg & 0xff;
	mul = (reg >> 16) & 0x7ff;
	if (div && mul) {
		freq /= div;
		freq *= mul + 1;
	} else
		freq = 0;

	return freq;
}

static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
	if (pll == &pllb && (reg & AT91_PMC_USB96M))
		return freq / 2;
	else
		return freq;
}

static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;

	/* PLL output max 240 MHz (or 180 MHz per errata) */
	if (out_freq > 240000000)
		goto fail;

	for (i = 1; i < 256; i++) {
		int diff1;
		unsigned input, mul1;

		/*
		 * PLL input between 1MHz and 32MHz per spec, but lower
		 * frequences seem necessary in some cases so allow 100K.
		 */
		input = main_freq / i;
		if (input < 100000)
			continue;
		if (input > 32000000)
			continue;

		mul1 = out_freq / input;
		if (mul1 > 2048)
			continue;
		if (mul1 < 2)
			goto fail;

		diff1 = out_freq - input * mul1;
		if (diff1 < 0)
			diff1 = -diff1;
		if (diff > diff1) {
			diff = diff1;
			div = i;
			mul = mul1;
			if (diff == 0)
				break;
		}
	}
	if (i == 256 && diff > (out_freq >> 5))
		goto fail;
	return ret | ((mul - 1) << 16) | div;
fail:
	return 0;
}

/*
 * Several unused clocks may be active.  Turn them off.
 */
static void __init at91_periphclk_reset(void)
{
	unsigned long reg;
	struct clk *clk;

	reg = at91_sys_read(AT91_PMC_PCSR);

	list_for_each_entry(clk, &clocks, node) {
		if (clk->mode != pmc_periph_mode)
			continue;

		if (clk->users > 0)
			reg &= ~clk->pmc_mask;
	}

	at91_sys_write(AT91_PMC_PCDR, reg);
}

static struct clk *const standard_pmc_clocks[] __initdata = {
	/* four primary clocks */
	&clk32k,
	&main_clk,
	&plla,
	&pllb,

	/* PLLB children (USB) */
	&udpck,
	&uhpck,

	/* MCK */
	&mck
};

int __init at91_clock_init(unsigned long main_clock)
{
	unsigned tmp, freq, mckr;
	int i;

	/*
	 * When the bootloader initialized the main oscillator correctly,
	 * there's no problem using the cycle counter.  But if it didn't,
	 * or when using oscillator bypass mode, we must be told the speed
	 * of the main clock.
	 */
	if (!main_clock) {
		do {
			tmp = at91_sys_read(AT91_CKGR_MCFR);
		} while (!(tmp & AT91_PMC_MAINRDY));
		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
	}
	main_clk.rate_hz = main_clock;

	/* report if PLLA is more than mildly overclocked */
	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
	if (plla.rate_hz > 209000000)
		pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);

	/*
	 * USB clock init:  choose 48 MHz PLLB value, turn all clocks off,
	 * disable 48MHz clock during usb peripheral suspend.
	 *
	 * REVISIT:  assumes MCK doesn't derive from PLLB!
	 */
	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
	if (cpu_is_at91rm9200()) {
		uhpck.pmc_mask = AT91RM9200_PMC_UHP;
		udpck.pmc_mask = AT91RM9200_PMC_UDP;
		at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
		at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
	} else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
		uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
		udpck.pmc_mask = AT91SAM926x_PMC_UDP;
		at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
	} else if (cpu_is_at91sam9261()) {
		uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
		udpck.pmc_mask = AT91SAM926x_PMC_UDP;
		at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
	}
	at91_sys_write(AT91_CKGR_PLLBR, 0);

	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);

	/*
	 * MCK and CPU derive from one of those primary clocks.
	 * For now, assume this parentage won't change.
	 */
	mckr = at91_sys_read(AT91_PMC_MCKR);
	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
	freq = mck.parent->rate_hz;
	freq /= (1 << ((mckr >> 2) & 3));		/* prescale */
	mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));	/* mdiv */

	/* Register the PMC's standard clocks */
	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
		list_add_tail(&standard_pmc_clocks[i]->node, &clocks);

	/* MCK and CPU clock are "always on" */
	clk_enable(&mck);

	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
		(unsigned) main_clock / 1000000,
		((unsigned) main_clock % 1000000) / 1000);

	/* disable all programmable clocks */
	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);

	/* disable all other unused peripheral clocks */
	at91_periphclk_reset();

	return 0;
}
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* linux/arch/arm/mach-at91/clock.c
73a59c1c SP	3	*
	4	* Copyright (C) 2005 David Brownell
	5	* Copyright (C) 2005 Ivan Kokshaysky
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/fs.h>
	17	#include <linux/debugfs.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/list.h>
	20	#include <linux/errno.h>
	21	#include <linux/err.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/delay.h>
	24	#include <linux/clk.h>
	25
	26	#include <asm/semaphore.h>
	27	#include <asm/io.h>
	28	#include <asm/mach-types.h>
	29
ea75ee9a	30	#include <asm/hardware.h>
55d8baee	31	#include <asm/arch/at91_pmc.h>
d481f864	32	#include <asm/arch/cpu.h>
73a59c1c	33
2eeaaa21	34	#include "clock.h"
73a59c1c	35
55c20c0a	36
73a59c1c SP	37	/*
	38	* There's a lot more which can be done with clocks, including cpufreq
	39	* integration, slow clock mode support (for system suspend), letting
	40	* PLLB be used at other rates (on boards that don't need USB), etc.
	41	*/
	42
2eeaaa21 AV	43	#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
	44	#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
	45	#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
d481f864	46	#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
2eeaaa21 AV	47
	48
	49	static LIST_HEAD(clocks);
	50	static DEFINE_SPINLOCK(clk_lock);
73a59c1c	51
2eeaaa21	52	static u32 at91_pllb_usb_init;
73a59c1c SP	53
	54	/*
	55	* Four primary clock sources: two crystal oscillators (32K, main), and
	56	* two PLLs. PLLA usually runs the master clock; and PLLB must run at
	57	* 48 MHz (unless no USB function clocks are needed). The main clock and
	58	* both PLLs are turned off to run in "slow clock mode" (system suspend).
	59	*/
	60	static struct clk clk32k = {
	61	.name = "clk32k",
	62	.rate_hz = AT91_SLOW_CLOCK,
	63	.users = 1, /* always on */
	64	.id = 0,
2eeaaa21	65	.type = CLK_TYPE_PRIMARY,
73a59c1c SP	66	};
	67	static struct clk main_clk = {
	68	.name = "main",
91f8ed83	69	.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
73a59c1c	70	.id = 1,
2eeaaa21	71	.type = CLK_TYPE_PRIMARY,
73a59c1c SP	72	};
	73	static struct clk plla = {
	74	.name = "plla",
	75	.parent = &main_clk,
91f8ed83	76	.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
73a59c1c	77	.id = 2,
2eeaaa21	78	.type = CLK_TYPE_PRIMARY \| CLK_TYPE_PLL,
73a59c1c SP	79	};
	80
	81	static void pllb_mode(struct clk *clk, int is_on)
	82	{
	83	u32 value;
	84
	85	if (is_on) {
	86	is_on = AT91_PMC_LOCKB;
	87	value = at91_pllb_usb_init;
	88	} else
	89	value = 0;
	90
2eeaaa21	91	// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
73a59c1c SP	92	at91_sys_write(AT91_CKGR_PLLBR, value);
	93
	94	do {
	95	cpu_relax();
	96	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
	97	}
	98
	99	static struct clk pllb = {
	100	.name = "pllb",
	101	.parent = &main_clk,
91f8ed83	102	.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
73a59c1c SP	103	.mode = pllb_mode,
73a59c1c SP	104	.id = 3,
2eeaaa21	105	.type = CLK_TYPE_PRIMARY \| CLK_TYPE_PLL,
73a59c1c SP	106	};
	107
	108	static void pmc_sys_mode(struct clk *clk, int is_on)
	109	{
	110	if (is_on)
	111	at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	112	else
	113	at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
	114	}
	115
	116	/* USB function clocks (PLLB must be 48 MHz) */
	117	static struct clk udpck = {
	118	.name = "udpck",
	119	.parent = &pllb,
73a59c1c SP	120	.mode = pmc_sys_mode,
	121	};
	122	static struct clk uhpck = {
	123	.name = "uhpck",
	124	.parent = &pllb,
73a59c1c SP	125	.mode = pmc_sys_mode,
	126	};
	127
73a59c1c SP	128
	129	/*
	130	* The master clock is divided from the CPU clock (by 1-4). It's used for
	131	* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
	132	* (e.g baud rate generation). It's sourced from one of the primary clocks.
	133	*/
	134	static struct clk mck = {
	135	.name = "mck",
91f8ed83	136	.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
73a59c1c SP	137	};
	138
	139	static void pmc_periph_mode(struct clk *clk, int is_on)
	140	{
	141	if (is_on)
	142	at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	143	else
	144	at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
	145	}
	146
2eeaaa21 AV	147	static struct clk __init *at91_css_to_clk(unsigned long css)
	148	{
	149	switch (css) {
	150	case AT91_PMC_CSS_SLOW:
	151	return &clk32k;
	152	case AT91_PMC_CSS_MAIN:
	153	return &main_clk;
	154	case AT91_PMC_CSS_PLLA:
	155	return &plla;
	156	case AT91_PMC_CSS_PLLB:
	157	return &pllb;
	158	}
73a59c1c	159
2eeaaa21 AV	160	return NULL;
2eeaaa21 AV	161	}
73a59c1c	162
91f8ed83 AV	163	/*
	164	* Associate a particular clock with a function (eg, "uart") and device.
	165	* The drivers can then request the same 'function' with several different
	166	* devices and not care about which clock name to use.
	167	*/
	168	void __init at91_clock_associate(const char id, struct device dev, const char *func)
	169	{
	170	struct clk *clk = clk_get(NULL, id);
	171
	172	if (!dev \|\| !clk \|\| !IS_ERR(clk_get(dev, func)))
	173	return;
	174
	175	clk->function = func;
	176	clk->dev = dev;
	177	}
	178
2eeaaa21	179	/* clocks cannot be de-registered no refcounting necessary */
73a59c1c SP	180	struct clk clk_get(struct device dev, const char *id)
73a59c1c SP	181	{
2eeaaa21	182	struct clk *clk;
91f8ed83	183
2eeaaa21	184	list_for_each_entry(clk, &clocks, node) {
91f8ed83 AV	185	if (strcmp(id, clk->name) == 0)
	186	return clk;
	187	if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
	188	return clk;
73a59c1c SP	189	}
	190
	191	return ERR_PTR(-ENOENT);
	192	}
	193	EXPORT_SYMBOL(clk_get);
	194
	195	void clk_put(struct clk *clk)
	196	{
	197	}
	198	EXPORT_SYMBOL(clk_put);
	199
	200	static void __clk_enable(struct clk *clk)
	201	{
	202	if (clk->parent)
	203	__clk_enable(clk->parent);
	204	if (clk->users++ == 0 && clk->mode)
	205	clk->mode(clk, 1);
	206	}
	207
	208	int clk_enable(struct clk *clk)
	209	{
	210	unsigned long flags;
	211
	212	spin_lock_irqsave(&clk_lock, flags);
	213	__clk_enable(clk);
	214	spin_unlock_irqrestore(&clk_lock, flags);
	215	return 0;
	216	}
	217	EXPORT_SYMBOL(clk_enable);
	218
	219	static void __clk_disable(struct clk *clk)
	220	{
	221	BUG_ON(clk->users == 0);
	222	if (--clk->users == 0 && clk->mode)
	223	clk->mode(clk, 0);
	224	if (clk->parent)
	225	__clk_disable(clk->parent);
	226	}
	227
	228	void clk_disable(struct clk *clk)
	229	{
	230	unsigned long flags;
	231
	232	spin_lock_irqsave(&clk_lock, flags);
	233	__clk_disable(clk);
	234	spin_unlock_irqrestore(&clk_lock, flags);
	235	}
	236	EXPORT_SYMBOL(clk_disable);
	237
	238	unsigned long clk_get_rate(struct clk *clk)
	239	{
	240	unsigned long flags;
	241	unsigned long rate;
	242
	243	spin_lock_irqsave(&clk_lock, flags);
	244	for (;;) {
	245	rate = clk->rate_hz;
	246	if (rate \|\| !clk->parent)
	247	break;
	248	clk = clk->parent;
	249	}
	250	spin_unlock_irqrestore(&clk_lock, flags);
	251	return rate;
	252	}
253	EXPORT_SYMBOL(clk_get_rate);
254
255	/------------------------------------------------------------------------/
256
257	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
258
259	/*
260	* For now, only the programmable clocks support reparenting (MCK could
261	* do this too, with care) or rate changing (the PLLs could do this too,
262	* ditto MCK but that's more for cpufreq). Drivers may reparent to get
263	* a better rate match; we don't.
264	*/
265
266	long clk_round_rate(struct clk *clk, unsigned long rate)
267	{
268	unsigned long flags;
269	unsigned prescale;
270	unsigned long actual;
271
2eeaaa21	272	if (!clk_is_programmable(clk))
73a59c1c SP	273	return -EINVAL;
	274	spin_lock_irqsave(&clk_lock, flags);
	275
	276	actual = clk->parent->rate_hz;
	277	for (prescale = 0; prescale < 7; prescale++) {
	278	if (actual && actual <= rate)
	279	break;
	280	actual >>= 1;
	281	}
	282
	283	spin_unlock_irqrestore(&clk_lock, flags);
	284	return (prescale < 7) ? actual : -ENOENT;
	285	}
	286	EXPORT_SYMBOL(clk_round_rate);
	287
	288	int clk_set_rate(struct clk *clk, unsigned long rate)
	289	{
	290	unsigned long flags;
	291	unsigned prescale;
	292	unsigned long actual;
	293
2eeaaa21	294	if (!clk_is_programmable(clk))
73a59c1c SP	295	return -EINVAL;
	296	if (clk->users)
	297	return -EBUSY;
	298	spin_lock_irqsave(&clk_lock, flags);
	299
	300	actual = clk->parent->rate_hz;
	301	for (prescale = 0; prescale < 7; prescale++) {
	302	if (actual && actual <= rate) {
	303	u32 pckr;
	304
	305	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
69b648a2	306	pckr &= AT91_PMC_CSS_PLLB; /* clock selection */
73a59c1c SP	307	pckr \|= prescale << 2;
	308	at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
	309	clk->rate_hz = actual;
	310	break;
	311	}
	312	actual >>= 1;
	313	}
	314
	315	spin_unlock_irqrestore(&clk_lock, flags);
	316	return (prescale < 7) ? actual : -ENOENT;
	317	}
	318	EXPORT_SYMBOL(clk_set_rate);
	319
	320	struct clk clk_get_parent(struct clk clk)
	321	{
	322	return clk->parent;
	323	}
	324	EXPORT_SYMBOL(clk_get_parent);
	325
	326	int clk_set_parent(struct clk clk, struct clk parent)
	327	{
	328	unsigned long flags;
	329
	330	if (clk->users)
	331	return -EBUSY;
2eeaaa21	332	if (!clk_is_primary(parent) \|\| !clk_is_programmable(clk))
73a59c1c SP	333	return -EINVAL;
	334	spin_lock_irqsave(&clk_lock, flags);
	335
	336	clk->rate_hz = parent->rate_hz;
	337	clk->parent = parent;
	338	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
	339
	340	spin_unlock_irqrestore(&clk_lock, flags);
	341	return 0;
	342	}
	343	EXPORT_SYMBOL(clk_set_parent);
	344
2eeaaa21 AV	345	/* establish PCK0..PCK3 parentage and rate */
	346	static void init_programmable_clock(struct clk *clk)
	347	{
	348	struct clk *parent;
	349	u32 pckr;
	350
	351	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
	352	parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
	353	clk->parent = parent;
	354	clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
	355	}
	356
73a59c1c SP	357	#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
	358
	359	/------------------------------------------------------------------------/
	360
	361	#ifdef CONFIG_DEBUG_FS
	362
	363	static int at91_clk_show(struct seq_file s, void unused)
	364	{
	365	u32 scsr, pcsr, sr;
2eeaaa21	366	struct clk *clk;
73a59c1c SP	367	unsigned i;
	368
	369	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	370	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
	371
	372	seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	373	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	374	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
	375	seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
	376
	377	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
	378	for (i = 0; i < 4; i++)
	379	seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
	380	seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
	381
	382	seq_printf(s, "\n");
	383
2eeaaa21 AV	384	list_for_each_entry(clk, &clocks, node) {
2eeaaa21 AV	385	char *state;
73a59c1c SP	386
	387	if (clk->mode == pmc_sys_mode)
	388	state = (scsr & clk->pmc_mask) ? "on" : "off";
	389	else if (clk->mode == pmc_periph_mode)
	390	state = (pcsr & clk->pmc_mask) ? "on" : "off";
	391	else if (clk->pmc_mask)
	392	state = (sr & clk->pmc_mask) ? "on" : "off";
	393	else if (clk == &clk32k \|\| clk == &main_clk)
	394	state = "on";
	395	else
	396	state = "";
	397
69b648a2	398	seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
73a59c1c SP	399	clk->name, clk->users, state, clk_get_rate(clk),
	400	clk->parent ? clk->parent->name : "");
	401	}
	402	return 0;
	403	}
	404
	405	static int at91_clk_open(struct inode inode, struct file file)
	406	{
	407	return single_open(file, at91_clk_show, NULL);
	408	}
	409
	410	static struct file_operations at91_clk_operations = {
	411	.open = at91_clk_open,
	412	.read = seq_read,
	413	.llseek = seq_lseek,
	414	.release = single_release,
	415	};
	416
	417	static int __init at91_clk_debugfs_init(void)
	418	{
	419	/* /sys/kernel/debug/at91_clk */
	420	(void) debugfs_create_file("at91_clk", S_IFREG \| S_IRUGO, NULL, NULL, &at91_clk_operations);
	421
	422	return 0;
	423	}
	424	postcore_initcall(at91_clk_debugfs_init);
	425
	426	#endif
	427
2eeaaa21 AV	428	/------------------------------------------------------------------------/
	429
	430	/* Register a new clock */
	431	int __init clk_register(struct clk *clk)
	432	{
	433	if (clk_is_peripheral(clk)) {
	434	clk->parent = &mck;
	435	clk->mode = pmc_periph_mode;
	436	list_add_tail(&clk->node, &clocks);
	437	}
d481f864 AV	438	else if (clk_is_sys(clk)) {
	439	clk->parent = &mck;
	440	clk->mode = pmc_sys_mode;
	441
	442	list_add_tail(&clk->node, &clocks);
	443	}
2eeaaa21 AV	444	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	445	else if (clk_is_programmable(clk)) {
	446	clk->mode = pmc_sys_mode;
	447	init_programmable_clock(clk);
	448	list_add_tail(&clk->node, &clocks);
	449	}
	450	#endif
	451
	452	return 0;
	453	}
	454
	455
73a59c1c SP	456	/------------------------------------------------------------------------/
	457
	458	static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
	459	{
	460	unsigned mul, div;
	461
	462	div = reg & 0xff;
	463	mul = (reg >> 16) & 0x7ff;
	464	if (div && mul) {
	465	freq /= div;
	466	freq *= mul + 1;
	467	} else
	468	freq = 0;
69b648a2	469
73a59c1c SP	470	return freq;
	471	}
	472
69b648a2 AV	473	static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
	474	{
	475	if (pll == &pllb && (reg & AT91_PMC_USB96M))
	476	return freq / 2;
	477	else
	478	return freq;
	479	}
	480
73a59c1c SP	481	static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
	482	{
	483	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	484	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
	485
	486	/* PLL output max 240 MHz (or 180 MHz per errata) */
	487	if (out_freq > 240000000)
	488	goto fail;
	489
	490	for (i = 1; i < 256; i++) {
	491	int diff1;
	492	unsigned input, mul1;
	493
	494	/*
	495	* PLL input between 1MHz and 32MHz per spec, but lower
	496	* frequences seem necessary in some cases so allow 100K.
	497	*/
	498	input = main_freq / i;
	499	if (input < 100000)
	500	continue;
	501	if (input > 32000000)
	502	continue;
	503
	504	mul1 = out_freq / input;
	505	if (mul1 > 2048)
	506	continue;
	507	if (mul1 < 2)
	508	goto fail;
	509
	510	diff1 = out_freq - input * mul1;
	511	if (diff1 < 0)
	512	diff1 = -diff1;
	513	if (diff > diff1) {
	514	diff = diff1;
	515	div = i;
	516	mul = mul1;
	517	if (diff == 0)
	518	break;
	519	}
	520	}
	521	if (i == 256 && diff > (out_freq >> 5))
	522	goto fail;
	523	return ret \| ((mul - 1) << 16) \| div;
	524	fail:
	525	return 0;
	526	}
	527
91f8ed83 AV	528	/*
	529	* Several unused clocks may be active. Turn them off.
	530	*/
2eeaaa21	531	static void __init at91_periphclk_reset(void)
91f8ed83 AV	532	{
91f8ed83 AV	533	unsigned long reg;
2eeaaa21	534	struct clk *clk;
91f8ed83 AV	535
	536	reg = at91_sys_read(AT91_PMC_PCSR);
	537
2eeaaa21	538	list_for_each_entry(clk, &clocks, node) {
91f8ed83 AV	539	if (clk->mode != pmc_periph_mode)
	540	continue;
	541
	542	if (clk->users > 0)
	543	reg &= ~clk->pmc_mask;
	544	}
	545
	546	at91_sys_write(AT91_PMC_PCDR, reg);
	547	}
	548
2eeaaa21 AV	549	static struct clk *const standard_pmc_clocks[] __initdata = {
	550	/* four primary clocks */
	551	&clk32k,
	552	&main_clk,
	553	&plla,
	554	&pllb,
	555
	556	/* PLLB children (USB) */
	557	&udpck,
	558	&uhpck,
	559
	560	/* MCK */
	561	&mck
	562	};
	563
73a59c1c SP	564	int __init at91_clock_init(unsigned long main_clock)
	565	{
	566	unsigned tmp, freq, mckr;
2eeaaa21	567	int i;
73a59c1c SP	568
	569	/*
	570	* When the bootloader initialized the main oscillator correctly,
	571	* there's no problem using the cycle counter. But if it didn't,
	572	* or when using oscillator bypass mode, we must be told the speed
	573	* of the main clock.
	574	*/
	575	if (!main_clock) {
	576	do {
	577	tmp = at91_sys_read(AT91_CKGR_MCFR);
69b648a2 AV	578	} while (!(tmp & AT91_PMC_MAINRDY));
69b648a2 AV	579	main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
73a59c1c SP	580	}
	581	main_clk.rate_hz = main_clock;
	582
	583	/* report if PLLA is more than mildly overclocked */
	584	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
	585	if (plla.rate_hz > 209000000)
	586	pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
	587
	588	/*
	589	* USB clock init: choose 48 MHz PLLB value, turn all clocks off,
	590	* disable 48MHz clock during usb peripheral suspend.
	591	*
	592	* REVISIT: assumes MCK doesn't derive from PLLB!
	593	*/
69b648a2	594	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) \| AT91_PMC_USB96M;
73a59c1c	595	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
d481f864 AV	596	if (cpu_is_at91rm9200()) {
	597	uhpck.pmc_mask = AT91RM9200_PMC_UHP;
	598	udpck.pmc_mask = AT91RM9200_PMC_UDP;
	599	at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP);
	600	at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
b2c65616	601	} else if (cpu_is_at91sam9260() \|\| cpu_is_at91sam9263()) {
d481f864 AV	602	uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
	603	udpck.pmc_mask = AT91SAM926x_PMC_UDP;
	604	at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP);
	605	} else if (cpu_is_at91sam9261()) {
	606	uhpck.pmc_mask = (AT91SAM926x_PMC_UHP \| AT91_PMC_HCK0);
	607	udpck.pmc_mask = AT91SAM926x_PMC_UDP;
	608	at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP \| AT91_PMC_HCK0 \| AT91SAM926x_PMC_UDP);
	609	}
73a59c1c	610	at91_sys_write(AT91_CKGR_PLLBR, 0);
73a59c1c	611
69b648a2 AV	612	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	613	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	614
73a59c1c SP	615	/*
	616	* MCK and CPU derive from one of those primary clocks.
	617	* For now, assume this parentage won't change.
	618	*/
	619	mckr = at91_sys_read(AT91_PMC_MCKR);
2eeaaa21	620	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
73a59c1c SP	621	freq = mck.parent->rate_hz;
	622	freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
	623	mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
	624
2eeaaa21 AV	625	/* Register the PMC's standard clocks */
	626	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
	627	list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
	628
91f8ed83 AV	629	/* MCK and CPU clock are "always on" */
	630	clk_enable(&mck);
	631
73a59c1c SP	632	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
	633	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
	634	(unsigned) main_clock / 1000000,
	635	((unsigned) main_clock % 1000000) / 1000);
	636
91f8ed83	637	/* disable all programmable clocks */
73a59c1c	638	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 \| AT91_PMC_PCK1 \| AT91_PMC_PCK2 \| AT91_PMC_PCK3);
91f8ed83 AV	639
	640	/* disable all other unused peripheral clocks */
	641	at91_periphclk_reset();
73a59c1c SP	642
	643	return 0;
	644	}