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CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/kernel/ptrace.c
3 *
4 * By Ross Biro 1/23/92
5 * edited by Linus Torvalds
6 * ARM modifications Copyright (C) 2000 Russell King
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
1da177e4
LT
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/smp.h>
1da177e4
LT
16#include <linux/ptrace.h>
17#include <linux/user.h>
18#include <linux/security.h>
19#include <linux/init.h>
7ed20e1a 20#include <linux/signal.h>
33fa9b13 21#include <linux/uaccess.h>
1da177e4 22
1da177e4
LT
23#include <asm/pgtable.h>
24#include <asm/system.h>
25#include <asm/traps.h>
26
27#include "ptrace.h"
28
29#define REG_PC 15
30#define REG_PSR 16
31/*
32 * does not yet catch signals sent when the child dies.
33 * in exit.c or in signal.c.
34 */
35
36#if 0
37/*
38 * Breakpoint SWI instruction: SWI &9F0001
39 */
40#define BREAKINST_ARM 0xef9f0001
41#define BREAKINST_THUMB 0xdf00 /* fill this in later */
42#else
43/*
44 * New breakpoints - use an undefined instruction. The ARM architecture
45 * reference manual guarantees that the following instruction space
46 * will produce an undefined instruction exception on all CPUs:
47 *
48 * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
49 * Thumb: 1101 1110 xxxx xxxx
50 */
51#define BREAKINST_ARM 0xe7f001f0
52#define BREAKINST_THUMB 0xde01
53#endif
54
e513f8bf
WD
55struct pt_regs_offset {
56 const char *name;
57 int offset;
58};
59
60#define REG_OFFSET_NAME(r) \
61 {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
62#define REG_OFFSET_END {.name = NULL, .offset = 0}
63
64static const struct pt_regs_offset regoffset_table[] = {
65 REG_OFFSET_NAME(r0),
66 REG_OFFSET_NAME(r1),
67 REG_OFFSET_NAME(r2),
68 REG_OFFSET_NAME(r3),
69 REG_OFFSET_NAME(r4),
70 REG_OFFSET_NAME(r5),
71 REG_OFFSET_NAME(r6),
72 REG_OFFSET_NAME(r7),
73 REG_OFFSET_NAME(r8),
74 REG_OFFSET_NAME(r9),
75 REG_OFFSET_NAME(r10),
76 REG_OFFSET_NAME(fp),
77 REG_OFFSET_NAME(ip),
78 REG_OFFSET_NAME(sp),
79 REG_OFFSET_NAME(lr),
80 REG_OFFSET_NAME(pc),
81 REG_OFFSET_NAME(cpsr),
82 REG_OFFSET_NAME(ORIG_r0),
83 REG_OFFSET_END,
84};
85
86/**
87 * regs_query_register_offset() - query register offset from its name
88 * @name: the name of a register
89 *
90 * regs_query_register_offset() returns the offset of a register in struct
91 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
92 */
93int regs_query_register_offset(const char *name)
94{
95 const struct pt_regs_offset *roff;
96 for (roff = regoffset_table; roff->name != NULL; roff++)
97 if (!strcmp(roff->name, name))
98 return roff->offset;
99 return -EINVAL;
100}
101
102/**
103 * regs_query_register_name() - query register name from its offset
104 * @offset: the offset of a register in struct pt_regs.
105 *
106 * regs_query_register_name() returns the name of a register from its
107 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
108 */
109const char *regs_query_register_name(unsigned int offset)
110{
111 const struct pt_regs_offset *roff;
112 for (roff = regoffset_table; roff->name != NULL; roff++)
113 if (roff->offset == offset)
114 return roff->name;
115 return NULL;
116}
117
118/**
119 * regs_within_kernel_stack() - check the address in the stack
120 * @regs: pt_regs which contains kernel stack pointer.
121 * @addr: address which is checked.
122 *
123 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
124 * If @addr is within the kernel stack, it returns true. If not, returns false.
125 */
126bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
127{
128 return ((addr & ~(THREAD_SIZE - 1)) ==
129 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
130}
131
132/**
133 * regs_get_kernel_stack_nth() - get Nth entry of the stack
134 * @regs: pt_regs which contains kernel stack pointer.
135 * @n: stack entry number.
136 *
137 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
138 * is specified by @regs. If the @n th entry is NOT in the kernel stack,
139 * this returns 0.
140 */
141unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
142{
143 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
144 addr += n;
145 if (regs_within_kernel_stack(regs, (unsigned long)addr))
146 return *addr;
147 else
148 return 0;
149}
150
1da177e4
LT
151/*
152 * this routine will get a word off of the processes privileged stack.
153 * the offset is how far from the base addr as stored in the THREAD.
154 * this routine assumes that all the privileged stacks are in our
155 * data space.
156 */
157static inline long get_user_reg(struct task_struct *task, int offset)
158{
815d5ec8 159 return task_pt_regs(task)->uregs[offset];
1da177e4
LT
160}
161
162/*
163 * this routine will put a word on the processes privileged stack.
164 * the offset is how far from the base addr as stored in the THREAD.
165 * this routine assumes that all the privileged stacks are in our
166 * data space.
167 */
168static inline int
169put_user_reg(struct task_struct *task, int offset, long data)
170{
815d5ec8 171 struct pt_regs newregs, *regs = task_pt_regs(task);
1da177e4
LT
172 int ret = -EINVAL;
173
174 newregs = *regs;
175 newregs.uregs[offset] = data;
176
177 if (valid_user_regs(&newregs)) {
178 regs->uregs[offset] = data;
179 ret = 0;
180 }
181
182 return ret;
183}
184
185static inline int
186read_u32(struct task_struct *task, unsigned long addr, u32 *res)
187{
188 int ret;
189
190 ret = access_process_vm(task, addr, res, sizeof(*res), 0);
191
192 return ret == sizeof(*res) ? 0 : -EIO;
193}
194
195static inline int
196read_instr(struct task_struct *task, unsigned long addr, u32 *res)
197{
198 int ret;
199
200 if (addr & 1) {
201 u16 val;
202 ret = access_process_vm(task, addr & ~1, &val, sizeof(val), 0);
203 ret = ret == sizeof(val) ? 0 : -EIO;
204 *res = val;
205 } else {
206 u32 val;
207 ret = access_process_vm(task, addr & ~3, &val, sizeof(val), 0);
208 ret = ret == sizeof(val) ? 0 : -EIO;
209 *res = val;
210 }
211 return ret;
212}
213
214/*
215 * Get value of register `rn' (in the instruction)
216 */
217static unsigned long
218ptrace_getrn(struct task_struct *child, unsigned long insn)
219{
220 unsigned int reg = (insn >> 16) & 15;
221 unsigned long val;
222
223 val = get_user_reg(child, reg);
224 if (reg == 15)
1de765c1 225 val += 8;
1da177e4
LT
226
227 return val;
228}
229
230/*
231 * Get value of operand 2 (in an ALU instruction)
232 */
233static unsigned long
234ptrace_getaluop2(struct task_struct *child, unsigned long insn)
235{
236 unsigned long val;
237 int shift;
238 int type;
239
240 if (insn & 1 << 25) {
241 val = insn & 255;
242 shift = (insn >> 8) & 15;
243 type = 3;
244 } else {
245 val = get_user_reg (child, insn & 15);
246
247 if (insn & (1 << 4))
248 shift = (int)get_user_reg (child, (insn >> 8) & 15);
249 else
250 shift = (insn >> 7) & 31;
251
252 type = (insn >> 5) & 3;
253 }
254
255 switch (type) {
256 case 0: val <<= shift; break;
257 case 1: val >>= shift; break;
258 case 2:
259 val = (((signed long)val) >> shift);
260 break;
261 case 3:
262 val = (val >> shift) | (val << (32 - shift));
263 break;
264 }
265 return val;
266}
267
268/*
269 * Get value of operand 2 (in a LDR instruction)
270 */
271static unsigned long
272ptrace_getldrop2(struct task_struct *child, unsigned long insn)
273{
274 unsigned long val;
275 int shift;
276 int type;
277
278 val = get_user_reg(child, insn & 15);
279 shift = (insn >> 7) & 31;
280 type = (insn >> 5) & 3;
281
282 switch (type) {
283 case 0: val <<= shift; break;
284 case 1: val >>= shift; break;
285 case 2:
286 val = (((signed long)val) >> shift);
287 break;
288 case 3:
289 val = (val >> shift) | (val << (32 - shift));
290 break;
291 }
292 return val;
293}
294
295#define OP_MASK 0x01e00000
296#define OP_AND 0x00000000
297#define OP_EOR 0x00200000
298#define OP_SUB 0x00400000
299#define OP_RSB 0x00600000
300#define OP_ADD 0x00800000
301#define OP_ADC 0x00a00000
302#define OP_SBC 0x00c00000
303#define OP_RSC 0x00e00000
304#define OP_ORR 0x01800000
305#define OP_MOV 0x01a00000
306#define OP_BIC 0x01c00000
307#define OP_MVN 0x01e00000
308
309static unsigned long
310get_branch_address(struct task_struct *child, unsigned long pc, unsigned long insn)
311{
312 u32 alt = 0;
313
314 switch (insn & 0x0e000000) {
315 case 0x00000000:
316 case 0x02000000: {
317 /*
318 * data processing
319 */
320 long aluop1, aluop2, ccbit;
321
22f975f4
NV
322 if ((insn & 0x0fffffd0) == 0x012fff10) {
323 /*
324 * bx or blx
325 */
326 alt = get_user_reg(child, insn & 15);
327 break;
328 }
329
330
1da177e4
LT
331 if ((insn & 0xf000) != 0xf000)
332 break;
333
334 aluop1 = ptrace_getrn(child, insn);
335 aluop2 = ptrace_getaluop2(child, insn);
336 ccbit = get_user_reg(child, REG_PSR) & PSR_C_BIT ? 1 : 0;
337
338 switch (insn & OP_MASK) {
339 case OP_AND: alt = aluop1 & aluop2; break;
340 case OP_EOR: alt = aluop1 ^ aluop2; break;
341 case OP_SUB: alt = aluop1 - aluop2; break;
342 case OP_RSB: alt = aluop2 - aluop1; break;
343 case OP_ADD: alt = aluop1 + aluop2; break;
344 case OP_ADC: alt = aluop1 + aluop2 + ccbit; break;
345 case OP_SBC: alt = aluop1 - aluop2 + ccbit; break;
346 case OP_RSC: alt = aluop2 - aluop1 + ccbit; break;
347 case OP_ORR: alt = aluop1 | aluop2; break;
348 case OP_MOV: alt = aluop2; break;
349 case OP_BIC: alt = aluop1 & ~aluop2; break;
350 case OP_MVN: alt = ~aluop2; break;
351 }
352 break;
353 }
354
355 case 0x04000000:
356 case 0x06000000:
357 /*
358 * ldr
359 */
360 if ((insn & 0x0010f000) == 0x0010f000) {
361 unsigned long base;
362
363 base = ptrace_getrn(child, insn);
364 if (insn & 1 << 24) {
365 long aluop2;
366
367 if (insn & 0x02000000)
368 aluop2 = ptrace_getldrop2(child, insn);
369 else
370 aluop2 = insn & 0xfff;
371
372 if (insn & 1 << 23)
373 base += aluop2;
374 else
375 base -= aluop2;
376 }
1de765c1 377 read_u32(child, base, &alt);
1da177e4
LT
378 }
379 break;
380
381 case 0x08000000:
382 /*
383 * ldm
384 */
385 if ((insn & 0x00108000) == 0x00108000) {
386 unsigned long base;
387 unsigned int nr_regs;
388
389 if (insn & (1 << 23)) {
390 nr_regs = hweight16(insn & 65535) << 2;
391
392 if (!(insn & (1 << 24)))
393 nr_regs -= 4;
394 } else {
395 if (insn & (1 << 24))
396 nr_regs = -4;
397 else
398 nr_regs = 0;
399 }
400
401 base = ptrace_getrn(child, insn);
402
1de765c1 403 read_u32(child, base + nr_regs, &alt);
1da177e4
LT
404 break;
405 }
406 break;
407
408 case 0x0a000000: {
409 /*
410 * bl or b
411 */
412 signed long displ;
413 /* It's a branch/branch link: instead of trying to
414 * figure out whether the branch will be taken or not,
415 * we'll put a breakpoint at both locations. This is
416 * simpler, more reliable, and probably not a whole lot
417 * slower than the alternative approach of emulating the
418 * branch.
419 */
420 displ = (insn & 0x00ffffff) << 8;
421 displ = (displ >> 6) + 8;
422 if (displ != 0 && displ != 4)
423 alt = pc + displ;
424 }
425 break;
426 }
427
428 return alt;
429}
430
431static int
432swap_insn(struct task_struct *task, unsigned long addr,
433 void *old_insn, void *new_insn, int size)
434{
435 int ret;
436
437 ret = access_process_vm(task, addr, old_insn, size, 0);
438 if (ret == size)
439 ret = access_process_vm(task, addr, new_insn, size, 1);
440 return ret;
441}
442
443static void
444add_breakpoint(struct task_struct *task, struct debug_info *dbg, unsigned long addr)
445{
446 int nr = dbg->nsaved;
447
448 if (nr < 2) {
449 u32 new_insn = BREAKINST_ARM;
450 int res;
451
452 res = swap_insn(task, addr, &dbg->bp[nr].insn, &new_insn, 4);
453
454 if (res == 4) {
455 dbg->bp[nr].address = addr;
456 dbg->nsaved += 1;
457 }
458 } else
459 printk(KERN_ERR "ptrace: too many breakpoints\n");
460}
461
462/*
463 * Clear one breakpoint in the user program. We copy what the hardware
464 * does and use bit 0 of the address to indicate whether this is a Thumb
465 * breakpoint or an ARM breakpoint.
466 */
467static void clear_breakpoint(struct task_struct *task, struct debug_entry *bp)
468{
469 unsigned long addr = bp->address;
470 union debug_insn old_insn;
471 int ret;
472
473 if (addr & 1) {
474 ret = swap_insn(task, addr & ~1, &old_insn.thumb,
475 &bp->insn.thumb, 2);
476
477 if (ret != 2 || old_insn.thumb != BREAKINST_THUMB)
478 printk(KERN_ERR "%s:%d: corrupted Thumb breakpoint at "
19c5870c
AD
479 "0x%08lx (0x%04x)\n", task->comm,
480 task_pid_nr(task), addr, old_insn.thumb);
1da177e4
LT
481 } else {
482 ret = swap_insn(task, addr & ~3, &old_insn.arm,
483 &bp->insn.arm, 4);
484
485 if (ret != 4 || old_insn.arm != BREAKINST_ARM)
486 printk(KERN_ERR "%s:%d: corrupted ARM breakpoint at "
19c5870c
AD
487 "0x%08lx (0x%08x)\n", task->comm,
488 task_pid_nr(task), addr, old_insn.arm);
1da177e4
LT
489 }
490}
491
492void ptrace_set_bpt(struct task_struct *child)
493{
494 struct pt_regs *regs;
495 unsigned long pc;
496 u32 insn;
497 int res;
498
815d5ec8 499 regs = task_pt_regs(child);
1da177e4
LT
500 pc = instruction_pointer(regs);
501
502 if (thumb_mode(regs)) {
503 printk(KERN_WARNING "ptrace: can't handle thumb mode\n");
504 return;
505 }
506
507 res = read_instr(child, pc, &insn);
508 if (!res) {
509 struct debug_info *dbg = &child->thread.debug;
510 unsigned long alt;
511
512 dbg->nsaved = 0;
513
514 alt = get_branch_address(child, pc, insn);
515 if (alt)
516 add_breakpoint(child, dbg, alt);
517
518 /*
519 * Note that we ignore the result of setting the above
520 * breakpoint since it may fail. When it does, this is
521 * not so much an error, but a forewarning that we may
522 * be receiving a prefetch abort shortly.
523 *
524 * If we don't set this breakpoint here, then we can
525 * lose control of the thread during single stepping.
526 */
527 if (!alt || predicate(insn) != PREDICATE_ALWAYS)
528 add_breakpoint(child, dbg, pc + 4);
529 }
530}
531
532/*
533 * Ensure no single-step breakpoint is pending. Returns non-zero
534 * value if child was being single-stepped.
535 */
536void ptrace_cancel_bpt(struct task_struct *child)
537{
538 int i, nsaved = child->thread.debug.nsaved;
539
540 child->thread.debug.nsaved = 0;
541
542 if (nsaved > 2) {
543 printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
544 nsaved = 2;
545 }
546
547 for (i = 0; i < nsaved; i++)
548 clear_breakpoint(child, &child->thread.debug.bp[i]);
549}
550
440e6ca7
CH
551void user_disable_single_step(struct task_struct *task)
552{
553 task->ptrace &= ~PT_SINGLESTEP;
554 ptrace_cancel_bpt(task);
555}
556
557void user_enable_single_step(struct task_struct *task)
558{
559 task->ptrace |= PT_SINGLESTEP;
560}
561
1da177e4
LT
562/*
563 * Called by kernel/ptrace.c when detaching..
1da177e4
LT
564 */
565void ptrace_disable(struct task_struct *child)
566{
440e6ca7 567 user_disable_single_step(child);
1da177e4
LT
568}
569
570/*
571 * Handle hitting a breakpoint.
572 */
573void ptrace_break(struct task_struct *tsk, struct pt_regs *regs)
574{
575 siginfo_t info;
576
577 ptrace_cancel_bpt(tsk);
578
579 info.si_signo = SIGTRAP;
580 info.si_errno = 0;
581 info.si_code = TRAP_BRKPT;
582 info.si_addr = (void __user *)instruction_pointer(regs);
583
584 force_sig_info(SIGTRAP, &info, tsk);
585}
586
587static int break_trap(struct pt_regs *regs, unsigned int instr)
588{
589 ptrace_break(current, regs);
590 return 0;
591}
592
593static struct undef_hook arm_break_hook = {
594 .instr_mask = 0x0fffffff,
595 .instr_val = 0x07f001f0,
596 .cpsr_mask = PSR_T_BIT,
597 .cpsr_val = 0,
598 .fn = break_trap,
599};
600
601static struct undef_hook thumb_break_hook = {
602 .instr_mask = 0xffff,
603 .instr_val = 0xde01,
604 .cpsr_mask = PSR_T_BIT,
605 .cpsr_val = PSR_T_BIT,
606 .fn = break_trap,
607};
608
d23bc1b3
DJ
609static int thumb2_break_trap(struct pt_regs *regs, unsigned int instr)
610{
611 unsigned int instr2;
612 void __user *pc;
613
614 /* Check the second half of the instruction. */
615 pc = (void __user *)(instruction_pointer(regs) + 2);
616
617 if (processor_mode(regs) == SVC_MODE) {
618 instr2 = *(u16 *) pc;
619 } else {
620 get_user(instr2, (u16 __user *)pc);
621 }
622
623 if (instr2 == 0xa000) {
624 ptrace_break(current, regs);
625 return 0;
626 } else {
627 return 1;
628 }
629}
630
631static struct undef_hook thumb2_break_hook = {
632 .instr_mask = 0xffff,
633 .instr_val = 0xf7f0,
634 .cpsr_mask = PSR_T_BIT,
635 .cpsr_val = PSR_T_BIT,
636 .fn = thumb2_break_trap,
637};
638
1da177e4
LT
639static int __init ptrace_break_init(void)
640{
641 register_undef_hook(&arm_break_hook);
642 register_undef_hook(&thumb_break_hook);
d23bc1b3 643 register_undef_hook(&thumb2_break_hook);
1da177e4
LT
644 return 0;
645}
646
647core_initcall(ptrace_break_init);
648
649/*
650 * Read the word at offset "off" into the "struct user". We
651 * actually access the pt_regs stored on the kernel stack.
652 */
653static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
654 unsigned long __user *ret)
655{
656 unsigned long tmp;
657
658 if (off & 3 || off >= sizeof(struct user))
659 return -EIO;
660
661 tmp = 0;
68b7f715
PB
662 if (off == PT_TEXT_ADDR)
663 tmp = tsk->mm->start_code;
664 else if (off == PT_DATA_ADDR)
665 tmp = tsk->mm->start_data;
666 else if (off == PT_TEXT_END_ADDR)
667 tmp = tsk->mm->end_code;
668 else if (off < sizeof(struct pt_regs))
1da177e4
LT
669 tmp = get_user_reg(tsk, off >> 2);
670
671 return put_user(tmp, ret);
672}
673
674/*
675 * Write the word at offset "off" into "struct user". We
676 * actually access the pt_regs stored on the kernel stack.
677 */
678static int ptrace_write_user(struct task_struct *tsk, unsigned long off,
679 unsigned long val)
680{
681 if (off & 3 || off >= sizeof(struct user))
682 return -EIO;
683
684 if (off >= sizeof(struct pt_regs))
685 return 0;
686
687 return put_user_reg(tsk, off >> 2, val);
688}
689
690/*
691 * Get all user integer registers.
692 */
693static int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
694{
815d5ec8 695 struct pt_regs *regs = task_pt_regs(tsk);
1da177e4
LT
696
697 return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
698}
699
700/*
701 * Set all user integer registers.
702 */
703static int ptrace_setregs(struct task_struct *tsk, void __user *uregs)
704{
705 struct pt_regs newregs;
706 int ret;
707
708 ret = -EFAULT;
709 if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
815d5ec8 710 struct pt_regs *regs = task_pt_regs(tsk);
1da177e4
LT
711
712 ret = -EINVAL;
713 if (valid_user_regs(&newregs)) {
714 *regs = newregs;
715 ret = 0;
716 }
717 }
718
719 return ret;
720}
721
722/*
723 * Get the child FPU state.
724 */
725static int ptrace_getfpregs(struct task_struct *tsk, void __user *ufp)
726{
e7c1b32f 727 return copy_to_user(ufp, &task_thread_info(tsk)->fpstate,
1da177e4
LT
728 sizeof(struct user_fp)) ? -EFAULT : 0;
729}
730
731/*
732 * Set the child FPU state.
733 */
734static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp)
735{
e7c1b32f 736 struct thread_info *thread = task_thread_info(tsk);
1da177e4
LT
737 thread->used_cp[1] = thread->used_cp[2] = 1;
738 return copy_from_user(&thread->fpstate, ufp,
739 sizeof(struct user_fp)) ? -EFAULT : 0;
740}
741
742#ifdef CONFIG_IWMMXT
743
744/*
745 * Get the child iWMMXt state.
746 */
747static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp)
748{
e7c1b32f 749 struct thread_info *thread = task_thread_info(tsk);
1da177e4
LT
750
751 if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT))
752 return -ENODATA;
753 iwmmxt_task_disable(thread); /* force it to ram */
cdaabbd7
RK
754 return copy_to_user(ufp, &thread->fpstate.iwmmxt, IWMMXT_SIZE)
755 ? -EFAULT : 0;
1da177e4
LT
756}
757
758/*
759 * Set the child iWMMXt state.
760 */
761static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp)
762{
e7c1b32f 763 struct thread_info *thread = task_thread_info(tsk);
1da177e4
LT
764
765 if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT))
766 return -EACCES;
767 iwmmxt_task_release(thread); /* force a reload */
17320a96 768 return copy_from_user(&thread->fpstate.iwmmxt, ufp, IWMMXT_SIZE)
cdaabbd7 769 ? -EFAULT : 0;
1da177e4
LT
770}
771
772#endif
773
5429b060
LB
774#ifdef CONFIG_CRUNCH
775/*
776 * Get the child Crunch state.
777 */
778static int ptrace_getcrunchregs(struct task_struct *tsk, void __user *ufp)
779{
780 struct thread_info *thread = task_thread_info(tsk);
781
782 crunch_task_disable(thread); /* force it to ram */
783 return copy_to_user(ufp, &thread->crunchstate, CRUNCH_SIZE)
784 ? -EFAULT : 0;
785}
786
787/*
788 * Set the child Crunch state.
789 */
790static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp)
791{
792 struct thread_info *thread = task_thread_info(tsk);
793
794 crunch_task_release(thread); /* force a reload */
795 return copy_from_user(&thread->crunchstate, ufp, CRUNCH_SIZE)
796 ? -EFAULT : 0;
797}
798#endif
799
3d1228ea
CM
800#ifdef CONFIG_VFP
801/*
802 * Get the child VFP state.
803 */
804static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
805{
806 struct thread_info *thread = task_thread_info(tsk);
807 union vfp_state *vfp = &thread->vfpstate;
808 struct user_vfp __user *ufp = data;
809
ad187f95 810 vfp_sync_hwstate(thread);
3d1228ea
CM
811
812 /* copy the floating point registers */
813 if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
814 sizeof(vfp->hard.fpregs)))
815 return -EFAULT;
816
817 /* copy the status and control register */
818 if (put_user(vfp->hard.fpscr, &ufp->fpscr))
819 return -EFAULT;
820
821 return 0;
822}
823
824/*
825 * Set the child VFP state.
826 */
827static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
828{
829 struct thread_info *thread = task_thread_info(tsk);
830 union vfp_state *vfp = &thread->vfpstate;
831 struct user_vfp __user *ufp = data;
832
ad187f95 833 vfp_sync_hwstate(thread);
3d1228ea
CM
834
835 /* copy the floating point registers */
836 if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
837 sizeof(vfp->hard.fpregs)))
838 return -EFAULT;
839
840 /* copy the status and control register */
841 if (get_user(vfp->hard.fpscr, &ufp->fpscr))
842 return -EFAULT;
843
ad187f95
RK
844 vfp_flush_hwstate(thread);
845
3d1228ea
CM
846 return 0;
847}
848#endif
849
481bed45 850long arch_ptrace(struct task_struct *child, long request, long addr, long data)
1da177e4 851{
1da177e4
LT
852 int ret;
853
854 switch (request) {
1da177e4
LT
855 case PTRACE_PEEKUSR:
856 ret = ptrace_read_user(child, addr, (unsigned long __user *)data);
857 break;
858
1da177e4
LT
859 case PTRACE_POKEUSR:
860 ret = ptrace_write_user(child, addr, data);
861 break;
862
1da177e4
LT
863 case PTRACE_GETREGS:
864 ret = ptrace_getregs(child, (void __user *)data);
865 break;
866
867 case PTRACE_SETREGS:
868 ret = ptrace_setregs(child, (void __user *)data);
869 break;
870
871 case PTRACE_GETFPREGS:
872 ret = ptrace_getfpregs(child, (void __user *)data);
873 break;
874
875 case PTRACE_SETFPREGS:
876 ret = ptrace_setfpregs(child, (void __user *)data);
877 break;
878
879#ifdef CONFIG_IWMMXT
880 case PTRACE_GETWMMXREGS:
881 ret = ptrace_getwmmxregs(child, (void __user *)data);
882 break;
883
884 case PTRACE_SETWMMXREGS:
885 ret = ptrace_setwmmxregs(child, (void __user *)data);
886 break;
887#endif
888
889 case PTRACE_GET_THREAD_AREA:
e7c1b32f 890 ret = put_user(task_thread_info(child)->tp_value,
1da177e4
LT
891 (unsigned long __user *) data);
892 break;
893
3f471126 894 case PTRACE_SET_SYSCALL:
5ba6d3fe 895 task_thread_info(child)->syscall = data;
3f471126 896 ret = 0;
3f471126
NP
897 break;
898
5429b060
LB
899#ifdef CONFIG_CRUNCH
900 case PTRACE_GETCRUNCHREGS:
901 ret = ptrace_getcrunchregs(child, (void __user *)data);
902 break;
903
904 case PTRACE_SETCRUNCHREGS:
905 ret = ptrace_setcrunchregs(child, (void __user *)data);
906 break;
907#endif
908
3d1228ea
CM
909#ifdef CONFIG_VFP
910 case PTRACE_GETVFPREGS:
911 ret = ptrace_getvfpregs(child, (void __user *)data);
912 break;
913
914 case PTRACE_SETVFPREGS:
915 ret = ptrace_setvfpregs(child, (void __user *)data);
916 break;
917#endif
918
1da177e4
LT
919 default:
920 ret = ptrace_request(child, request, addr, data);
921 break;
922 }
923
924 return ret;
925}
926
3f471126 927asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
1da177e4
LT
928{
929 unsigned long ip;
930
931 if (!test_thread_flag(TIF_SYSCALL_TRACE))
3f471126 932 return scno;
1da177e4 933 if (!(current->ptrace & PT_PTRACED))
3f471126 934 return scno;
1da177e4
LT
935
936 /*
937 * Save IP. IP is used to denote syscall entry/exit:
938 * IP = 0 -> entry, = 1 -> exit
939 */
940 ip = regs->ARM_ip;
941 regs->ARM_ip = why;
942
5ba6d3fe 943 current_thread_info()->syscall = scno;
3f471126 944
1da177e4
LT
945 /* the 0x80 provides a way for the tracing parent to distinguish
946 between a syscall stop and SIGTRAP delivery */
947 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
948 ? 0x80 : 0));
949 /*
950 * this isn't the same as continuing with a signal, but it will do
951 * for normal use. strace only continues with a signal if the
952 * stopping signal is not SIGTRAP. -brl
953 */
954 if (current->exit_code) {
955 send_sig(current->exit_code, current, 1);
956 current->exit_code = 0;
957 }
958 regs->ARM_ip = ip;
3f471126 959
5ba6d3fe 960 return current_thread_info()->syscall;
1da177e4 961}