[net-next-2.6.git] / arch / arm / include / asm / system.h

#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H

#ifdef __KERNEL__

#define CPU_ARCH_UNKNOWN	0
#define CPU_ARCH_ARMv3		1
#define CPU_ARCH_ARMv4		2
#define CPU_ARCH_ARMv4T		3
#define CPU_ARCH_ARMv5		4
#define CPU_ARCH_ARMv5T		5
#define CPU_ARCH_ARMv5TE	6
#define CPU_ARCH_ARMv5TEJ	7
#define CPU_ARCH_ARMv6		8
#define CPU_ARCH_ARMv7		9

/*
 * CR1 bits (CP#15 CR1)
 */
#define CR_M	(1 << 0)	/* MMU enable				*/
#define CR_A	(1 << 1)	/* Alignment abort enable		*/
#define CR_C	(1 << 2)	/* Dcache enable			*/
#define CR_W	(1 << 3)	/* Write buffer enable			*/
#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
#define CR_D	(1 << 5)	/* 32-bit data address range		*/
#define CR_L	(1 << 6)	/* Implementation defined		*/
#define CR_B	(1 << 7)	/* Big endian				*/
#define CR_S	(1 << 8)	/* System MMU protection		*/
#define CR_R	(1 << 9)	/* ROM MMU protection			*/
#define CR_F	(1 << 10)	/* Implementation defined		*/
#define CR_Z	(1 << 11)	/* Implementation defined		*/
#define CR_I	(1 << 12)	/* Icache enable			*/
#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
#define CR_DT	(1 << 16)
#define CR_IT	(1 << 18)
#define CR_ST	(1 << 19)
#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
#define CR_U	(1 << 22)	/* Unaligned access operation		*/
#define CR_XP	(1 << 23)	/* Extended page tables			*/
#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
#define CR_AFE	(1 << 29)	/* Access flag enable			*/
#define CR_TE	(1 << 30)	/* Thumb exception enable		*/

/*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust
 * the compiler from one version to another so a bit of paranoia won't hurt.
 * This string is meant to be concatenated with the inline asm string and
 * will cause compilation to stop on mismatch.
 * (for details, see gcc PR 15089)
 */
#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>

#define __exception	__attribute__((section(".exception.text")))

struct thread_info;
struct task_struct;

/* information about the system we're running on */
extern unsigned int system_rev;
extern unsigned int system_serial_low;
extern unsigned int system_serial_high;
extern unsigned int mem_fclk_21285;

struct pt_regs;

void die(const char *msg, struct pt_regs *regs, int err);

struct siginfo;
void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
		unsigned long err, unsigned long trap);

void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
				       struct pt_regs *),
		     int sig, const char *name);

#define xchg(ptr,x) \
	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

extern asmlinkage void __backtrace(void);
extern asmlinkage void c_backtrace(unsigned long fp, int pmode);

struct mm_struct;
extern void show_pte(struct mm_struct *mm, unsigned long addr);
extern void __show_regs(struct pt_regs *);

extern int cpu_architecture(void);
extern void cpu_init(void);

void arm_machine_restart(char mode, const char *cmd);
extern void (*arm_pm_restart)(char str, const char *cmd);

#define UDBG_UNDEFINED	(1 << 0)
#define UDBG_SYSCALL	(1 << 1)
#define UDBG_BADABORT	(1 << 2)
#define UDBG_SEGV	(1 << 3)
#define UDBG_BUS	(1 << 4)

extern unsigned int user_debug;

#if __LINUX_ARM_ARCH__ >= 4
#define vectors_high()	(cr_alignment & CR_V)
#else
#define vectors_high()	(0)
#endif

#if __LINUX_ARM_ARCH__ >= 7
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
				    : : "r" (0) : "memory")
#elif defined(CONFIG_CPU_FA526)
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#else
#define isb() __asm__ __volatile__ ("" : : : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#endif

#if __LINUX_ARM_ARCH__ >= 7 || defined(CONFIG_SMP)
#define mb()		dmb()
#define rmb()		dmb()
#define wmb()		dmb()
#else
#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#endif

#ifndef CONFIG_SMP
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#else
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	wmb()
#endif

#define read_barrier_depends()		do { } while(0)
#define smp_read_barrier_depends()	do { } while(0)

#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
extern unsigned long cr_alignment;	/* defined in entry-armv.S */

static inline unsigned int get_cr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_cr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
	  : : "r" (val) : "cc");
	isb();
}

#ifndef CONFIG_SMP
extern void adjust_cr(unsigned long mask, unsigned long set);
#endif

#define CPACC_FULL(n)		(3 << (n * 2))
#define CPACC_SVC(n)		(1 << (n * 2))
#define CPACC_DISABLE(n)	(0 << (n * 2))

static inline unsigned int get_copro_access(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	  : "=r" (val) : : "cc");
	return val;
}

static inline void set_copro_access(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	  : : "r" (val) : "cc");
	isb();
}

/*
 * switch_mm() may do a full cache flush over the context switch,
 * so enable interrupts over the context switch to avoid high
 * latency.
 */
#define __ARCH_WANT_INTERRUPTS_ON_CTXSW

/*
 * switch_to(prev, next) should switch from task `prev' to `next'
 * `prev' will never be the same as `next'.  schedule() itself
 * contains the memory barrier to tell GCC not to cache `current'.
 */
extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);

#define switch_to(prev,next,last)					\
do {									\
	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
} while (0)

#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
/*
 * On the StrongARM, "swp" is terminally broken since it bypasses the
 * cache totally.  This means that the cache becomes inconsistent, and,
 * since we use normal loads/stores as well, this is really bad.
 * Typically, this causes oopsen in filp_close, but could have other,
 * more disasterous effects.  There are two work-arounds:
 *  1. Disable interrupts and emulate the atomic swap
 *  2. Clean the cache, perform atomic swap, flush the cache
 *
 * We choose (1) since its the "easiest" to achieve here and is not
 * dependent on the processor type.
 *
 * NOTE that this solution won't work on an SMP system, so explcitly
 * forbid it here.
 */
#define swp_is_buggy
#endif

static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
	extern void __bad_xchg(volatile void *, int);
	unsigned long ret;
#ifdef swp_is_buggy
	unsigned long flags;
#endif
#if __LINUX_ARM_ARCH__ >= 6
	unsigned int tmp;
#endif

	smp_mb();

	switch (size) {
#if __LINUX_ARM_ARCH__ >= 6
	case 1:
		asm volatile("@	__xchg1\n"
		"1:	ldrexb	%0, [%3]\n"
		"	strexb	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"1:	ldrex	%0, [%3]\n"
		"	strex	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#elif defined(swp_is_buggy)
#ifdef CONFIG_SMP
#error SMP is not supported on this platform
#endif
	case 1:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned char *)ptr;
		*(volatile unsigned char *)ptr = x;
		raw_local_irq_restore(flags);
		break;

	case 4:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned long *)ptr;
		*(volatile unsigned long *)ptr = x;
		raw_local_irq_restore(flags);
		break;
#else
	case 1:
		asm volatile("@	__xchg1\n"
		"	swpb	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"	swp	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#endif
	default:
		__bad_xchg(ptr, size), ret = 0;
		break;
	}
	smp_mb();

	return ret;
}

extern void disable_hlt(void);
extern void enable_hlt(void);

#include <asm-generic/cmpxchg-local.h>

#if __LINUX_ARM_ARCH__ < 6

#ifdef CONFIG_SMP
#error "SMP is not supported on this platform"
#endif

/*
 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 * them available.
 */
#define cmpxchg_local(ptr, o, n)				  	       \
	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
			(unsigned long)(n), sizeof(*(ptr))))
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))

#ifndef CONFIG_SMP
#include <asm-generic/cmpxchg.h>
#endif

#else	/* __LINUX_ARM_ARCH__ >= 6 */

extern void __bad_cmpxchg(volatile void *ptr, int size);

/*
 * cmpxchg only support 32-bits operands on ARMv6.
 */

static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
				      unsigned long new, int size)
{
	unsigned long oldval, res;

	switch (size) {
#ifdef CONFIG_CPU_32v6K
	case 1:
		do {
			asm volatile("@ __cmpxchg1\n"
			"	ldrexb	%1, [%2]\n"
			"	mov	%0, #0\n"
			"	teq	%1, %3\n"
			"	strexbeq %0, %4, [%2]\n"
				: "=&r" (res), "=&r" (oldval)
				: "r" (ptr), "Ir" (old), "r" (new)
				: "memory", "cc");
		} while (res);
		break;
	case 2:
		do {
			asm volatile("@ __cmpxchg1\n"
			"	ldrexh	%1, [%2]\n"
			"	mov	%0, #0\n"
			"	teq	%1, %3\n"
			"	strexheq %0, %4, [%2]\n"
				: "=&r" (res), "=&r" (oldval)
				: "r" (ptr), "Ir" (old), "r" (new)
				: "memory", "cc");
		} while (res);
		break;
#endif /* CONFIG_CPU_32v6K */
	case 4:
		do {
			asm volatile("@ __cmpxchg4\n"
			"	ldrex	%1, [%2]\n"
			"	mov	%0, #0\n"
			"	teq	%1, %3\n"
			"	strexeq %0, %4, [%2]\n"
				: "=&r" (res), "=&r" (oldval)
				: "r" (ptr), "Ir" (old), "r" (new)
				: "memory", "cc");
		} while (res);
		break;
	default:
		__bad_cmpxchg(ptr, size);
		oldval = 0;
	}

	return oldval;
}

static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
					 unsigned long new, int size)
{
	unsigned long ret;

	smp_mb();
	ret = __cmpxchg(ptr, old, new, size);
	smp_mb();

	return ret;
}

#define cmpxchg(ptr,o,n)						\
	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
					  (unsigned long)(o),		\
					  (unsigned long)(n),		\
					  sizeof(*(ptr))))

static inline unsigned long __cmpxchg_local(volatile void *ptr,
					    unsigned long old,
					    unsigned long new, int size)
{
	unsigned long ret;

	switch (size) {
#ifndef CONFIG_CPU_32v6K
	case 1:
	case 2:
		ret = __cmpxchg_local_generic(ptr, old, new, size);
		break;
#endif	/* !CONFIG_CPU_32v6K */
	default:
		ret = __cmpxchg(ptr, old, new, size);
	}

	return ret;
}

#define cmpxchg_local(ptr,o,n)						\
	((__typeof__(*(ptr)))__cmpxchg_local((ptr),			\
				       (unsigned long)(o),		\
				       (unsigned long)(n),		\
				       sizeof(*(ptr))))

#ifdef CONFIG_CPU_32v6K

/*
 * Note : ARMv7-M (currently unsupported by Linux) does not support
 * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
 * not be allowed to use __cmpxchg64.
 */
static inline unsigned long long __cmpxchg64(volatile void *ptr,
					     unsigned long long old,
					     unsigned long long new)
{
	register unsigned long long oldval asm("r0");
	register unsigned long long __old asm("r2") = old;
	register unsigned long long __new asm("r4") = new;
	unsigned long res;

	do {
		asm volatile(
		"	@ __cmpxchg8\n"
		"	ldrexd	%1, %H1, [%2]\n"
		"	mov	%0, #0\n"
		"	teq	%1, %3\n"
		"	teqeq	%H1, %H3\n"
		"	strexdeq %0, %4, %H4, [%2]\n"
			: "=&r" (res), "=&r" (oldval)
			: "r" (ptr), "Ir" (__old), "r" (__new)
			: "memory", "cc");
	} while (res);

	return oldval;
}

static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
						unsigned long long old,
						unsigned long long new)
{
	unsigned long long ret;

	smp_mb();
	ret = __cmpxchg64(ptr, old, new);
	smp_mb();

	return ret;
}

#define cmpxchg64(ptr,o,n)						\
	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
					    (unsigned long long)(o),	\
					    (unsigned long long)(n)))

#define cmpxchg64_local(ptr,o,n)					\
	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
					 (unsigned long long)(o),	\
					 (unsigned long long)(n)))

#else	/* !CONFIG_CPU_32v6K */

#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))

#endif	/* CONFIG_CPU_32v6K */

#endif	/* __LINUX_ARM_ARCH__ >= 6 */

#endif /* __ASSEMBLY__ */

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_ARM_SYSTEM_H
	2	#define __ASM_ARM_SYSTEM_H
	3
	4	#ifdef __KERNEL__
	5
1da177e4 LT	6	#define CPU_ARCH_UNKNOWN 0
	7	#define CPU_ARCH_ARMv3 1
	8	#define CPU_ARCH_ARMv4 2
	9	#define CPU_ARCH_ARMv4T 3
	10	#define CPU_ARCH_ARMv5 4
	11	#define CPU_ARCH_ARMv5T 5
	12	#define CPU_ARCH_ARMv5TE 6
	13	#define CPU_ARCH_ARMv5TEJ 7
	14	#define CPU_ARCH_ARMv6 8
bbe88886	15	#define CPU_ARCH_ARMv7 9
1da177e4 LT	16
	17	/*
	18	* CR1 bits (CP#15 CR1)
	19	*/
	20	#define CR_M (1 << 0) /* MMU enable */
	21	#define CR_A (1 << 1) /* Alignment abort enable */
	22	#define CR_C (1 << 2) /* Dcache enable */
	23	#define CR_W (1 << 3) /* Write buffer enable */
	24	#define CR_P (1 << 4) /* 32-bit exception handler */
	25	#define CR_D (1 << 5) /* 32-bit data address range */
	26	#define CR_L (1 << 6) /* Implementation defined */
	27	#define CR_B (1 << 7) /* Big endian */
	28	#define CR_S (1 << 8) /* System MMU protection */
	29	#define CR_R (1 << 9) /* ROM MMU protection */
	30	#define CR_F (1 << 10) /* Implementation defined */
	31	#define CR_Z (1 << 11) /* Implementation defined */
	32	#define CR_I (1 << 12) /* Icache enable */
	33	#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
	34	#define CR_RR (1 << 14) /* Round Robin cache replacement */
	35	#define CR_L4 (1 << 15) /* LDR pc can set T bit */
	36	#define CR_DT (1 << 16)
	37	#define CR_IT (1 << 18)
	38	#define CR_ST (1 << 19)
	39	#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
	40	#define CR_U (1 << 22) /* Unaligned access operation */
	41	#define CR_XP (1 << 23) /* Extended page tables */
	42	#define CR_VE (1 << 24) /* Vectored interrupts */
b1cce6b1 RK	43	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	44	#define CR_TRE (1 << 28) /* TEX remap enable */
	45	#define CR_AFE (1 << 29) /* Access flag enable */
	46	#define CR_TE (1 << 30) /* Thumb exception enable */
1da177e4	47
1da177e4 LT	48	/*
	49	* This is used to ensure the compiler did actually allocate the register we
	50	* asked it for some inline assembly sequences. Apparently we can't trust
	51	* the compiler from one version to another so a bit of paranoia won't hurt.
	52	* This string is meant to be concatenated with the inline asm string and
	53	* will cause compilation to stop on mismatch.
	54	* (for details, see gcc PR 15089)
	55	*/
	56	#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
	57
	58	#ifndef __ASSEMBLY__
	59
	60	#include <linux/linkage.h>
255d1f86	61	#include <linux/irqflags.h>
1da177e4	62
7ab3f8d5 RK	63	#define __exception __attribute__((section(".exception.text")))
7ab3f8d5 RK	64
1da177e4 LT	65	struct thread_info;
	66	struct task_struct;
	67
	68	/* information about the system we're running on */
	69	extern unsigned int system_rev;
	70	extern unsigned int system_serial_low;
	71	extern unsigned int system_serial_high;
	72	extern unsigned int mem_fclk_21285;
	73
	74	struct pt_regs;
	75
a9221de6	76	void die(const char msg, struct pt_regs regs, int err);
1da177e4	77
cfb0810e	78	struct siginfo;
1eeb66a1	79	void arm_notify_die(const char str, struct pt_regs regs, struct siginfo *info,
cfb0810e	80	unsigned long err, unsigned long trap);
1da177e4 LT	81
	82	void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
	83	struct pt_regs *),
	84	int sig, const char *name);
	85
1da177e4 LT	86	#define xchg(ptr,x) \
	87	((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	88
1da177e4	89	extern asmlinkage void __backtrace(void);
652a12ef	90	extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
5470dc65 RK	91
5470dc65 RK	92	struct mm_struct;
652a12ef RK	93	extern void show_pte(struct mm_struct *mm, unsigned long addr);
652a12ef RK	94	extern void __show_regs(struct pt_regs *);
1da177e4 LT	95
1da177e4 LT	96	extern int cpu_architecture(void);
36c5ed23	97	extern void cpu_init(void);
1da177e4	98
be093beb RK	99	void arm_machine_restart(char mode, const char *cmd);
be093beb RK	100	extern void (arm_pm_restart)(char str, const char cmd);
74617fb6	101
56660faf CM	102	#define UDBG_UNDEFINED (1 << 0)
	103	#define UDBG_SYSCALL (1 << 1)
	104	#define UDBG_BADABORT (1 << 2)
	105	#define UDBG_SEGV (1 << 3)
	106	#define UDBG_BUS (1 << 4)
	107
	108	extern unsigned int user_debug;
	109
	110	#if __LINUX_ARM_ARCH__ >= 4
	111	#define vectors_high() (cr_alignment & CR_V)
	112	#else
	113	#define vectors_high() (0)
	114	#endif
	115
56163fcf CM	116	#if __LINUX_ARM_ARCH__ >= 7
	117	#define isb() __asm__ __volatile__ ("isb" : : : "memory")
	118	#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
	119	#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
	120	#elif defined(CONFIG_CPU_XSC3) \|\| __LINUX_ARM_ARCH__ == 6
56660faf CM	121	#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
	122	: : "r" (0) : "memory")
	123	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	124	: : "r" (0) : "memory")
	125	#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
	126	: : "r" (0) : "memory")
28853ac8 PZ	127	#elif defined(CONFIG_CPU_FA526)
	128	#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
	129	: : "r" (0) : "memory")
	130	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	131	: : "r" (0) : "memory")
	132	#define dmb() __asm__ __volatile__ ("" : : : "memory")
56660faf CM	133	#else
	134	#define isb() __asm__ __volatile__ ("" : : : "memory")
	135	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	136	: : "r" (0) : "memory")
	137	#define dmb() __asm__ __volatile__ ("" : : : "memory")
	138	#endif
9623b373	139
26a26d32 RK	140	#if __LINUX_ARM_ARCH__ >= 7 \|\| defined(CONFIG_SMP)
	141	#define mb() dmb()
	142	#define rmb() dmb()
	143	#define wmb() dmb()
	144	#else
398e692f LB	145	#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
	146	#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
	147	#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
26a26d32 RK	148	#endif
	149
	150	#ifndef CONFIG_SMP
398e692f LB	151	#define smp_mb() barrier()
	152	#define smp_rmb() barrier()
	153	#define smp_wmb() barrier()
9623b373	154	#else
26a26d32 RK	155	#define smp_mb() mb()
	156	#define smp_rmb() rmb()
	157	#define smp_wmb() wmb()
398e692f	158	#endif
26a26d32	159
398e692f LB	160	#define read_barrier_depends() do { } while(0)
398e692f LB	161	#define smp_read_barrier_depends() do { } while(0)
9623b373 CM	162
9623b373 CM	163	#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
56660faf CM	164	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
56660faf CM	165
255d1f86 RK	166	extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
	167	extern unsigned long cr_alignment; /* defined in entry-armv.S */
	168
efe90d27 RK	169	static inline unsigned int get_cr(void)
	170	{
	171	unsigned int val;
	172	asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
	173	return val;
	174	}
	175
	176	static inline void set_cr(unsigned int val)
	177	{
	178	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
	179	: : "r" (val) : "cc");
56660faf	180	isb();
efe90d27 RK	181	}
efe90d27 RK	182
255d1f86 RK	183	#ifndef CONFIG_SMP
	184	extern void adjust_cr(unsigned long mask, unsigned long set);
	185	#endif
	186
efe90d27 RK	187	#define CPACC_FULL(n) (3 << (n * 2))
	188	#define CPACC_SVC(n) (1 << (n * 2))
	189	#define CPACC_DISABLE(n) (0 << (n * 2))
	190
	191	static inline unsigned int get_copro_access(void)
	192	{
	193	unsigned int val;
	194	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	195	: "=r" (val) : : "cc");
	196	return val;
	197	}
	198
	199	static inline void set_copro_access(unsigned int val)
	200	{
	201	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	202	: : "r" (val) : "cc");
56660faf	203	isb();
efe90d27	204	}
1da177e4	205
1da177e4	206	/*
4866cde0 NP	207	* switch_mm() may do a full cache flush over the context switch,
	208	* so enable interrupts over the context switch to avoid high
	209	* latency.
1da177e4	210	*/
4866cde0	211	#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
1da177e4 LT	212
	213	/*
	214	* switch_to(prev, next) should switch from task `prev' to `next'
	215	* `prev' will never be the same as `next'. schedule() itself
	216	* contains the memory barrier to tell GCC not to cache `current'.
	217	*/
	218	extern struct task_struct __switch_to(struct task_struct , struct thread_info , struct thread_info );
	219
	220	#define switch_to(prev,next,last) \
	221	do { \
e7c1b32f	222	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
1da177e4 LT	223	} while (0)
1da177e4 LT	224
1da177e4 LT	225	#if defined(CONFIG_CPU_SA1100) \|\| defined(CONFIG_CPU_SA110)
	226	/*
	227	* On the StrongARM, "swp" is terminally broken since it bypasses the
	228	* cache totally. This means that the cache becomes inconsistent, and,
	229	* since we use normal loads/stores as well, this is really bad.
	230	* Typically, this causes oopsen in filp_close, but could have other,
	231	* more disasterous effects. There are two work-arounds:
	232	* 1. Disable interrupts and emulate the atomic swap
	233	* 2. Clean the cache, perform atomic swap, flush the cache
	234	*
	235	* We choose (1) since its the "easiest" to achieve here and is not
	236	* dependent on the processor type.
053a7b5b RK	237	*
	238	* NOTE that this solution won't work on an SMP system, so explcitly
	239	* forbid it here.
1da177e4 LT	240	*/
	241	#define swp_is_buggy
	242	#endif
	243
	244	static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
	245	{
	246	extern void __bad_xchg(volatile void *, int);
	247	unsigned long ret;
	248	#ifdef swp_is_buggy
	249	unsigned long flags;
	250	#endif
9560782f RK	251	#if __LINUX_ARM_ARCH__ >= 6
	252	unsigned int tmp;
	253	#endif
1da177e4	254
bac4e960 RK	255	smp_mb();
bac4e960 RK	256
1da177e4	257	switch (size) {
9560782f RK	258	#if __LINUX_ARM_ARCH__ >= 6
	259	case 1:
	260	asm volatile("@ __xchg1\n"
	261	"1: ldrexb %0, [%3]\n"
	262	" strexb %1, %2, [%3]\n"
	263	" teq %1, #0\n"
	264	" bne 1b"
	265	: "=&r" (ret), "=&r" (tmp)
	266	: "r" (x), "r" (ptr)
	267	: "memory", "cc");
	268	break;
	269	case 4:
	270	asm volatile("@ __xchg4\n"
	271	"1: ldrex %0, [%3]\n"
	272	" strex %1, %2, [%3]\n"
	273	" teq %1, #0\n"
	274	" bne 1b"
	275	: "=&r" (ret), "=&r" (tmp)
	276	: "r" (x), "r" (ptr)
	277	: "memory", "cc");
	278	break;
	279	#elif defined(swp_is_buggy)
	280	#ifdef CONFIG_SMP
	281	#error SMP is not supported on this platform
	282	#endif
	283	case 1:
e7cc2c59	284	raw_local_irq_save(flags);
9560782f RK	285	ret = (volatile unsigned char )ptr;
9560782f RK	286	(volatile unsigned char )ptr = x;
e7cc2c59	287	raw_local_irq_restore(flags);
9560782f RK	288	break;
	289
	290	case 4:
e7cc2c59	291	raw_local_irq_save(flags);
9560782f RK	292	ret = (volatile unsigned long )ptr;
9560782f RK	293	(volatile unsigned long )ptr = x;
e7cc2c59	294	raw_local_irq_restore(flags);
9560782f	295	break;
1da177e4	296	#else
9560782f RK	297	case 1:
	298	asm volatile("@ __xchg1\n"
	299	" swpb %0, %1, [%2]"
	300	: "=&r" (ret)
	301	: "r" (x), "r" (ptr)
	302	: "memory", "cc");
	303	break;
	304	case 4:
	305	asm volatile("@ __xchg4\n"
	306	" swp %0, %1, [%2]"
	307	: "=&r" (ret)
	308	: "r" (x), "r" (ptr)
	309	: "memory", "cc");
	310	break;
1da177e4	311	#endif
9560782f RK	312	default:
	313	__bad_xchg(ptr, size), ret = 0;
	314	break;
1da177e4	315	}
bac4e960	316	smp_mb();
1da177e4 LT	317
	318	return ret;
	319	}
	320
dabaeff0 BD	321	extern void disable_hlt(void);
	322	extern void enable_hlt(void);
	323
176393d4 MD	324	#include <asm-generic/cmpxchg-local.h>
176393d4 MD	325
ecd322c9 MD	326	#if __LINUX_ARM_ARCH__ < 6
	327
	328	#ifdef CONFIG_SMP
	329	#error "SMP is not supported on this platform"
	330	#endif
	331
176393d4 MD	332	/*
	333	* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
	334	* them available.
	335	*/
	336	#define cmpxchg_local(ptr, o, n) \
	337	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
	338	(unsigned long)(n), sizeof(*(ptr))))
	339	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
	340
	341	#ifndef CONFIG_SMP
	342	#include <asm-generic/cmpxchg.h>
	343	#endif
	344
ecd322c9 MD	345	#else /* __LINUX_ARM_ARCH__ >= 6 */
	346
	347	extern void __bad_cmpxchg(volatile void *ptr, int size);
	348
	349	/*
	350	* cmpxchg only support 32-bits operands on ARMv6.
	351	*/
	352
	353	static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
	354	unsigned long new, int size)
	355	{
	356	unsigned long oldval, res;
	357
	358	switch (size) {
	359	#ifdef CONFIG_CPU_32v6K
	360	case 1:
	361	do {
	362	asm volatile("@ __cmpxchg1\n"
	363	" ldrexb %1, [%2]\n"
	364	" mov %0, #0\n"
	365	" teq %1, %3\n"
	366	" strexbeq %0, %4, [%2]\n"
	367	: "=&r" (res), "=&r" (oldval)
	368	: "r" (ptr), "Ir" (old), "r" (new)
	369	: "memory", "cc");
	370	} while (res);
	371	break;
	372	case 2:
	373	do {
	374	asm volatile("@ __cmpxchg1\n"
	375	" ldrexh %1, [%2]\n"
	376	" mov %0, #0\n"
	377	" teq %1, %3\n"
	378	" strexheq %0, %4, [%2]\n"
	379	: "=&r" (res), "=&r" (oldval)
	380	: "r" (ptr), "Ir" (old), "r" (new)
	381	: "memory", "cc");
	382	} while (res);
	383	break;
	384	#endif /* CONFIG_CPU_32v6K */
	385	case 4:
	386	do {
	387	asm volatile("@ __cmpxchg4\n"
	388	" ldrex %1, [%2]\n"
	389	" mov %0, #0\n"
	390	" teq %1, %3\n"
	391	" strexeq %0, %4, [%2]\n"
	392	: "=&r" (res), "=&r" (oldval)
	393	: "r" (ptr), "Ir" (old), "r" (new)
	394	: "memory", "cc");
	395	} while (res);
	396	break;
	397	default:
	398	__bad_cmpxchg(ptr, size);
	399	oldval = 0;
	400	}
	401
	402	return oldval;
	403	}
	404
	405	static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
	406	unsigned long new, int size)
	407	{
	408	unsigned long ret;
409
410	smp_mb();
411	ret = __cmpxchg(ptr, old, new, size);
412	smp_mb();
413
414	return ret;
415	}
416
417	#define cmpxchg(ptr,o,n) \
418	((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
419	(unsigned long)(o), \
420	(unsigned long)(n), \
421	sizeof(*(ptr))))
422
423	static inline unsigned long __cmpxchg_local(volatile void *ptr,
424	unsigned long old,
425	unsigned long new, int size)
426	{
427	unsigned long ret;
428
429	switch (size) {
430	#ifndef CONFIG_CPU_32v6K
431	case 1:
432	case 2:
433	ret = __cmpxchg_local_generic(ptr, old, new, size);
434	break;
435	#endif /* !CONFIG_CPU_32v6K */
436	default:
437	ret = __cmpxchg(ptr, old, new, size);
438	}
439
440	return ret;
441	}
442
443	#define cmpxchg_local(ptr,o,n) \
444	((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
445	(unsigned long)(o), \
446	(unsigned long)(n), \
447	sizeof(*(ptr))))
448
449	#ifdef CONFIG_CPU_32v6K
450
451	/*
452	* Note : ARMv7-M (currently unsupported by Linux) does not support
453	* ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
454	* not be allowed to use __cmpxchg64.
455	*/
456	static inline unsigned long long __cmpxchg64(volatile void *ptr,
457	unsigned long long old,
458	unsigned long long new)
459	{
460	register unsigned long long oldval asm("r0");
461	register unsigned long long __old asm("r2") = old;
462	register unsigned long long __new asm("r4") = new;
463	unsigned long res;
464
465	do {
466	asm volatile(
467	" @ __cmpxchg8\n"
468	" ldrexd %1, %H1, [%2]\n"
469	" mov %0, #0\n"
470	" teq %1, %3\n"
471	" teqeq %H1, %H3\n"
472	" strexdeq %0, %4, %H4, [%2]\n"
473	: "=&r" (res), "=&r" (oldval)
474	: "r" (ptr), "Ir" (__old), "r" (__new)
475	: "memory", "cc");
476	} while (res);
477
478	return oldval;
479	}
480
481	static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
482	unsigned long long old,
483	unsigned long long new)
484	{
485	unsigned long long ret;
486
487	smp_mb();
488	ret = __cmpxchg64(ptr, old, new);
489	smp_mb();
490
491	return ret;
492	}
493
494	#define cmpxchg64(ptr,o,n) \
495	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
496	(unsigned long long)(o), \
497	(unsigned long long)(n)))
498
499	#define cmpxchg64_local(ptr,o,n) \
500	((__typeof__(*(ptr)))__cmpxchg64((ptr), \
501	(unsigned long long)(o), \
502	(unsigned long long)(n)))
503
504	#else /* !CONFIG_CPU_32v6K */
505
506	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
507
508	#endif /* CONFIG_CPU_32v6K */
509
510	#endif /* __LINUX_ARM_ARCH__ >= 6 */
511
1da177e4 LT	512	#endif /* __ASSEMBLY__ */
	513
	514	#define arch_align_stack(x) (x)
	515
	516	#endif /* __KERNEL__ */
	517
	518	#endif