[net-next-2.6.git] / arch / arm / include / asm / assembler.h

/*
 *  arch/arm/include/asm/assembler.h
 *
 *  Copyright (C) 1996-2000 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This file contains arm architecture specific defines
 *  for the different processors.
 *
 *  Do not include any C declarations in this file - it is included by
 *  assembler source.
 */
#ifndef __ASSEMBLY__
#error "Only include this from assembly code"
#endif

#include <asm/ptrace.h>

/*
 * Endian independent macros for shifting bytes within registers.
 */
#ifndef __ARMEB__
#define pull            lsr
#define push            lsl
#define get_byte_0      lsl #0
#define get_byte_1	lsr #8
#define get_byte_2	lsr #16
#define get_byte_3	lsr #24
#define put_byte_0      lsl #0
#define put_byte_1	lsl #8
#define put_byte_2	lsl #16
#define put_byte_3	lsl #24
#else
#define pull            lsl
#define push            lsr
#define get_byte_0	lsr #24
#define get_byte_1	lsr #16
#define get_byte_2	lsr #8
#define get_byte_3      lsl #0
#define put_byte_0	lsl #24
#define put_byte_1	lsl #16
#define put_byte_2	lsl #8
#define put_byte_3      lsl #0
#endif

/*
 * Data preload for architectures that support it
 */
#if __LINUX_ARM_ARCH__ >= 5
#define PLD(code...)	code
#else
#define PLD(code...)
#endif

/*
 * This can be used to enable code to cacheline align the destination
 * pointer when bulk writing to memory.  Experiments on StrongARM and
 * XScale didn't show this a worthwhile thing to do when the cache is not
 * set to write-allocate (this would need further testing on XScale when WA
 * is used).
 *
 * On Feroceon there is much to gain however, regardless of cache mode.
 */
#ifdef CONFIG_CPU_FEROCEON
#define CALGN(code...) code
#else
#define CALGN(code...)
#endif

/*
 * Enable and disable interrupts
 */
#if __LINUX_ARM_ARCH__ >= 6
	.macro	disable_irq
	cpsid	i
	.endm

	.macro	enable_irq
	cpsie	i
	.endm
#else
	.macro	disable_irq
	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
	.endm

	.macro	enable_irq
	msr	cpsr_c, #SVC_MODE
	.endm
#endif

/*
 * Save the current IRQ state and disable IRQs.  Note that this macro
 * assumes FIQs are enabled, and that the processor is in SVC mode.
 */
	.macro	save_and_disable_irqs, oldcpsr
	mrs	\oldcpsr, cpsr
	disable_irq
	.endm

/*
 * Restore interrupt state previously stored in a register.  We don't
 * guarantee that this will preserve the flags.
 */
	.macro	restore_irqs, oldcpsr
	msr	cpsr_c, \oldcpsr
	.endm

#define USER(x...)				\
9999:	x;					\
	.section __ex_table,"a";		\
	.align	3;				\
	.long	9999b,9001f;			\
	.previous

/*
 * SMP data memory barrier
 */
	.macro	smp_dmb
#ifdef CONFIG_SMP
#if __LINUX_ARM_ARCH__ >= 7
	dmb
#elif __LINUX_ARM_ARCH__ == 6
	mcr	p15, 0, r0, c7, c10, 5	@ dmb
#endif
#endif
	.endm

#ifdef CONFIG_THUMB2_KERNEL
	.macro	setmode, mode, reg
	mov	\reg, #\mode
	msr	cpsr_c, \reg
	.endm
#else
	.macro	setmode, mode, reg
	msr	cpsr_c, #\mode
	.endm
#endif

/*
 * STRT/LDRT access macros with ARM and Thumb-2 variants
 */
#ifdef CONFIG_THUMB2_KERNEL

	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort
9999:
	.if	\inc == 1
	\instr\cond\()bt \reg, [\ptr, #\off]
	.elseif	\inc == 4
	\instr\cond\()t \reg, [\ptr, #\off]
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.section __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.previous
	.endm

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
	@ explicit IT instruction needed because of the label
	@ introduced by the USER macro
	.ifnc	\cond,al
	.if	\rept == 1
	itt	\cond
	.elseif	\rept == 2
	ittt	\cond
	.else
	.error	"Unsupported rept macro argument"
	.endif
	.endif

	@ Slightly optimised to avoid incrementing the pointer twice
	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
	.if	\rept == 2
	usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort
	.endif

	add\cond \ptr, #\rept * \inc
	.endm

#else	/* !CONFIG_THUMB2_KERNEL */

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
	.rept	\rept
9999:
	.if	\inc == 1
	\instr\cond\()bt \reg, [\ptr], #\inc
	.elseif	\inc == 4
	\instr\cond\()t \reg, [\ptr], #\inc
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.section __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.previous
	.endr
	.endm

#endif	/* CONFIG_THUMB2_KERNEL */

	.macro	strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	str, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm

	.macro	ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	ldr, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/assembler.h
1da177e4 LT	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This file contains arm architecture specific defines
	11	* for the different processors.
	12	*
	13	* Do not include any C declarations in this file - it is included by
	14	* assembler source.
	15	*/
	16	#ifndef __ASSEMBLY__
	17	#error "Only include this from assembly code"
	18	#endif
	19
	20	#include <asm/ptrace.h>
	21
	22	/*
	23	* Endian independent macros for shifting bytes within registers.
	24	*/
	25	#ifndef __ARMEB__
	26	#define pull lsr
	27	#define push lsl
	28	#define get_byte_0 lsl #0
	29	#define get_byte_1 lsr #8
	30	#define get_byte_2 lsr #16
	31	#define get_byte_3 lsr #24
	32	#define put_byte_0 lsl #0
	33	#define put_byte_1 lsl #8
	34	#define put_byte_2 lsl #16
	35	#define put_byte_3 lsl #24
	36	#else
	37	#define pull lsl
	38	#define push lsr
	39	#define get_byte_0 lsr #24
	40	#define get_byte_1 lsr #16
	41	#define get_byte_2 lsr #8
	42	#define get_byte_3 lsl #0
	43	#define put_byte_0 lsl #24
	44	#define put_byte_1 lsl #16
	45	#define put_byte_2 lsl #8
	46	#define put_byte_3 lsl #0
	47	#endif
	48
	49	/*
	50	* Data preload for architectures that support it
	51	*/
	52	#if __LINUX_ARM_ARCH__ >= 5
	53	#define PLD(code...) code
	54	#else
	55	#define PLD(code...)
	56	#endif
	57
2239aff6 NP	58	/*
	59	* This can be used to enable code to cacheline align the destination
	60	* pointer when bulk writing to memory. Experiments on StrongARM and
	61	* XScale didn't show this a worthwhile thing to do when the cache is not
	62	* set to write-allocate (this would need further testing on XScale when WA
	63	* is used).
	64	*
	65	* On Feroceon there is much to gain however, regardless of cache mode.
	66	*/
	67	#ifdef CONFIG_CPU_FEROCEON
	68	#define CALGN(code...) code
	69	#else
	70	#define CALGN(code...)
	71	#endif
	72
1da177e4	73	/*
9c42954d	74	* Enable and disable interrupts
1da177e4	75	*/
59d1ff3b	76	#if __LINUX_ARM_ARCH__ >= 6
9c42954d	77	.macro disable_irq
59d1ff3b	78	cpsid i
9c42954d RK	79	.endm
	80
	81	.macro enable_irq
	82	cpsie i
	83	.endm
59d1ff3b	84	#else
9c42954d RK	85	.macro disable_irq
	86	msr cpsr_c, #PSR_I_BIT \| SVC_MODE
	87	.endm
	88
	89	.macro enable_irq
	90	msr cpsr_c, #SVC_MODE
	91	.endm
59d1ff3b	92	#endif
9c42954d RK	93
	94	/*
	95	* Save the current IRQ state and disable IRQs. Note that this macro
	96	* assumes FIQs are enabled, and that the processor is in SVC mode.
	97	*/
	98	.macro save_and_disable_irqs, oldcpsr
	99	mrs \oldcpsr, cpsr
	100	disable_irq
1da177e4 LT	101	.endm
	102
	103	/*
	104	* Restore interrupt state previously stored in a register. We don't
	105	* guarantee that this will preserve the flags.
	106	*/
	107	.macro restore_irqs, oldcpsr
	108	msr cpsr_c, \oldcpsr
	109	.endm
	110
1da177e4 LT	111	#define USER(x...) \
	112	9999: x; \
	113	.section __ex_table,"a"; \
	114	.align 3; \
	115	.long 9999b,9001f; \
	116	.previous
bac4e960 RK	117
	118	/*
	119	* SMP data memory barrier
	120	*/
	121	.macro smp_dmb
	122	#ifdef CONFIG_SMP
	123	#if __LINUX_ARM_ARCH__ >= 7
	124	dmb
	125	#elif __LINUX_ARM_ARCH__ == 6
	126	mcr p15, 0, r0, c7, c10, 5 @ dmb
	127	#endif
	128	#endif
	129	.endm
b86040a5 CM	130
	131	#ifdef CONFIG_THUMB2_KERNEL
	132	.macro setmode, mode, reg
	133	mov \reg, #\mode
	134	msr cpsr_c, \reg
	135	.endm
	136	#else
	137	.macro setmode, mode, reg
	138	msr cpsr_c, #\mode
	139	.endm
	140	#endif
8b592783 CM	141
	142	/*
	143	* STRT/LDRT access macros with ARM and Thumb-2 variants
	144	*/
	145	#ifdef CONFIG_THUMB2_KERNEL
	146
	147	.macro usraccoff, instr, reg, ptr, inc, off, cond, abort
	148	9999:
	149	.if \inc == 1
	150	\instr\cond\()bt \reg, [\ptr, #\off]
	151	.elseif \inc == 4
	152	\instr\cond\()t \reg, [\ptr, #\off]
	153	.else
	154	.error "Unsupported inc macro argument"
	155	.endif
	156
	157	.section __ex_table,"a"
	158	.align 3
	159	.long 9999b, \abort
	160	.previous
	161	.endm
	162
	163	.macro usracc, instr, reg, ptr, inc, cond, rept, abort
	164	@ explicit IT instruction needed because of the label
	165	@ introduced by the USER macro
	166	.ifnc \cond,al
	167	.if \rept == 1
	168	itt \cond
	169	.elseif \rept == 2
	170	ittt \cond
	171	.else
	172	.error "Unsupported rept macro argument"
	173	.endif
	174	.endif
	175
	176	@ Slightly optimised to avoid incrementing the pointer twice
	177	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
	178	.if \rept == 2
	179	usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort
	180	.endif
	181
	182	add\cond \ptr, #\rept * \inc
	183	.endm
	184
	185	#else /* !CONFIG_THUMB2_KERNEL */
	186
	187	.macro usracc, instr, reg, ptr, inc, cond, rept, abort
	188	.rept \rept
	189	9999:
	190	.if \inc == 1
	191	\instr\cond\()bt \reg, [\ptr], #\inc
	192	.elseif \inc == 4
	193	\instr\cond\()t \reg, [\ptr], #\inc
	194	.else
	195	.error "Unsupported inc macro argument"
	196	.endif
	197
	198	.section __ex_table,"a"
	199	.align 3
	200	.long 9999b, \abort
	201	.previous
	202	.endr
	203	.endm
	204
205	#endif /* CONFIG_THUMB2_KERNEL */
206
207	.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
208	usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
209	.endm
210
211	.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
212	usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
213	.endm