[net-next-2.6.git] / arch / arm / common / it8152.c

/*
 * linux/arch/arm/common/it8152.c
 *
 * Copyright Compulab Ltd, 2002-2007
 * Mike Rapoport <mike@compulab.co.il>
 *
 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
 * (see this file for respective copyrights)
 *
 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
 * and demux code.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ptrace.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/mach/pci.h>
#include <asm/hardware/it8152.h>

#define MAX_SLOTS		21

static void it8152_mask_irq(unsigned int irq)
{
       if (irq >= IT8152_LD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
			    (1 << (irq - IT8152_LD_IRQ(0)))),
			    IT8152_INTC_LDCNIMR);
       } else if (irq >= IT8152_LP_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
			    (1 << (irq - IT8152_LP_IRQ(0)))),
			    IT8152_INTC_LPCNIMR);
       } else if (irq >= IT8152_PD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
			    (1 << (irq - IT8152_PD_IRQ(0)))),
			    IT8152_INTC_PDCNIMR);
       }
}

static void it8152_unmask_irq(unsigned int irq)
{
       if (irq >= IT8152_LD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
			     ~(1 << (irq - IT8152_LD_IRQ(0)))),
			    IT8152_INTC_LDCNIMR);
       } else if (irq >= IT8152_LP_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
			     ~(1 << (irq - IT8152_LP_IRQ(0)))),
			    IT8152_INTC_LPCNIMR);
       } else if (irq >= IT8152_PD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
			     ~(1 << (irq - IT8152_PD_IRQ(0)))),
			    IT8152_INTC_PDCNIMR);
       }
}

static struct irq_chip it8152_irq_chip = {
	.name		= "it8152",
	.ack		= it8152_mask_irq,
	.mask		= it8152_mask_irq,
	.unmask		= it8152_unmask_irq,
};

void it8152_init_irq(void)
{
	int irq;

	__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
	__raw_writel((0), IT8152_INTC_PDCNIRR);
	__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
	__raw_writel((0), IT8152_INTC_LPCNIRR);
	__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
	__raw_writel((0), IT8152_INTC_LDCNIRR);

	for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
		set_irq_chip(irq, &it8152_irq_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
}

void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
       int bits_pd, bits_lp, bits_ld;
       int i;

       while (1) {
	       /* Read all */
	       bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	       bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
	       bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);

	       /* Ack */
	       __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
	       __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
	       __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);

	       if (!(bits_ld | bits_lp | bits_pd)) {
		       /* Re-read to guarantee, that there was a moment of
			  time, when they all three were 0. */
		       bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
		       bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
		       bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
		       if (!(bits_ld | bits_lp | bits_pd))
			       return;
	       }

	       bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
	       while (bits_pd) {
		       i = __ffs(bits_pd);
		       generic_handle_irq(IT8152_PD_IRQ(i));
		       bits_pd &= ~(1 << i);
	       }

	       bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
	       while (bits_lp) {
		       i = __ffs(bits_lp);
		       generic_handle_irq(IT8152_LP_IRQ(i));
		       bits_lp &= ~(1 << i);
	       }

	       bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
	       while (bits_ld) {
		       i = __ffs(bits_ld);
		       generic_handle_irq(IT8152_LD_IRQ(i));
		       bits_ld &= ~(1 << i);
	       }
       }
}

/* mapping for on-chip devices */
int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	    (dev->device == PCI_DEVICE_ID_ITE_8152)) {
		if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
			return IT8152_AUDIO_INT;
		if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
			return IT8152_USB_INT;
		if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
			return IT8152_CDMA_INT;
	}

	return 0;
}

static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
						 unsigned int devfn)
{
	unsigned long addr = 0;

	if (bus->number == 0) {
			if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
				addr = (devfn << 8);
	} else
		addr = (bus->number << 16) | (devfn << 8);

	return addr;
}

static int it8152_pci_read_config(struct pci_bus *bus,
				  unsigned int devfn, int where,
				  int size, u32 *value)
{
	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	u32 v;
	int shift;

	shift = (where & 3);

	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));

	*value = v;

	return PCIBIOS_SUCCESSFUL;
}

static int it8152_pci_write_config(struct pci_bus *bus,
				   unsigned int devfn, int where,
				   int size, u32 value)
{
	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	u32 v, vtemp, mask = 0;
	int shift;

	if (size == 1)
		mask = 0xff;
	if (size == 2)
		mask = 0xffff;

	shift = (where & 3);

	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	vtemp = __raw_readl(IT8152_PCI_CFG_DATA);

	if (mask)
		vtemp &= ~(mask << (8 * shift));
	else
		vtemp = 0;

	v = (value << (8 * shift));
	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	__raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops it8152_ops = {
	.read = it8152_pci_read_config,
	.write = it8152_pci_write_config,
};

static struct resource it8152_io = {
	.name	= "IT8152 PCI I/O region",
	.flags	= IORESOURCE_IO,
};

static struct resource it8152_mem = {
	.name	= "IT8152 PCI memory region",
	.start	= 0x10000000,
	.end	= 0x13e00000,
	.flags	= IORESOURCE_MEM,
};

/*
 * The following functions are needed for DMA bouncing.
 * ITE8152 chip can addrees up to 64MByte, so all the devices
 * connected to ITE8152 (PCI and USB) should have limited DMA window
 */

/*
 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
 * other devices.
 */
static int it8152_pci_platform_notify(struct device *dev)
{
	if (dev->bus == &pci_bus_type) {
		if (dev->dma_mask)
			*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
		dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
		dmabounce_register_dev(dev, 2048, 4096);
	}
	return 0;
}

static int it8152_pci_platform_notify_remove(struct device *dev)
{
	if (dev->bus == &pci_bus_type)
		dmabounce_unregister_dev(dev);

	return 0;
}

int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
{
	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
		__func__, dma_addr, size);
	return (dev->bus == &pci_bus_type) &&
		((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
}

int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
{
	it8152_io.start = IT8152_IO_BASE + 0x12000;
	it8152_io.end	= IT8152_IO_BASE + 0x12000 + 0x100000;

	sys->mem_offset = 0x10000000;
	sys->io_offset  = IT8152_IO_BASE;

	if (request_resource(&ioport_resource, &it8152_io)) {
		printk(KERN_ERR "PCI: unable to allocate IO region\n");
		goto err0;
	}
	if (request_resource(&iomem_resource, &it8152_mem)) {
		printk(KERN_ERR "PCI: unable to allocate memory region\n");
		goto err1;
	}

	sys->resource[0] = &it8152_io;
	sys->resource[1] = &it8152_mem;

	if (platform_notify || platform_notify_remove) {
		printk(KERN_ERR "PCI: Can't use platform_notify\n");
		goto err2;
	}

	platform_notify = it8152_pci_platform_notify;
	platform_notify_remove = it8152_pci_platform_notify_remove;

	return 1;

err2:
	release_resource(&it8152_io);
err1:
	release_resource(&it8152_mem);
err0:
	return -EBUSY;
}

/*
 * If we set up a device for bus mastering, we need to check the latency
 * timer as we don't have even crappy BIOSes to set it properly.
 * The implementation is from arch/i386/pci/i386.c
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;

	/* no need to update on-chip OHCI controller */
	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	    (dev->device == PCI_DEVICE_ID_ITE_8152) &&
	    ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
		return;

	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}


struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
	return pci_scan_bus(nr, &it8152_ops, sys);
}
Commit	Line	Data
a8fc0789 MR	1	/*
	2	* linux/arch/arm/common/it8152.c
	3	*
	4	* Copyright Compulab Ltd, 2002-2007
	5	* Mike Rapoport <mike@compulab.co.il>
	6	*
	7	* The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
	8	* (see this file for respective copyrights)
	9	*
	10	* Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
	11	* and demux code.
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17
	18	#include <linux/sched.h>
	19	#include <linux/kernel.h>
	20	#include <linux/pci.h>
	21	#include <linux/ptrace.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/mm.h>
a8fc0789 MR	24	#include <linux/init.h>
	25	#include <linux/ioport.h>
	26	#include <linux/irq.h>
	27	#include <linux/io.h>
	28
	29	#include <asm/mach/pci.h>
	30	#include <asm/hardware/it8152.h>
	31
	32	#define MAX_SLOTS 21
	33
	34	static void it8152_mask_irq(unsigned int irq)
	35	{
	36	if (irq >= IT8152_LD_IRQ(0)) {
	37	__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) \|
	38	(1 << (irq - IT8152_LD_IRQ(0)))),
	39	IT8152_INTC_LDCNIMR);
	40	} else if (irq >= IT8152_LP_IRQ(0)) {
	41	__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) \|
	42	(1 << (irq - IT8152_LP_IRQ(0)))),
	43	IT8152_INTC_LPCNIMR);
	44	} else if (irq >= IT8152_PD_IRQ(0)) {
	45	__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) \|
	46	(1 << (irq - IT8152_PD_IRQ(0)))),
	47	IT8152_INTC_PDCNIMR);
	48	}
	49	}
	50
	51	static void it8152_unmask_irq(unsigned int irq)
	52	{
	53	if (irq >= IT8152_LD_IRQ(0)) {
	54	__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
	55	~(1 << (irq - IT8152_LD_IRQ(0)))),
	56	IT8152_INTC_LDCNIMR);
	57	} else if (irq >= IT8152_LP_IRQ(0)) {
	58	__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
	59	~(1 << (irq - IT8152_LP_IRQ(0)))),
	60	IT8152_INTC_LPCNIMR);
	61	} else if (irq >= IT8152_PD_IRQ(0)) {
	62	__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
	63	~(1 << (irq - IT8152_PD_IRQ(0)))),
	64	IT8152_INTC_PDCNIMR);
	65	}
	66	}
	67
a8fc0789 MR	68	static struct irq_chip it8152_irq_chip = {
	69	.name = "it8152",
	70	.ack = it8152_mask_irq,
	71	.mask = it8152_mask_irq,
	72	.unmask = it8152_unmask_irq,
	73	};
	74
	75	void it8152_init_irq(void)
	76	{
	77	int irq;
	78
	79	__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
	80	__raw_writel((0), IT8152_INTC_PDCNIRR);
	81	__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
	82	__raw_writel((0), IT8152_INTC_LPCNIRR);
	83	__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
	84	__raw_writel((0), IT8152_INTC_LDCNIRR);
	85
	86	for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
	87	set_irq_chip(irq, &it8152_irq_chip);
	88	set_irq_handler(irq, handle_level_irq);
	89	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	90	}
	91	}
	92
	93	void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
	94	{
	95	int bits_pd, bits_lp, bits_ld;
	96	int i;
	97
a8fc0789 MR	98	while (1) {
	99	/* Read all */
	100	bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	101	bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
	102	bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
	103
	104	/* Ack */
	105	__raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
	106	__raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
	107	__raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
	108
	109	if (!(bits_ld \| bits_lp \| bits_pd)) {
	110	/* Re-read to guarantee, that there was a moment of
	111	time, when they all three were 0. */
	112	bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	113	bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
b6265177	114	bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
a8fc0789 MR	115	if (!(bits_ld \| bits_lp \| bits_pd))
	116	return;
	117	}
	118
	119	bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
	120	while (bits_pd) {
	121	i = __ffs(bits_pd);
d8aa0251	122	generic_handle_irq(IT8152_PD_IRQ(i));
a8fc0789 MR	123	bits_pd &= ~(1 << i);
	124	}
	125
	126	bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
	127	while (bits_lp) {
b6265177	128	i = __ffs(bits_lp);
d8aa0251	129	generic_handle_irq(IT8152_LP_IRQ(i));
a8fc0789 MR	130	bits_lp &= ~(1 << i);
	131	}
	132
	133	bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
	134	while (bits_ld) {
b6265177	135	i = __ffs(bits_ld);
d8aa0251	136	generic_handle_irq(IT8152_LD_IRQ(i));
a8fc0789 MR	137	bits_ld &= ~(1 << i);
	138	}
	139	}
	140	}
	141
	142	/* mapping for on-chip devices */
	143	int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	144	{
	145	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	146	(dev->device == PCI_DEVICE_ID_ITE_8152)) {
	147	if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
	148	return IT8152_AUDIO_INT;
	149	if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
	150	return IT8152_USB_INT;
	151	if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
	152	return IT8152_CDMA_INT;
	153	}
	154
	155	return 0;
	156	}
	157
	158	static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
	159	unsigned int devfn)
	160	{
	161	unsigned long addr = 0;
	162
	163	if (bus->number == 0) {
	164	if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
	165	addr = (devfn << 8);
	166	} else
	167	addr = (bus->number << 16) \| (devfn << 8);
	168
	169	return addr;
	170	}
	171
	172	static int it8152_pci_read_config(struct pci_bus *bus,
	173	unsigned int devfn, int where,
	174	int size, u32 *value)
	175	{
	176	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	177	u32 v;
	178	int shift;
	179
	180	shift = (where & 3);
	181
	182	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	183	v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
	184
	185	*value = v;
	186
	187	return PCIBIOS_SUCCESSFUL;
	188	}
	189
	190	static int it8152_pci_write_config(struct pci_bus *bus,
	191	unsigned int devfn, int where,
	192	int size, u32 value)
	193	{
	194	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	195	u32 v, vtemp, mask = 0;
	196	int shift;
	197
	198	if (size == 1)
	199	mask = 0xff;
	200	if (size == 2)
201	mask = 0xffff;
202
203	shift = (where & 3);
204
205	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
206	vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
207
208	if (mask)
209	vtemp &= ~(mask << (8 * shift));
210	else
211	vtemp = 0;
212
213	v = (value << (8 * shift));
214	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
215	__raw_writel((v \| vtemp), IT8152_PCI_CFG_DATA);
216
217	return PCIBIOS_SUCCESSFUL;
218	}
219
220	static struct pci_ops it8152_ops = {
221	.read = it8152_pci_read_config,
222	.write = it8152_pci_write_config,
223	};
224
225	static struct resource it8152_io = {
226	.name = "IT8152 PCI I/O region",
227	.flags = IORESOURCE_IO,
228	};
229
230	static struct resource it8152_mem = {
231	.name = "IT8152 PCI memory region",
232	.start = 0x10000000,
233	.end = 0x13e00000,
234	.flags = IORESOURCE_MEM,
235	};
236
237	/*
238	* The following functions are needed for DMA bouncing.
239	* ITE8152 chip can addrees up to 64MByte, so all the devices
240	* connected to ITE8152 (PCI and USB) should have limited DMA window
241	*/
242
243	/*
244	* Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
245	* other devices.
246	*/
247	static int it8152_pci_platform_notify(struct device *dev)
248	{
249	if (dev->bus == &pci_bus_type) {
250	if (dev->dma_mask)
251	*dev->dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
252	dev->coherent_dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
253	dmabounce_register_dev(dev, 2048, 4096);
254	}
255	return 0;
256	}
257
258	static int it8152_pci_platform_notify_remove(struct device *dev)
259	{
260	if (dev->bus == &pci_bus_type)
261	dmabounce_unregister_dev(dev);
262
263	return 0;
264	}
265
0485e18b RK	266	int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
	267	{
	268	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
	269	__func__, dma_addr, size);
	270	return (dev->bus == &pci_bus_type) &&
	271	((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
	272	}
	273
a8fc0789 MR	274	int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
	275	{
	276	it8152_io.start = IT8152_IO_BASE + 0x12000;
	277	it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
	278
	279	sys->mem_offset = 0x10000000;
	280	sys->io_offset = IT8152_IO_BASE;
	281
	282	if (request_resource(&ioport_resource, &it8152_io)) {
	283	printk(KERN_ERR "PCI: unable to allocate IO region\n");
	284	goto err0;
	285	}
	286	if (request_resource(&iomem_resource, &it8152_mem)) {
	287	printk(KERN_ERR "PCI: unable to allocate memory region\n");
	288	goto err1;
	289	}
	290
	291	sys->resource[0] = &it8152_io;
	292	sys->resource[1] = &it8152_mem;
	293
	294	if (platform_notify \|\| platform_notify_remove) {
	295	printk(KERN_ERR "PCI: Can't use platform_notify\n");
	296	goto err2;
	297	}
	298
	299	platform_notify = it8152_pci_platform_notify;
	300	platform_notify_remove = it8152_pci_platform_notify_remove;
	301
	302	return 1;
	303
	304	err2:
	305	release_resource(&it8152_io);
	306	err1:
	307	release_resource(&it8152_mem);
	308	err0:
	309	return -EBUSY;
	310	}
	311
	312	/*
	313	* If we set up a device for bus mastering, we need to check the latency
	314	* timer as we don't have even crappy BIOSes to set it properly.
	315	* The implementation is from arch/i386/pci/i386.c
	316	*/
	317	unsigned int pcibios_max_latency = 255;
	318
	319	void pcibios_set_master(struct pci_dev *dev)
	320	{
	321	u8 lat;
	322
	323	/* no need to update on-chip OHCI controller */
	324	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	325	(dev->device == PCI_DEVICE_ID_ITE_8152) &&
	326	((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
	327	return;
	328
	329	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	330	if (lat < 16)
	331	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	332	else if (lat > pcibios_max_latency)
	333	lat = pcibios_max_latency;
	334	else
	335	return;
	336	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	337	pci_name(dev), lat);
338	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
339	}
340
341
342	struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
343	{
344	return pci_scan_bus(nr, &it8152_ops, sys);
345	}
346