[net-next-2.6.git] / arch / arm / common / icst525.c

/*
 *  linux/arch/arm/common/icst525.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Support functions for calculating clocks/divisors for the ICST525
 *  clock generators.  See http://www.icst.com/ for more information
 *  on these devices.
 */
#include <linux/module.h>
#include <linux/kernel.h>

#include <asm/hardware/icst525.h>

/*
 * Divisors for each OD setting.
 */
const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };

EXPORT_SYMBOL(icst525_s2div);

unsigned long icst525_hz(const struct icst_params *p, struct icst_vco vco)
{
	return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]);
}

EXPORT_SYMBOL(icst525_hz);

/*
 * Ascending divisor S values.
 */
const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };

EXPORT_SYMBOL(icst525_idx2s);

struct icst_vco
icst525_hz_to_vco(const struct icst_params *p, unsigned long freq)
{
	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
	unsigned long f;
	unsigned int i = 0, rd, best = (unsigned int)-1;

	/*
	 * First, find the PLL output divisor such
	 * that the PLL output is within spec.
	 */
	do {
		f = freq * p->s2div[p->idx2s[i]];

		/*
		 * f must be between 10MHz and
		 *  320MHz (5V) or 200MHz (3V)
		 */
		if (f > p->vco_min && f <= p->vco_max)
			break;
	} while (i < 8);

	if (i >= 8)
		return vco;

	vco.s = p->idx2s[i];

	/*
	 * Now find the closest divisor combination
	 * which gives a PLL output of 'f'.
	 */
	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
		unsigned long fref_div, f_pll;
		unsigned int vd;
		int f_diff;

		fref_div = (2 * p->ref) / rd;

		vd = (f + fref_div / 2) / fref_div;
		if (vd < p->vd_min || vd > p->vd_max)
			continue;

		f_pll = fref_div * vd;
		f_diff = f_pll - f;
		if (f_diff < 0)
			f_diff = -f_diff;

		if ((unsigned)f_diff < best) {
			vco.v = vd - 8;
			vco.r = rd - 2;
			if (f_diff == 0)
				break;
			best = f_diff;
		}
	}

	return vco;
}

EXPORT_SYMBOL(icst525_hz_to_vco);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/common/icst525.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Support functions for calculating clocks/divisors for the ICST525
	11	* clock generators. See http://www.icst.com/ for more information
	12	* on these devices.
	13	*/
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16
	17	#include <asm/hardware/icst525.h>
	18
	19	/*
	20	* Divisors for each OD setting.
	21	*/
232eaf7f RK	22	const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
	23
	24	EXPORT_SYMBOL(icst525_s2div);
1da177e4	25
64fceb1d	26	unsigned long icst525_hz(const struct icst_params *p, struct icst_vco vco)
1da177e4	27	{
232eaf7f	28	return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]);
1da177e4 LT	29	}
1da177e4 LT	30
64fceb1d	31	EXPORT_SYMBOL(icst525_hz);
1da177e4 LT	32
	33	/*
	34	* Ascending divisor S values.
	35	*/
232eaf7f RK	36	const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
	37
	38	EXPORT_SYMBOL(icst525_idx2s);
1da177e4	39
39c0cb02	40	struct icst_vco
64fceb1d	41	icst525_hz_to_vco(const struct icst_params *p, unsigned long freq)
1da177e4	42	{
39c0cb02	43	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
1da177e4 LT	44	unsigned long f;
	45	unsigned int i = 0, rd, best = (unsigned int)-1;
	46
	47	/*
	48	* First, find the PLL output divisor such
	49	* that the PLL output is within spec.
	50	*/
	51	do {
232eaf7f	52	f = freq * p->s2div[p->idx2s[i]];
1da177e4 LT	53
	54	/*
	55	* f must be between 10MHz and
	56	* 320MHz (5V) or 200MHz (3V)
	57	*/
e73a46a3	58	if (f > p->vco_min && f <= p->vco_max)
1da177e4	59	break;
232eaf7f	60	} while (i < 8);
1da177e4	61
232eaf7f	62	if (i >= 8)
1da177e4 LT	63	return vco;
1da177e4 LT	64
232eaf7f	65	vco.s = p->idx2s[i];
1da177e4 LT	66
	67	/*
	68	* Now find the closest divisor combination
	69	* which gives a PLL output of 'f'.
	70	*/
	71	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
	72	unsigned long fref_div, f_pll;
	73	unsigned int vd;
	74	int f_diff;
	75
	76	fref_div = (2 * p->ref) / rd;
	77
	78	vd = (f + fref_div / 2) / fref_div;
	79	if (vd < p->vd_min \|\| vd > p->vd_max)
	80	continue;
	81
	82	f_pll = fref_div * vd;
	83	f_diff = f_pll - f;
	84	if (f_diff < 0)
	85	f_diff = -f_diff;
	86
	87	if ((unsigned)f_diff < best) {
	88	vco.v = vd - 8;
	89	vco.r = rd - 2;
	90	if (f_diff == 0)
	91	break;
	92	best = f_diff;
	93	}
	94	}
	95
	96	return vco;
	97	}
	98
64fceb1d	99	EXPORT_SYMBOL(icst525_hz_to_vco);