[net-next-2.6.git] / arch / arm / common / icst307.c

/*
 *  linux/arch/arm/common/icst307.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Support functions for calculating clocks/divisors for the ICST307
 *  clock generators.  See http://www.icst.com/ for more information
 *  on these devices.
 *
 *  This is an almost identical implementation to the ICST525 clock generator.
 *  The s2div and idx2s files are different
 */
#include <linux/module.h>
#include <linux/kernel.h>

#include <asm/hardware/icst307.h>

/*
 * Divisors for each OD setting.
 */
static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };

unsigned long icst307_hz(const struct icst_params *p, struct icst_vco vco)
{
	return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
}

EXPORT_SYMBOL(icst307_hz);

/*
 * Ascending divisor S values.
 */
static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };

struct icst_vco
icst307_hz_to_vco(const struct icst_params *p, unsigned long freq)
{
	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
	unsigned long f;
	unsigned int i = 0, rd, best = (unsigned int)-1;

	/*
	 * First, find the PLL output divisor such
	 * that the PLL output is within spec.
	 */
	do {
		f = freq * s2div[idx2s[i]];

		/*
		 * f must be between 6MHz and 200MHz (3.3 or 5V)
		 */
		if (f > p->vco_min && f <= p->vco_max)
			break;
	} while (i < ARRAY_SIZE(idx2s));

	if (i >= ARRAY_SIZE(idx2s))
		return vco;

	vco.s = idx2s[i];

	/*
	 * Now find the closest divisor combination
	 * which gives a PLL output of 'f'.
	 */
	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
		unsigned long fref_div, f_pll;
		unsigned int vd;
		int f_diff;

		fref_div = (2 * p->ref) / rd;

		vd = (f + fref_div / 2) / fref_div;
		if (vd < p->vd_min || vd > p->vd_max)
			continue;

		f_pll = fref_div * vd;
		f_diff = f_pll - f;
		if (f_diff < 0)
			f_diff = -f_diff;

		if ((unsigned)f_diff < best) {
			vco.v = vd - 8;
			vco.r = rd - 2;
			if (f_diff == 0)
				break;
			best = f_diff;
		}
	}

	return vco;
}

EXPORT_SYMBOL(icst307_hz_to_vco);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/common/icst307.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Support functions for calculating clocks/divisors for the ICST307
	11	* clock generators. See http://www.icst.com/ for more information
	12	* on these devices.
	13	*
	14	* This is an almost identical implementation to the ICST525 clock generator.
	15	* The s2div and idx2s files are different
	16	*/
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19
	20	#include <asm/hardware/icst307.h>
	21
	22	/*
	23	* Divisors for each OD setting.
	24	*/
	25	static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
	26
64fceb1d	27	unsigned long icst307_hz(const struct icst_params *p, struct icst_vco vco)
1da177e4 LT	28	{
	29	return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
	30	}
	31
64fceb1d	32	EXPORT_SYMBOL(icst307_hz);
1da177e4 LT	33
	34	/*
	35	* Ascending divisor S values.
	36	*/
	37	static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
	38
39c0cb02	39	struct icst_vco
64fceb1d	40	icst307_hz_to_vco(const struct icst_params *p, unsigned long freq)
1da177e4	41	{
39c0cb02	42	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
1da177e4 LT	43	unsigned long f;
	44	unsigned int i = 0, rd, best = (unsigned int)-1;
	45
	46	/*
	47	* First, find the PLL output divisor such
	48	* that the PLL output is within spec.
	49	*/
	50	do {
	51	f = freq * s2div[idx2s[i]];
	52
	53	/*
	54	* f must be between 6MHz and 200MHz (3.3 or 5V)
	55	*/
e73a46a3	56	if (f > p->vco_min && f <= p->vco_max)
1da177e4 LT	57	break;
	58	} while (i < ARRAY_SIZE(idx2s));
	59
d1d8f7de	60	if (i >= ARRAY_SIZE(idx2s))
1da177e4 LT	61	return vco;
	62
	63	vco.s = idx2s[i];
	64
	65	/*
	66	* Now find the closest divisor combination
	67	* which gives a PLL output of 'f'.
	68	*/
	69	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
	70	unsigned long fref_div, f_pll;
	71	unsigned int vd;
	72	int f_diff;
	73
	74	fref_div = (2 * p->ref) / rd;
	75
	76	vd = (f + fref_div / 2) / fref_div;
	77	if (vd < p->vd_min \|\| vd > p->vd_max)
	78	continue;
	79
	80	f_pll = fref_div * vd;
	81	f_diff = f_pll - f;
	82	if (f_diff < 0)
	83	f_diff = -f_diff;
	84
	85	if ((unsigned)f_diff < best) {
	86	vco.v = vd - 8;
	87	vco.r = rd - 2;
	88	if (f_diff == 0)
	89	break;
	90	best = f_diff;
	91	}
	92	}
	93
	94	return vco;
	95	}
	96
64fceb1d	97	EXPORT_SYMBOL(icst307_hz_to_vco);