[net-next-2.6.git] / arch / alpha / include / asm / spinlock.h

#ifndef _ALPHA_SPINLOCK_H
#define _ALPHA_SPINLOCK_H

#include <asm/system.h>
#include <linux/kernel.h>
#include <asm/current.h>

/*
 * Simple spin lock operations.  There are two variants, one clears IRQ's
 * on the local processor, one does not.
 *
 * We make no fairness assumptions. They have a cost.
 */

#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
#define __raw_spin_is_locked(x)	((x)->lock != 0)
#define __raw_spin_unlock_wait(x) \
		do { cpu_relax(); } while ((x)->lock)

static inline void __raw_spin_unlock(raw_spinlock_t * lock)
{
	mb();
	lock->lock = 0;
}

static inline void __raw_spin_lock(raw_spinlock_t * lock)
{
	long tmp;

	__asm__ __volatile__(
	"1:	ldl_l	%0,%1\n"
	"	bne	%0,2f\n"
	"	lda	%0,1\n"
	"	stl_c	%0,%1\n"
	"	beq	%0,2f\n"
	"	mb\n"
	".subsection 2\n"
	"2:	ldl	%0,%1\n"
	"	bne	%0,2b\n"
	"	br	1b\n"
	".previous"
	: "=&r" (tmp), "=m" (lock->lock)
	: "m"(lock->lock) : "memory");
}

static inline int __raw_spin_trylock(raw_spinlock_t *lock)
{
	return !test_and_set_bit(0, &lock->lock);
}

/***********************************************************/

static inline int __raw_read_can_lock(raw_rwlock_t *lock)
{
	return (lock->lock & 1) == 0;
}

static inline int __raw_write_can_lock(raw_rwlock_t *lock)
{
	return lock->lock == 0;
}

static inline void __raw_read_lock(raw_rwlock_t *lock)
{
	long regx;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	blbs	%1,6f\n"
	"	subl	%1,2,%1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	"	mb\n"
	".subsection 2\n"
	"6:	ldl	%1,%0\n"
	"	blbs	%1,6b\n"
	"	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline void __raw_write_lock(raw_rwlock_t *lock)
{
	long regx;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	bne	%1,6f\n"
	"	lda	%1,1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	"	mb\n"
	".subsection 2\n"
	"6:	ldl	%1,%0\n"
	"	bne	%1,6b\n"
	"	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline int __raw_read_trylock(raw_rwlock_t * lock)
{
	long regx;
	int success;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	lda	%2,0\n"
	"	blbs	%1,2f\n"
	"	subl	%1,2,%2\n"
	"	stl_c	%2,%0\n"
	"	beq	%2,6f\n"
	"2:	mb\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	: "m" (*lock) : "memory");

	return success;
}

static inline int __raw_write_trylock(raw_rwlock_t * lock)
{
	long regx;
	int success;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	lda	%2,0\n"
	"	bne	%1,2f\n"
	"	lda	%2,1\n"
	"	stl_c	%2,%0\n"
	"	beq	%2,6f\n"
	"2:	mb\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	: "m" (*lock) : "memory");

	return success;
}

static inline void __raw_read_unlock(raw_rwlock_t * lock)
{
	long regx;
	__asm__ __volatile__(
	"	mb\n"
	"1:	ldl_l	%1,%0\n"
	"	addl	%1,2,%1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline void __raw_write_unlock(raw_rwlock_t * lock)
{
	mb();
	lock->lock = 0;
}

#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)

#define _raw_spin_relax(lock)	cpu_relax()
#define _raw_read_relax(lock)	cpu_relax()
#define _raw_write_relax(lock)	cpu_relax()

#endif /* _ALPHA_SPINLOCK_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ALPHA_SPINLOCK_H
	2	#define _ALPHA_SPINLOCK_H
	3
1da177e4 LT	4	#include <asm/system.h>
	5	#include <linux/kernel.h>
	6	#include <asm/current.h>
	7
1da177e4 LT	8	/*
	9	* Simple spin lock operations. There are two variants, one clears IRQ's
	10	* on the local processor, one does not.
	11	*
	12	* We make no fairness assumptions. They have a cost.
	13	*/
	14
fb1c8f93 IM	15	#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
	16	#define __raw_spin_is_locked(x) ((x)->lock != 0)
	17	#define __raw_spin_unlock_wait(x) \
	18	do { cpu_relax(); } while ((x)->lock)
	19
	20	static inline void __raw_spin_unlock(raw_spinlock_t * lock)
1da177e4 LT	21	{
	22	mb();
	23	lock->lock = 0;
	24	}
	25
fb1c8f93	26	static inline void __raw_spin_lock(raw_spinlock_t * lock)
1da177e4 LT	27	{
	28	long tmp;
	29
	30	__asm__ __volatile__(
	31	"1: ldl_l %0,%1\n"
	32	" bne %0,2f\n"
	33	" lda %0,1\n"
	34	" stl_c %0,%1\n"
	35	" beq %0,2f\n"
	36	" mb\n"
	37	".subsection 2\n"
	38	"2: ldl %0,%1\n"
	39	" bne %0,2b\n"
	40	" br 1b\n"
	41	".previous"
	42	: "=&r" (tmp), "=m" (lock->lock)
	43	: "m"(lock->lock) : "memory");
	44	}
	45
fb1c8f93	46	static inline int __raw_spin_trylock(raw_spinlock_t *lock)
1da177e4 LT	47	{
	48	return !test_and_set_bit(0, &lock->lock);
	49	}
1da177e4 LT	50
	51	/***********************************************************/
	52
fb1c8f93	53	static inline int __raw_read_can_lock(raw_rwlock_t *lock)
1da177e4 LT	54	{
	55	return (lock->lock & 1) == 0;
	56	}
	57
fb1c8f93	58	static inline int __raw_write_can_lock(raw_rwlock_t *lock)
1da177e4 LT	59	{
	60	return lock->lock == 0;
	61	}
	62
fb1c8f93	63	static inline void __raw_read_lock(raw_rwlock_t *lock)
1da177e4 LT	64	{
	65	long regx;
	66
	67	__asm__ __volatile__(
	68	"1: ldl_l %1,%0\n"
fb1c8f93 IM	69	" blbs %1,6f\n"
fb1c8f93 IM	70	" subl %1,2,%1\n"
1da177e4 LT	71	" stl_c %1,%0\n"
	72	" beq %1,6f\n"
	73	" mb\n"
	74	".subsection 2\n"
	75	"6: ldl %1,%0\n"
fb1c8f93	76	" blbs %1,6b\n"
1da177e4 LT	77	" br 1b\n"
	78	".previous"
	79	: "=m" (*lock), "=&r" (regx)
	80	: "m" (*lock) : "memory");
	81	}
	82
fb1c8f93	83	static inline void __raw_write_lock(raw_rwlock_t *lock)
1da177e4 LT	84	{
	85	long regx;
	86
	87	__asm__ __volatile__(
	88	"1: ldl_l %1,%0\n"
fb1c8f93 IM	89	" bne %1,6f\n"
fb1c8f93 IM	90	" lda %1,1\n"
1da177e4 LT	91	" stl_c %1,%0\n"
	92	" beq %1,6f\n"
	93	" mb\n"
	94	".subsection 2\n"
	95	"6: ldl %1,%0\n"
fb1c8f93	96	" bne %1,6b\n"
1da177e4 LT	97	" br 1b\n"
	98	".previous"
	99	: "=m" (*lock), "=&r" (regx)
	100	: "m" (*lock) : "memory");
	101	}
1da177e4	102
fb1c8f93	103	static inline int __raw_read_trylock(raw_rwlock_t * lock)
1da177e4 LT	104	{
	105	long regx;
	106	int success;
	107
	108	__asm__ __volatile__(
	109	"1: ldl_l %1,%0\n"
	110	" lda %2,0\n"
	111	" blbs %1,2f\n"
	112	" subl %1,2,%2\n"
	113	" stl_c %2,%0\n"
	114	" beq %2,6f\n"
	115	"2: mb\n"
	116	".subsection 2\n"
	117	"6: br 1b\n"
	118	".previous"
	119	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	120	: "m" (*lock) : "memory");
	121
	122	return success;
	123	}
	124
fb1c8f93	125	static inline int __raw_write_trylock(raw_rwlock_t * lock)
1da177e4 LT	126	{
	127	long regx;
	128	int success;
	129
	130	__asm__ __volatile__(
	131	"1: ldl_l %1,%0\n"
	132	" lda %2,0\n"
	133	" bne %1,2f\n"
	134	" lda %2,1\n"
	135	" stl_c %2,%0\n"
	136	" beq %2,6f\n"
	137	"2: mb\n"
	138	".subsection 2\n"
	139	"6: br 1b\n"
	140	".previous"
	141	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	142	: "m" (*lock) : "memory");
	143
	144	return success;
	145	}
	146
fb1c8f93	147	static inline void __raw_read_unlock(raw_rwlock_t * lock)
1da177e4 LT	148	{
	149	long regx;
	150	__asm__ __volatile__(
	151	" mb\n"
	152	"1: ldl_l %1,%0\n"
	153	" addl %1,2,%1\n"
	154	" stl_c %1,%0\n"
	155	" beq %1,6f\n"
	156	".subsection 2\n"
	157	"6: br 1b\n"
	158	".previous"
	159	: "=m" (*lock), "=&r" (regx)
	160	: "m" (*lock) : "memory");
	161	}
	162
fb1c8f93 IM	163	static inline void __raw_write_unlock(raw_rwlock_t * lock)
	164	{
	165	mb();
	166	lock->lock = 0;
	167	}
	168
f5f7eac4 RH	169	#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
	170	#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
	171
ef6edc97 MS	172	#define _raw_spin_relax(lock) cpu_relax()
	173	#define _raw_read_relax(lock) cpu_relax()
	174	#define _raw_write_relax(lock) cpu_relax()
	175
1da177e4	176	#endif /* _ALPHA_SPINLOCK_H */